rcar-sysc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car SYSC Power management support
  4. *
  5. * Copyright (C) 2014 Magnus Damm
  6. * Copyright (C) 2015-2017 Glider bvba
  7. */
  8. #include <linux/clk/renesas.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/mm.h>
  12. #include <linux/of_address.h>
  13. #include <linux/pm_domain.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/io.h>
  17. #include <linux/soc/renesas/rcar-sysc.h>
  18. #include "rcar-sysc.h"
  19. /* SYSC Common */
  20. #define SYSCSR 0x00 /* SYSC Status Register */
  21. #define SYSCISR 0x04 /* Interrupt Status Register */
  22. #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
  23. #define SYSCIER 0x0c /* Interrupt Enable Register */
  24. #define SYSCIMR 0x10 /* Interrupt Mask Register */
  25. /* SYSC Status Register */
  26. #define SYSCSR_PONENB 1 /* Ready for power resume requests */
  27. #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
  28. /*
  29. * Power Control Register Offsets inside the register block for each domain
  30. * Note: The "CR" registers for ARM cores exist on H1 only
  31. * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
  32. * Use PSCI on R-Car Gen3
  33. */
  34. #define PWRSR_OFFS 0x00 /* Power Status Register */
  35. #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
  36. #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
  37. #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
  38. #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
  39. #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
  40. #define SYSCSR_RETRIES 100
  41. #define SYSCSR_DELAY_US 1
  42. #define PWRER_RETRIES 100
  43. #define PWRER_DELAY_US 1
  44. #define SYSCISR_RETRIES 1000
  45. #define SYSCISR_DELAY_US 1
  46. #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
  47. struct rcar_sysc_ch {
  48. u16 chan_offs;
  49. u8 chan_bit;
  50. u8 isr_bit;
  51. };
  52. static void __iomem *rcar_sysc_base;
  53. static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
  54. static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
  55. static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
  56. {
  57. unsigned int sr_bit, reg_offs;
  58. int k;
  59. if (on) {
  60. sr_bit = SYSCSR_PONENB;
  61. reg_offs = PWRONCR_OFFS;
  62. } else {
  63. sr_bit = SYSCSR_POFFENB;
  64. reg_offs = PWROFFCR_OFFS;
  65. }
  66. /* Wait until SYSC is ready to accept a power request */
  67. for (k = 0; k < SYSCSR_RETRIES; k++) {
  68. if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
  69. break;
  70. udelay(SYSCSR_DELAY_US);
  71. }
  72. if (k == SYSCSR_RETRIES)
  73. return -EAGAIN;
  74. /* Submit power shutoff or power resume request */
  75. iowrite32(BIT(sysc_ch->chan_bit),
  76. rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
  77. return 0;
  78. }
  79. static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
  80. {
  81. unsigned int isr_mask = BIT(sysc_ch->isr_bit);
  82. unsigned int chan_mask = BIT(sysc_ch->chan_bit);
  83. unsigned int status;
  84. unsigned long flags;
  85. int ret = 0;
  86. int k;
  87. spin_lock_irqsave(&rcar_sysc_lock, flags);
  88. /*
  89. * Mask external power requests for CPU or 3DG domains
  90. */
  91. if (rcar_sysc_extmask_val) {
  92. iowrite32(rcar_sysc_extmask_val,
  93. rcar_sysc_base + rcar_sysc_extmask_offs);
  94. }
  95. /*
  96. * The interrupt source needs to be enabled, but masked, to prevent the
  97. * CPU from receiving it.
  98. */
  99. iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
  100. rcar_sysc_base + SYSCIMR);
  101. iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
  102. rcar_sysc_base + SYSCIER);
  103. iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
  104. /* Submit power shutoff or resume request until it was accepted */
  105. for (k = 0; k < PWRER_RETRIES; k++) {
  106. ret = rcar_sysc_pwr_on_off(sysc_ch, on);
  107. if (ret)
  108. goto out;
  109. status = ioread32(rcar_sysc_base +
  110. sysc_ch->chan_offs + PWRER_OFFS);
  111. if (!(status & chan_mask))
  112. break;
  113. udelay(PWRER_DELAY_US);
  114. }
  115. if (k == PWRER_RETRIES) {
  116. ret = -EIO;
  117. goto out;
  118. }
  119. /* Wait until the power shutoff or resume request has completed * */
  120. for (k = 0; k < SYSCISR_RETRIES; k++) {
  121. if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
  122. break;
  123. udelay(SYSCISR_DELAY_US);
  124. }
  125. if (k == SYSCISR_RETRIES)
  126. ret = -EIO;
  127. iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
  128. out:
  129. if (rcar_sysc_extmask_val)
  130. iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
  131. spin_unlock_irqrestore(&rcar_sysc_lock, flags);
  132. pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
  133. sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
  134. return ret;
  135. }
  136. static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
  137. {
  138. unsigned int st;
  139. st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
  140. if (st & BIT(sysc_ch->chan_bit))
  141. return true;
  142. return false;
  143. }
  144. struct rcar_sysc_pd {
  145. struct generic_pm_domain genpd;
  146. struct rcar_sysc_ch ch;
  147. unsigned int flags;
  148. char name[];
  149. };
  150. static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
  151. {
  152. return container_of(d, struct rcar_sysc_pd, genpd);
  153. }
  154. static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
  155. {
  156. struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
  157. pr_debug("%s: %s\n", __func__, genpd->name);
  158. return rcar_sysc_power(&pd->ch, false);
  159. }
  160. static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
  161. {
  162. struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
  163. pr_debug("%s: %s\n", __func__, genpd->name);
  164. return rcar_sysc_power(&pd->ch, true);
  165. }
  166. static bool has_cpg_mstp;
  167. static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
  168. {
  169. struct generic_pm_domain *genpd = &pd->genpd;
  170. const char *name = pd->genpd.name;
  171. int error;
  172. if (pd->flags & PD_CPU) {
  173. /*
  174. * This domain contains a CPU core and therefore it should
  175. * only be turned off if the CPU is not in use.
  176. */
  177. pr_debug("PM domain %s contains %s\n", name, "CPU");
  178. genpd->flags |= GENPD_FLAG_ALWAYS_ON;
  179. } else if (pd->flags & PD_SCU) {
  180. /*
  181. * This domain contains an SCU and cache-controller, and
  182. * therefore it should only be turned off if the CPU cores are
  183. * not in use.
  184. */
  185. pr_debug("PM domain %s contains %s\n", name, "SCU");
  186. genpd->flags |= GENPD_FLAG_ALWAYS_ON;
  187. } else if (pd->flags & PD_NO_CR) {
  188. /*
  189. * This domain cannot be turned off.
  190. */
  191. genpd->flags |= GENPD_FLAG_ALWAYS_ON;
  192. }
  193. if (!(pd->flags & (PD_CPU | PD_SCU))) {
  194. /* Enable Clock Domain for I/O devices */
  195. genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
  196. if (has_cpg_mstp) {
  197. genpd->attach_dev = cpg_mstp_attach_dev;
  198. genpd->detach_dev = cpg_mstp_detach_dev;
  199. } else {
  200. genpd->attach_dev = cpg_mssr_attach_dev;
  201. genpd->detach_dev = cpg_mssr_detach_dev;
  202. }
  203. }
  204. genpd->power_off = rcar_sysc_pd_power_off;
  205. genpd->power_on = rcar_sysc_pd_power_on;
  206. if (pd->flags & (PD_CPU | PD_NO_CR)) {
  207. /* Skip CPUs (handled by SMP code) and areas without control */
  208. pr_debug("%s: Not touching %s\n", __func__, genpd->name);
  209. goto finalize;
  210. }
  211. if (!rcar_sysc_power_is_off(&pd->ch)) {
  212. pr_debug("%s: %s is already powered\n", __func__, genpd->name);
  213. goto finalize;
  214. }
  215. rcar_sysc_power(&pd->ch, true);
  216. finalize:
  217. error = pm_genpd_init(genpd, &simple_qos_governor, false);
  218. if (error)
  219. pr_err("Failed to init PM domain %s: %d\n", name, error);
  220. return error;
  221. }
  222. static const struct of_device_id rcar_sysc_matches[] __initconst = {
  223. #ifdef CONFIG_SYSC_R8A7742
  224. { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
  225. #endif
  226. #ifdef CONFIG_SYSC_R8A7743
  227. { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
  228. /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
  229. { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
  230. #endif
  231. #ifdef CONFIG_SYSC_R8A7745
  232. { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
  233. #endif
  234. #ifdef CONFIG_SYSC_R8A77470
  235. { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
  236. #endif
  237. #ifdef CONFIG_SYSC_R8A774A1
  238. { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
  239. #endif
  240. #ifdef CONFIG_SYSC_R8A774B1
  241. { .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
  242. #endif
  243. #ifdef CONFIG_SYSC_R8A774C0
  244. { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
  245. #endif
  246. #ifdef CONFIG_SYSC_R8A774E1
  247. { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
  248. #endif
  249. #ifdef CONFIG_SYSC_R8A7779
  250. { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
  251. #endif
  252. #ifdef CONFIG_SYSC_R8A7790
  253. { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
  254. #endif
  255. #ifdef CONFIG_SYSC_R8A7791
  256. { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
  257. /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
  258. { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
  259. #endif
  260. #ifdef CONFIG_SYSC_R8A7792
  261. { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
  262. #endif
  263. #ifdef CONFIG_SYSC_R8A7794
  264. { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
  265. #endif
  266. #ifdef CONFIG_SYSC_R8A7795
  267. { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
  268. #endif
  269. #ifdef CONFIG_SYSC_R8A77960
  270. { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
  271. #endif
  272. #ifdef CONFIG_SYSC_R8A77961
  273. { .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
  274. #endif
  275. #ifdef CONFIG_SYSC_R8A77965
  276. { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
  277. #endif
  278. #ifdef CONFIG_SYSC_R8A77970
  279. { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
  280. #endif
  281. #ifdef CONFIG_SYSC_R8A77980
  282. { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
  283. #endif
  284. #ifdef CONFIG_SYSC_R8A77990
  285. { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
  286. #endif
  287. #ifdef CONFIG_SYSC_R8A77995
  288. { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
  289. #endif
  290. { /* sentinel */ }
  291. };
  292. struct rcar_pm_domains {
  293. struct genpd_onecell_data onecell_data;
  294. struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
  295. };
  296. static struct genpd_onecell_data *rcar_sysc_onecell_data;
  297. static int __init rcar_sysc_pd_init(void)
  298. {
  299. const struct rcar_sysc_info *info;
  300. const struct of_device_id *match;
  301. struct rcar_pm_domains *domains;
  302. struct device_node *np;
  303. void __iomem *base;
  304. unsigned int i;
  305. int error;
  306. np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
  307. if (!np)
  308. return -ENODEV;
  309. info = match->data;
  310. if (info->init) {
  311. error = info->init();
  312. if (error)
  313. goto out_put;
  314. }
  315. has_cpg_mstp = of_find_compatible_node(NULL, NULL,
  316. "renesas,cpg-mstp-clocks");
  317. base = of_iomap(np, 0);
  318. if (!base) {
  319. pr_warn("%pOF: Cannot map regs\n", np);
  320. error = -ENOMEM;
  321. goto out_put;
  322. }
  323. rcar_sysc_base = base;
  324. /* Optional External Request Mask Register */
  325. rcar_sysc_extmask_offs = info->extmask_offs;
  326. rcar_sysc_extmask_val = info->extmask_val;
  327. domains = kzalloc(sizeof(*domains), GFP_KERNEL);
  328. if (!domains) {
  329. error = -ENOMEM;
  330. goto out_put;
  331. }
  332. domains->onecell_data.domains = domains->domains;
  333. domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
  334. rcar_sysc_onecell_data = &domains->onecell_data;
  335. for (i = 0; i < info->num_areas; i++) {
  336. const struct rcar_sysc_area *area = &info->areas[i];
  337. struct rcar_sysc_pd *pd;
  338. if (!area->name) {
  339. /* Skip NULLified area */
  340. continue;
  341. }
  342. pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
  343. if (!pd) {
  344. error = -ENOMEM;
  345. goto out_put;
  346. }
  347. strcpy(pd->name, area->name);
  348. pd->genpd.name = pd->name;
  349. pd->ch.chan_offs = area->chan_offs;
  350. pd->ch.chan_bit = area->chan_bit;
  351. pd->ch.isr_bit = area->isr_bit;
  352. pd->flags = area->flags;
  353. error = rcar_sysc_pd_setup(pd);
  354. if (error)
  355. goto out_put;
  356. domains->domains[area->isr_bit] = &pd->genpd;
  357. if (area->parent < 0)
  358. continue;
  359. error = pm_genpd_add_subdomain(domains->domains[area->parent],
  360. &pd->genpd);
  361. if (error) {
  362. pr_warn("Failed to add PM subdomain %s to parent %u\n",
  363. area->name, area->parent);
  364. goto out_put;
  365. }
  366. }
  367. error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
  368. out_put:
  369. of_node_put(np);
  370. return error;
  371. }
  372. early_initcall(rcar_sysc_pd_init);
  373. void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
  374. unsigned int num_areas, u8 id)
  375. {
  376. unsigned int i;
  377. for (i = 0; i < num_areas; i++)
  378. if (areas[i].isr_bit == id) {
  379. areas[i].name = NULL;
  380. return;
  381. }
  382. }
  383. #ifdef CONFIG_ARCH_R8A7779
  384. static int rcar_sysc_power_cpu(unsigned int idx, bool on)
  385. {
  386. struct generic_pm_domain *genpd;
  387. struct rcar_sysc_pd *pd;
  388. unsigned int i;
  389. if (!rcar_sysc_onecell_data)
  390. return -ENODEV;
  391. for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
  392. genpd = rcar_sysc_onecell_data->domains[i];
  393. if (!genpd)
  394. continue;
  395. pd = to_rcar_pd(genpd);
  396. if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
  397. continue;
  398. return rcar_sysc_power(&pd->ch, on);
  399. }
  400. return -ENOENT;
  401. }
  402. int rcar_sysc_power_down_cpu(unsigned int cpu)
  403. {
  404. return rcar_sysc_power_cpu(cpu, false);
  405. }
  406. int rcar_sysc_power_up_cpu(unsigned int cpu)
  407. {
  408. return rcar_sysc_power_cpu(cpu, true);
  409. }
  410. #endif /* CONFIG_ARCH_R8A7779 */