rcar-rst.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
  4. *
  5. * Copyright (C) 2016 Glider bvba
  6. */
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/of_address.h>
  10. #include <linux/soc/renesas/rcar-rst.h>
  11. #define WDTRSTCR_RESET 0xA55A0002
  12. #define WDTRSTCR 0x0054
  13. static int rcar_rst_enable_wdt_reset(void __iomem *base)
  14. {
  15. iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
  16. return 0;
  17. }
  18. struct rst_config {
  19. unsigned int modemr; /* Mode Monitoring Register Offset */
  20. int (*configure)(void __iomem *base); /* Platform specific config */
  21. };
  22. static const struct rst_config rcar_rst_gen1 __initconst = {
  23. .modemr = 0x20,
  24. };
  25. static const struct rst_config rcar_rst_gen2 __initconst = {
  26. .modemr = 0x60,
  27. .configure = rcar_rst_enable_wdt_reset,
  28. };
  29. static const struct rst_config rcar_rst_gen3 __initconst = {
  30. .modemr = 0x60,
  31. };
  32. static const struct rst_config rcar_rst_r8a779a0 __initconst = {
  33. .modemr = 0x00, /* MODEMR0 and it has CPG related bits */
  34. };
  35. static const struct of_device_id rcar_rst_matches[] __initconst = {
  36. /* RZ/G1 is handled like R-Car Gen2 */
  37. { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
  38. { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
  39. { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
  40. { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
  41. { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
  42. /* RZ/G2 is handled like R-Car Gen3 */
  43. { .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
  44. { .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
  45. { .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
  46. { .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
  47. /* R-Car Gen1 */
  48. { .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
  49. { .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
  50. /* R-Car Gen2 */
  51. { .compatible = "renesas,r8a7790-rst", .data = &rcar_rst_gen2 },
  52. { .compatible = "renesas,r8a7791-rst", .data = &rcar_rst_gen2 },
  53. { .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
  54. { .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
  55. { .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
  56. /* R-Car Gen3 */
  57. { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
  58. { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
  59. { .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
  60. { .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
  61. { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
  62. { .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
  63. { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
  64. { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
  65. /* R-Car V3U */
  66. { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_r8a779a0 },
  67. { /* sentinel */ }
  68. };
  69. static void __iomem *rcar_rst_base __initdata;
  70. static u32 saved_mode __initdata;
  71. static int __init rcar_rst_init(void)
  72. {
  73. const struct of_device_id *match;
  74. const struct rst_config *cfg;
  75. struct device_node *np;
  76. void __iomem *base;
  77. int error = 0;
  78. np = of_find_matching_node_and_match(NULL, rcar_rst_matches, &match);
  79. if (!np)
  80. return -ENODEV;
  81. base = of_iomap(np, 0);
  82. if (!base) {
  83. pr_warn("%pOF: Cannot map regs\n", np);
  84. error = -ENOMEM;
  85. goto out_put;
  86. }
  87. rcar_rst_base = base;
  88. cfg = match->data;
  89. saved_mode = ioread32(base + cfg->modemr);
  90. if (cfg->configure) {
  91. error = cfg->configure(base);
  92. if (error) {
  93. pr_warn("%pOF: Cannot run SoC specific configuration\n",
  94. np);
  95. goto out_put;
  96. }
  97. }
  98. pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
  99. out_put:
  100. of_node_put(np);
  101. return error;
  102. }
  103. int __init rcar_rst_read_mode_pins(u32 *mode)
  104. {
  105. int error;
  106. if (!rcar_rst_base) {
  107. error = rcar_rst_init();
  108. if (error)
  109. return error;
  110. }
  111. *mode = saved_mode;
  112. return 0;
  113. }