r8a779a0-sysc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas R-Car V3U System Controller
  4. *
  5. * Copyright (C) 2020 Renesas Electronics Corp.
  6. */
  7. #include <linux/bits.h>
  8. #include <linux/clk/renesas.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mm.h>
  15. #include <linux/of_address.h>
  16. #include <linux/pm_domain.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/types.h>
  20. #include <dt-bindings/power/r8a779a0-sysc.h>
  21. /*
  22. * Power Domain flags
  23. */
  24. #define PD_CPU BIT(0) /* Area contains main CPU core */
  25. #define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
  26. #define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
  27. #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR */
  28. #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
  29. /*
  30. * Description of a Power Area
  31. */
  32. struct r8a779a0_sysc_area {
  33. const char *name;
  34. u8 pdr; /* PDRn */
  35. int parent; /* -1 if none */
  36. unsigned int flags; /* See PD_* */
  37. };
  38. /*
  39. * SoC-specific Power Area Description
  40. */
  41. struct r8a779a0_sysc_info {
  42. const struct r8a779a0_sysc_area *areas;
  43. unsigned int num_areas;
  44. };
  45. static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = {
  46. { "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
  47. { "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
  48. { "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
  49. { "a2e0d0", R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
  50. { "a2e0d1", R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
  51. { "a2e1d0", R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
  52. { "a2e1d1", R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
  53. { "a1e0d0c0", R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
  54. { "a1e0d0c1", R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
  55. { "a1e0d1c0", R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
  56. { "a1e0d1c1", R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
  57. { "a1e1d0c0", R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
  58. { "a1e1d0c1", R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
  59. { "a1e1d1c0", R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
  60. { "a1e1d1c1", R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
  61. { "3dg-a", R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
  62. { "3dg-b", R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
  63. { "a3vip0", R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
  64. { "a3vip1", R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
  65. { "a3vip3", R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
  66. { "a3vip2", R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
  67. { "a3isp01", R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
  68. { "a3isp23", R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
  69. { "a3ir", R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
  70. { "a2cn0", R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
  71. { "a2imp01", R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
  72. { "a2dp0", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
  73. { "a2cv0", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
  74. { "a2cv1", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
  75. { "a2cv4", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
  76. { "a2cv6", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
  77. { "a2cn2", R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
  78. { "a2imp23", R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
  79. { "a2dp1", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
  80. { "a2cv2", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
  81. { "a2cv3", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
  82. { "a2cv5", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
  83. { "a2cv7", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
  84. { "a2cn1", R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
  85. { "a1cnn0", R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
  86. { "a1cnn2", R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
  87. { "a1dsp0", R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
  88. { "a1cnn1", R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
  89. { "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
  90. };
  91. static const struct r8a779a0_sysc_info r8a779a0_sysc_info __initconst = {
  92. .areas = r8a779a0_areas,
  93. .num_areas = ARRAY_SIZE(r8a779a0_areas),
  94. };
  95. /* SYSC Common */
  96. #define SYSCSR 0x000 /* SYSC Status Register */
  97. #define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
  98. #define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
  99. #define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
  100. #define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
  101. #define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
  102. /* Power Domain Registers */
  103. #define PDRSR(n) (0x1000 + ((n) * 0x40))
  104. #define PDRONCR(n) (0x1004 + ((n) * 0x40))
  105. #define PDROFFCR(n) (0x1008 + ((n) * 0x40))
  106. #define PDRESR(n) (0x100C + ((n) * 0x40))
  107. /* PWRON/PWROFF */
  108. #define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */
  109. /* PDRESR */
  110. #define PDRESR_ERR BIT(0)
  111. /* PDRSR */
  112. #define PDRSR_OFF BIT(0) /* Power-OFF state */
  113. #define PDRSR_ON BIT(4) /* Power-ON state */
  114. #define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */
  115. #define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */
  116. #define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */
  117. #define SYSCSR_TIMEOUT 10000
  118. #define SYSCSR_DELAY_US 10
  119. #define PDRESR_RETRIES 1000
  120. #define PDRESR_DELAY_US 10
  121. #define SYSCISR_TIMEOUT 10000
  122. #define SYSCISR_DELAY_US 10
  123. #define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32)
  124. static void __iomem *r8a779a0_sysc_base;
  125. static DEFINE_SPINLOCK(r8a779a0_sysc_lock); /* SMP CPUs + I/O devices */
  126. static int r8a779a0_sysc_pwr_on_off(u8 pdr, bool on)
  127. {
  128. unsigned int reg_offs;
  129. u32 val;
  130. int ret;
  131. if (on)
  132. reg_offs = PDRONCR(pdr);
  133. else
  134. reg_offs = PDROFFCR(pdr);
  135. /* Wait until SYSC is ready to accept a power request */
  136. ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCSR, val,
  137. (val & SYSCSR_BUSY) == SYSCSR_BUSY,
  138. SYSCSR_DELAY_US, SYSCSR_TIMEOUT);
  139. if (ret < 0)
  140. return -EAGAIN;
  141. /* Submit power shutoff or power resume request */
  142. iowrite32(PWRON_PWROFF, r8a779a0_sysc_base + reg_offs);
  143. return 0;
  144. }
  145. static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
  146. {
  147. u32 val;
  148. int ret;
  149. iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx));
  150. ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx),
  151. val, !(val & isr_mask),
  152. SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
  153. if (ret < 0) {
  154. pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
  155. return -EIO;
  156. }
  157. return 0;
  158. }
  159. static int r8a779a0_sysc_power(u8 pdr, bool on)
  160. {
  161. unsigned int isr_mask;
  162. unsigned int reg_idx, bit_idx;
  163. unsigned int status;
  164. unsigned long flags;
  165. int ret = 0;
  166. u32 val;
  167. int k;
  168. spin_lock_irqsave(&r8a779a0_sysc_lock, flags);
  169. reg_idx = pdr / NUM_DOMAINS_EACH_REG;
  170. bit_idx = pdr % NUM_DOMAINS_EACH_REG;
  171. isr_mask = BIT(bit_idx);
  172. /*
  173. * The interrupt source needs to be enabled, but masked, to prevent the
  174. * CPU from receiving it.
  175. */
  176. iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask,
  177. r8a779a0_sysc_base + SYSCIER(reg_idx));
  178. iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask,
  179. r8a779a0_sysc_base + SYSCIMR(reg_idx));
  180. ret = clear_irq_flags(reg_idx, isr_mask);
  181. if (ret)
  182. goto out;
  183. /* Submit power shutoff or resume request until it was accepted */
  184. for (k = 0; k < PDRESR_RETRIES; k++) {
  185. ret = r8a779a0_sysc_pwr_on_off(pdr, on);
  186. if (ret)
  187. goto out;
  188. status = ioread32(r8a779a0_sysc_base + PDRESR(pdr));
  189. if (!(status & PDRESR_ERR))
  190. break;
  191. udelay(PDRESR_DELAY_US);
  192. }
  193. if (k == PDRESR_RETRIES) {
  194. ret = -EIO;
  195. goto out;
  196. }
  197. /* Wait until the power shutoff or resume request has completed * */
  198. ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx),
  199. val, (val & isr_mask),
  200. SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
  201. if (ret < 0) {
  202. ret = -EIO;
  203. goto out;
  204. }
  205. /* Clear interrupt flags */
  206. ret = clear_irq_flags(reg_idx, isr_mask);
  207. if (ret)
  208. goto out;
  209. out:
  210. spin_unlock_irqrestore(&r8a779a0_sysc_lock, flags);
  211. pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
  212. pdr, ioread32(r8a779a0_sysc_base + SYSCISCR(reg_idx)), ret);
  213. return ret;
  214. }
  215. static bool r8a779a0_sysc_power_is_off(u8 pdr)
  216. {
  217. unsigned int st;
  218. st = ioread32(r8a779a0_sysc_base + PDRSR(pdr));
  219. if (st & PDRSR_OFF)
  220. return true;
  221. return false;
  222. }
  223. struct r8a779a0_sysc_pd {
  224. struct generic_pm_domain genpd;
  225. u8 pdr;
  226. unsigned int flags;
  227. char name[];
  228. };
  229. static inline struct r8a779a0_sysc_pd *to_r8a779a0_pd(struct generic_pm_domain *d)
  230. {
  231. return container_of(d, struct r8a779a0_sysc_pd, genpd);
  232. }
  233. static int r8a779a0_sysc_pd_power_off(struct generic_pm_domain *genpd)
  234. {
  235. struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd);
  236. pr_debug("%s: %s\n", __func__, genpd->name);
  237. return r8a779a0_sysc_power(pd->pdr, false);
  238. }
  239. static int r8a779a0_sysc_pd_power_on(struct generic_pm_domain *genpd)
  240. {
  241. struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd);
  242. pr_debug("%s: %s\n", __func__, genpd->name);
  243. return r8a779a0_sysc_power(pd->pdr, true);
  244. }
  245. static int __init r8a779a0_sysc_pd_setup(struct r8a779a0_sysc_pd *pd)
  246. {
  247. struct generic_pm_domain *genpd = &pd->genpd;
  248. const char *name = pd->genpd.name;
  249. int error;
  250. if (pd->flags & PD_CPU) {
  251. /*
  252. * This domain contains a CPU core and therefore it should
  253. * only be turned off if the CPU is not in use.
  254. */
  255. pr_debug("PM domain %s contains %s\n", name, "CPU");
  256. genpd->flags |= GENPD_FLAG_ALWAYS_ON;
  257. } else if (pd->flags & PD_SCU) {
  258. /*
  259. * This domain contains an SCU and cache-controller, and
  260. * therefore it should only be turned off if the CPU cores are
  261. * not in use.
  262. */
  263. pr_debug("PM domain %s contains %s\n", name, "SCU");
  264. genpd->flags |= GENPD_FLAG_ALWAYS_ON;
  265. } else if (pd->flags & PD_NO_CR) {
  266. /*
  267. * This domain cannot be turned off.
  268. */
  269. genpd->flags |= GENPD_FLAG_ALWAYS_ON;
  270. }
  271. if (!(pd->flags & (PD_CPU | PD_SCU))) {
  272. /* Enable Clock Domain for I/O devices */
  273. genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
  274. genpd->attach_dev = cpg_mssr_attach_dev;
  275. genpd->detach_dev = cpg_mssr_detach_dev;
  276. }
  277. genpd->power_off = r8a779a0_sysc_pd_power_off;
  278. genpd->power_on = r8a779a0_sysc_pd_power_on;
  279. if (pd->flags & (PD_CPU | PD_NO_CR)) {
  280. /* Skip CPUs (handled by SMP code) and areas without control */
  281. pr_debug("%s: Not touching %s\n", __func__, genpd->name);
  282. goto finalize;
  283. }
  284. if (!r8a779a0_sysc_power_is_off(pd->pdr)) {
  285. pr_debug("%s: %s is already powered\n", __func__, genpd->name);
  286. goto finalize;
  287. }
  288. r8a779a0_sysc_power(pd->pdr, true);
  289. finalize:
  290. error = pm_genpd_init(genpd, &simple_qos_governor, false);
  291. if (error)
  292. pr_err("Failed to init PM domain %s: %d\n", name, error);
  293. return error;
  294. }
  295. static const struct of_device_id r8a779a0_sysc_matches[] __initconst = {
  296. { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info },
  297. { /* sentinel */ }
  298. };
  299. struct r8a779a0_pm_domains {
  300. struct genpd_onecell_data onecell_data;
  301. struct generic_pm_domain *domains[R8A779A0_PD_ALWAYS_ON + 1];
  302. };
  303. static struct genpd_onecell_data *r8a779a0_sysc_onecell_data;
  304. static int __init r8a779a0_sysc_pd_init(void)
  305. {
  306. const struct r8a779a0_sysc_info *info;
  307. const struct of_device_id *match;
  308. struct r8a779a0_pm_domains *domains;
  309. struct device_node *np;
  310. void __iomem *base;
  311. unsigned int i;
  312. int error;
  313. np = of_find_matching_node_and_match(NULL, r8a779a0_sysc_matches, &match);
  314. if (!np)
  315. return -ENODEV;
  316. info = match->data;
  317. base = of_iomap(np, 0);
  318. if (!base) {
  319. pr_warn("%pOF: Cannot map regs\n", np);
  320. error = -ENOMEM;
  321. goto out_put;
  322. }
  323. r8a779a0_sysc_base = base;
  324. domains = kzalloc(sizeof(*domains), GFP_KERNEL);
  325. if (!domains) {
  326. error = -ENOMEM;
  327. goto out_put;
  328. }
  329. domains->onecell_data.domains = domains->domains;
  330. domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
  331. r8a779a0_sysc_onecell_data = &domains->onecell_data;
  332. for (i = 0; i < info->num_areas; i++) {
  333. const struct r8a779a0_sysc_area *area = &info->areas[i];
  334. struct r8a779a0_sysc_pd *pd;
  335. if (!area->name) {
  336. /* Skip NULLified area */
  337. continue;
  338. }
  339. pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
  340. if (!pd) {
  341. error = -ENOMEM;
  342. goto out_put;
  343. }
  344. strcpy(pd->name, area->name);
  345. pd->genpd.name = pd->name;
  346. pd->pdr = area->pdr;
  347. pd->flags = area->flags;
  348. error = r8a779a0_sysc_pd_setup(pd);
  349. if (error)
  350. goto out_put;
  351. domains->domains[area->pdr] = &pd->genpd;
  352. if (area->parent < 0)
  353. continue;
  354. error = pm_genpd_add_subdomain(domains->domains[area->parent],
  355. &pd->genpd);
  356. if (error) {
  357. pr_warn("Failed to add PM subdomain %s to parent %u\n",
  358. area->name, area->parent);
  359. goto out_put;
  360. }
  361. }
  362. error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
  363. out_put:
  364. of_node_put(np);
  365. return error;
  366. }
  367. early_initcall(r8a779a0_sysc_pd_init);