r8a7795-sysc.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas R-Car H3 System Controller
  4. *
  5. * Copyright (C) 2016-2017 Glider bvba
  6. */
  7. #include <linux/bits.h>
  8. #include <linux/kernel.h>
  9. #include <linux/sys_soc.h>
  10. #include <dt-bindings/power/r8a7795-sysc.h>
  11. #include "rcar-sysc.h"
  12. static struct rcar_sysc_area r8a7795_areas[] __initdata = {
  13. { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
  14. { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
  15. PD_SCU },
  16. { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
  17. PD_CPU_NOCR },
  18. { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
  19. PD_CPU_NOCR },
  20. { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
  21. PD_CPU_NOCR },
  22. { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
  23. PD_CPU_NOCR },
  24. { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
  25. PD_SCU },
  26. { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
  27. PD_CPU_NOCR },
  28. { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
  29. PD_CPU_NOCR },
  30. { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
  31. PD_CPU_NOCR },
  32. { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
  33. PD_CPU_NOCR },
  34. { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
  35. { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
  36. { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
  37. /* A2VC0 exists on ES1.x only */
  38. { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
  39. { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
  40. { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
  41. { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
  42. { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
  43. { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
  44. { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
  45. { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
  46. };
  47. /*
  48. * Fixups for R-Car H3 revisions
  49. */
  50. #define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
  51. #define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
  52. static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
  53. {
  54. .soc_id = "r8a7795", .revision = "ES1.*",
  55. .data = (void *)(HAS_A2VC0 | NO_EXTMASK),
  56. }, {
  57. .soc_id = "r8a7795", .revision = "ES2.*",
  58. .data = (void *)(NO_EXTMASK),
  59. },
  60. { /* sentinel */ }
  61. };
  62. static int __init r8a7795_sysc_init(void)
  63. {
  64. const struct soc_device_attribute *attr;
  65. u32 quirks = 0;
  66. attr = soc_device_match(r8a7795_quirks_match);
  67. if (attr)
  68. quirks = (uintptr_t)attr->data;
  69. if (!(quirks & HAS_A2VC0))
  70. rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
  71. R8A7795_PD_A2VC0);
  72. if (quirks & NO_EXTMASK)
  73. r8a7795_sysc_info.extmask_val = 0;
  74. return 0;
  75. }
  76. struct rcar_sysc_info r8a7795_sysc_info __initdata = {
  77. .init = r8a7795_sysc_init,
  78. .areas = r8a7795_areas,
  79. .num_areas = ARRAY_SIZE(r8a7795_areas),
  80. .extmask_offs = 0x2f8,
  81. .extmask_val = BIT(0),
  82. };