smsm.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015, Sony Mobile Communications Inc.
  4. * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  5. */
  6. #include <linux/interrupt.h>
  7. #include <linux/mfd/syscon.h>
  8. #include <linux/module.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/regmap.h>
  13. #include <linux/soc/qcom/smem.h>
  14. #include <linux/soc/qcom/smem_state.h>
  15. /*
  16. * This driver implements the Qualcomm Shared Memory State Machine, a mechanism
  17. * for communicating single bit state information to remote processors.
  18. *
  19. * The implementation is based on two sections of shared memory; the first
  20. * holding the state bits and the second holding a matrix of subscription bits.
  21. *
  22. * The state bits are structured in entries of 32 bits, each belonging to one
  23. * system in the SoC. The entry belonging to the local system is considered
  24. * read-write, while the rest should be considered read-only.
  25. *
  26. * The subscription matrix consists of N bitmaps per entry, denoting interest
  27. * in updates of the entry for each of the N hosts. Upon updating a state bit
  28. * each host's subscription bitmap should be queried and the remote system
  29. * should be interrupted if they request so.
  30. *
  31. * The subscription matrix is laid out in entry-major order:
  32. * entry0: [host0 ... hostN]
  33. * .
  34. * .
  35. * entryM: [host0 ... hostN]
  36. *
  37. * A third, optional, shared memory region might contain information regarding
  38. * the number of entries in the state bitmap as well as number of columns in
  39. * the subscription matrix.
  40. */
  41. /*
  42. * Shared memory identifiers, used to acquire handles to respective memory
  43. * region.
  44. */
  45. #define SMEM_SMSM_SHARED_STATE 85
  46. #define SMEM_SMSM_CPU_INTR_MASK 333
  47. #define SMEM_SMSM_SIZE_INFO 419
  48. /*
  49. * Default sizes, in case SMEM_SMSM_SIZE_INFO is not found.
  50. */
  51. #define SMSM_DEFAULT_NUM_ENTRIES 8
  52. #define SMSM_DEFAULT_NUM_HOSTS 3
  53. struct smsm_entry;
  54. struct smsm_host;
  55. /**
  56. * struct qcom_smsm - smsm driver context
  57. * @dev: smsm device pointer
  58. * @local_host: column in the subscription matrix representing this system
  59. * @num_hosts: number of columns in the subscription matrix
  60. * @num_entries: number of entries in the state map and rows in the subscription
  61. * matrix
  62. * @local_state: pointer to the local processor's state bits
  63. * @subscription: pointer to local processor's row in subscription matrix
  64. * @state: smem state handle
  65. * @lock: spinlock for read-modify-write of the outgoing state
  66. * @entries: context for each of the entries
  67. * @hosts: context for each of the hosts
  68. */
  69. struct qcom_smsm {
  70. struct device *dev;
  71. u32 local_host;
  72. u32 num_hosts;
  73. u32 num_entries;
  74. u32 *local_state;
  75. u32 *subscription;
  76. struct qcom_smem_state *state;
  77. spinlock_t lock;
  78. struct smsm_entry *entries;
  79. struct smsm_host *hosts;
  80. };
  81. /**
  82. * struct smsm_entry - per remote processor entry context
  83. * @smsm: back-reference to driver context
  84. * @domain: IRQ domain for this entry, if representing a remote system
  85. * @irq_enabled: bitmap of which state bits IRQs are enabled
  86. * @irq_rising: bitmap tracking if rising bits should be propagated
  87. * @irq_falling: bitmap tracking if falling bits should be propagated
  88. * @last_value: snapshot of state bits last time the interrupts where propagated
  89. * @remote_state: pointer to this entry's state bits
  90. * @subscription: pointer to a row in the subscription matrix representing this
  91. * entry
  92. */
  93. struct smsm_entry {
  94. struct qcom_smsm *smsm;
  95. struct irq_domain *domain;
  96. DECLARE_BITMAP(irq_enabled, 32);
  97. DECLARE_BITMAP(irq_rising, 32);
  98. DECLARE_BITMAP(irq_falling, 32);
  99. unsigned long last_value;
  100. u32 *remote_state;
  101. u32 *subscription;
  102. };
  103. /**
  104. * struct smsm_host - representation of a remote host
  105. * @ipc_regmap: regmap for outgoing interrupt
  106. * @ipc_offset: offset in @ipc_regmap for outgoing interrupt
  107. * @ipc_bit: bit in @ipc_regmap + @ipc_offset for outgoing interrupt
  108. */
  109. struct smsm_host {
  110. struct regmap *ipc_regmap;
  111. int ipc_offset;
  112. int ipc_bit;
  113. };
  114. /**
  115. * smsm_update_bits() - change bit in outgoing entry and inform subscribers
  116. * @data: smsm context pointer
  117. * @offset: bit in the entry
  118. * @value: new value
  119. *
  120. * Used to set and clear the bits in the outgoing/local entry and inform
  121. * subscribers about the change.
  122. */
  123. static int smsm_update_bits(void *data, u32 mask, u32 value)
  124. {
  125. struct qcom_smsm *smsm = data;
  126. struct smsm_host *hostp;
  127. unsigned long flags;
  128. u32 changes;
  129. u32 host;
  130. u32 orig;
  131. u32 val;
  132. spin_lock_irqsave(&smsm->lock, flags);
  133. /* Update the entry */
  134. val = orig = readl(smsm->local_state);
  135. val &= ~mask;
  136. val |= value;
  137. /* Don't signal if we didn't change the value */
  138. changes = val ^ orig;
  139. if (!changes) {
  140. spin_unlock_irqrestore(&smsm->lock, flags);
  141. goto done;
  142. }
  143. /* Write out the new value */
  144. writel(val, smsm->local_state);
  145. spin_unlock_irqrestore(&smsm->lock, flags);
  146. /* Make sure the value update is ordered before any kicks */
  147. wmb();
  148. /* Iterate over all hosts to check whom wants a kick */
  149. for (host = 0; host < smsm->num_hosts; host++) {
  150. hostp = &smsm->hosts[host];
  151. val = readl(smsm->subscription + host);
  152. if (val & changes && hostp->ipc_regmap) {
  153. regmap_write(hostp->ipc_regmap,
  154. hostp->ipc_offset,
  155. BIT(hostp->ipc_bit));
  156. }
  157. }
  158. done:
  159. return 0;
  160. }
  161. static const struct qcom_smem_state_ops smsm_state_ops = {
  162. .update_bits = smsm_update_bits,
  163. };
  164. /**
  165. * smsm_intr() - cascading IRQ handler for SMSM
  166. * @irq: unused
  167. * @data: entry related to this IRQ
  168. *
  169. * This function cascades an incoming interrupt from a remote system, based on
  170. * the state bits and configuration.
  171. */
  172. static irqreturn_t smsm_intr(int irq, void *data)
  173. {
  174. struct smsm_entry *entry = data;
  175. unsigned i;
  176. int irq_pin;
  177. u32 changed;
  178. u32 val;
  179. val = readl(entry->remote_state);
  180. changed = val ^ xchg(&entry->last_value, val);
  181. for_each_set_bit(i, entry->irq_enabled, 32) {
  182. if (!(changed & BIT(i)))
  183. continue;
  184. if (val & BIT(i)) {
  185. if (test_bit(i, entry->irq_rising)) {
  186. irq_pin = irq_find_mapping(entry->domain, i);
  187. handle_nested_irq(irq_pin);
  188. }
  189. } else {
  190. if (test_bit(i, entry->irq_falling)) {
  191. irq_pin = irq_find_mapping(entry->domain, i);
  192. handle_nested_irq(irq_pin);
  193. }
  194. }
  195. }
  196. return IRQ_HANDLED;
  197. }
  198. /**
  199. * smsm_mask_irq() - un-subscribe from cascades of IRQs of a certain staus bit
  200. * @irqd: IRQ handle to be masked
  201. *
  202. * This un-subscribes the local CPU from interrupts upon changes to the defines
  203. * status bit. The bit is also cleared from cascading.
  204. */
  205. static void smsm_mask_irq(struct irq_data *irqd)
  206. {
  207. struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd);
  208. irq_hw_number_t irq = irqd_to_hwirq(irqd);
  209. struct qcom_smsm *smsm = entry->smsm;
  210. u32 val;
  211. if (entry->subscription) {
  212. val = readl(entry->subscription + smsm->local_host);
  213. val &= ~BIT(irq);
  214. writel(val, entry->subscription + smsm->local_host);
  215. }
  216. clear_bit(irq, entry->irq_enabled);
  217. }
  218. /**
  219. * smsm_unmask_irq() - subscribe to cascades of IRQs of a certain status bit
  220. * @irqd: IRQ handle to be unmasked
  221. *
  222. * This subscribes the local CPU to interrupts upon changes to the defined
  223. * status bit. The bit is also marked for cascading.
  224. */
  225. static void smsm_unmask_irq(struct irq_data *irqd)
  226. {
  227. struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd);
  228. irq_hw_number_t irq = irqd_to_hwirq(irqd);
  229. struct qcom_smsm *smsm = entry->smsm;
  230. u32 val;
  231. /* Make sure our last cached state is up-to-date */
  232. if (readl(entry->remote_state) & BIT(irq))
  233. set_bit(irq, &entry->last_value);
  234. else
  235. clear_bit(irq, &entry->last_value);
  236. set_bit(irq, entry->irq_enabled);
  237. if (entry->subscription) {
  238. val = readl(entry->subscription + smsm->local_host);
  239. val |= BIT(irq);
  240. writel(val, entry->subscription + smsm->local_host);
  241. }
  242. }
  243. /**
  244. * smsm_set_irq_type() - updates the requested IRQ type for the cascading
  245. * @irqd: consumer interrupt handle
  246. * @type: requested flags
  247. */
  248. static int smsm_set_irq_type(struct irq_data *irqd, unsigned int type)
  249. {
  250. struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd);
  251. irq_hw_number_t irq = irqd_to_hwirq(irqd);
  252. if (!(type & IRQ_TYPE_EDGE_BOTH))
  253. return -EINVAL;
  254. if (type & IRQ_TYPE_EDGE_RISING)
  255. set_bit(irq, entry->irq_rising);
  256. else
  257. clear_bit(irq, entry->irq_rising);
  258. if (type & IRQ_TYPE_EDGE_FALLING)
  259. set_bit(irq, entry->irq_falling);
  260. else
  261. clear_bit(irq, entry->irq_falling);
  262. return 0;
  263. }
  264. static struct irq_chip smsm_irq_chip = {
  265. .name = "smsm",
  266. .irq_mask = smsm_mask_irq,
  267. .irq_unmask = smsm_unmask_irq,
  268. .irq_set_type = smsm_set_irq_type,
  269. };
  270. /**
  271. * smsm_irq_map() - sets up a mapping for a cascaded IRQ
  272. * @d: IRQ domain representing an entry
  273. * @irq: IRQ to set up
  274. * @hw: unused
  275. */
  276. static int smsm_irq_map(struct irq_domain *d,
  277. unsigned int irq,
  278. irq_hw_number_t hw)
  279. {
  280. struct smsm_entry *entry = d->host_data;
  281. irq_set_chip_and_handler(irq, &smsm_irq_chip, handle_level_irq);
  282. irq_set_chip_data(irq, entry);
  283. irq_set_nested_thread(irq, 1);
  284. return 0;
  285. }
  286. static const struct irq_domain_ops smsm_irq_ops = {
  287. .map = smsm_irq_map,
  288. .xlate = irq_domain_xlate_twocell,
  289. };
  290. /**
  291. * smsm_parse_ipc() - parses a qcom,ipc-%d device tree property
  292. * @smsm: smsm driver context
  293. * @host_id: index of the remote host to be resolved
  294. *
  295. * Parses device tree to acquire the information needed for sending the
  296. * outgoing interrupts to a remote host - identified by @host_id.
  297. */
  298. static int smsm_parse_ipc(struct qcom_smsm *smsm, unsigned host_id)
  299. {
  300. struct device_node *syscon;
  301. struct device_node *node = smsm->dev->of_node;
  302. struct smsm_host *host = &smsm->hosts[host_id];
  303. char key[16];
  304. int ret;
  305. snprintf(key, sizeof(key), "qcom,ipc-%d", host_id);
  306. syscon = of_parse_phandle(node, key, 0);
  307. if (!syscon)
  308. return 0;
  309. host->ipc_regmap = syscon_node_to_regmap(syscon);
  310. if (IS_ERR(host->ipc_regmap))
  311. return PTR_ERR(host->ipc_regmap);
  312. ret = of_property_read_u32_index(node, key, 1, &host->ipc_offset);
  313. if (ret < 0) {
  314. dev_err(smsm->dev, "no offset in %s\n", key);
  315. return -EINVAL;
  316. }
  317. ret = of_property_read_u32_index(node, key, 2, &host->ipc_bit);
  318. if (ret < 0) {
  319. dev_err(smsm->dev, "no bit in %s\n", key);
  320. return -EINVAL;
  321. }
  322. return 0;
  323. }
  324. /**
  325. * smsm_inbound_entry() - parse DT and set up an entry representing a remote system
  326. * @smsm: smsm driver context
  327. * @entry: entry context to be set up
  328. * @node: dt node containing the entry's properties
  329. */
  330. static int smsm_inbound_entry(struct qcom_smsm *smsm,
  331. struct smsm_entry *entry,
  332. struct device_node *node)
  333. {
  334. int ret;
  335. int irq;
  336. irq = irq_of_parse_and_map(node, 0);
  337. if (!irq) {
  338. dev_err(smsm->dev, "failed to parse smsm interrupt\n");
  339. return -EINVAL;
  340. }
  341. ret = devm_request_threaded_irq(smsm->dev, irq,
  342. NULL, smsm_intr,
  343. IRQF_ONESHOT,
  344. "smsm", (void *)entry);
  345. if (ret) {
  346. dev_err(smsm->dev, "failed to request interrupt\n");
  347. return ret;
  348. }
  349. entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry);
  350. if (!entry->domain) {
  351. dev_err(smsm->dev, "failed to add irq_domain\n");
  352. return -ENOMEM;
  353. }
  354. return 0;
  355. }
  356. /**
  357. * smsm_get_size_info() - parse the optional memory segment for sizes
  358. * @smsm: smsm driver context
  359. *
  360. * Attempt to acquire the number of hosts and entries from the optional shared
  361. * memory location. Not being able to find this segment should indicate that
  362. * we're on a older system where these values was hard coded to
  363. * SMSM_DEFAULT_NUM_ENTRIES and SMSM_DEFAULT_NUM_HOSTS.
  364. *
  365. * Returns 0 on success, negative errno on failure.
  366. */
  367. static int smsm_get_size_info(struct qcom_smsm *smsm)
  368. {
  369. size_t size;
  370. struct {
  371. u32 num_hosts;
  372. u32 num_entries;
  373. u32 reserved0;
  374. u32 reserved1;
  375. } *info;
  376. info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SIZE_INFO, &size);
  377. if (IS_ERR(info) && PTR_ERR(info) != -ENOENT) {
  378. if (PTR_ERR(info) != -EPROBE_DEFER)
  379. dev_err(smsm->dev, "unable to retrieve smsm size info\n");
  380. return PTR_ERR(info);
  381. } else if (IS_ERR(info) || size != sizeof(*info)) {
  382. dev_warn(smsm->dev, "no smsm size info, using defaults\n");
  383. smsm->num_entries = SMSM_DEFAULT_NUM_ENTRIES;
  384. smsm->num_hosts = SMSM_DEFAULT_NUM_HOSTS;
  385. return 0;
  386. }
  387. smsm->num_entries = info->num_entries;
  388. smsm->num_hosts = info->num_hosts;
  389. dev_dbg(smsm->dev,
  390. "found custom size of smsm: %d entries %d hosts\n",
  391. smsm->num_entries, smsm->num_hosts);
  392. return 0;
  393. }
  394. static int qcom_smsm_probe(struct platform_device *pdev)
  395. {
  396. struct device_node *local_node;
  397. struct device_node *node;
  398. struct smsm_entry *entry;
  399. struct qcom_smsm *smsm;
  400. u32 *intr_mask;
  401. size_t size;
  402. u32 *states;
  403. u32 id;
  404. int ret;
  405. smsm = devm_kzalloc(&pdev->dev, sizeof(*smsm), GFP_KERNEL);
  406. if (!smsm)
  407. return -ENOMEM;
  408. smsm->dev = &pdev->dev;
  409. spin_lock_init(&smsm->lock);
  410. ret = smsm_get_size_info(smsm);
  411. if (ret)
  412. return ret;
  413. smsm->entries = devm_kcalloc(&pdev->dev,
  414. smsm->num_entries,
  415. sizeof(struct smsm_entry),
  416. GFP_KERNEL);
  417. if (!smsm->entries)
  418. return -ENOMEM;
  419. smsm->hosts = devm_kcalloc(&pdev->dev,
  420. smsm->num_hosts,
  421. sizeof(struct smsm_host),
  422. GFP_KERNEL);
  423. if (!smsm->hosts)
  424. return -ENOMEM;
  425. for_each_child_of_node(pdev->dev.of_node, local_node) {
  426. if (of_find_property(local_node, "#qcom,smem-state-cells", NULL))
  427. break;
  428. }
  429. if (!local_node) {
  430. dev_err(&pdev->dev, "no state entry\n");
  431. return -EINVAL;
  432. }
  433. of_property_read_u32(pdev->dev.of_node,
  434. "qcom,local-host",
  435. &smsm->local_host);
  436. /* Parse the host properties */
  437. for (id = 0; id < smsm->num_hosts; id++) {
  438. ret = smsm_parse_ipc(smsm, id);
  439. if (ret < 0)
  440. return ret;
  441. }
  442. /* Acquire the main SMSM state vector */
  443. ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE,
  444. smsm->num_entries * sizeof(u32));
  445. if (ret < 0 && ret != -EEXIST) {
  446. dev_err(&pdev->dev, "unable to allocate shared state entry\n");
  447. return ret;
  448. }
  449. states = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL);
  450. if (IS_ERR(states)) {
  451. dev_err(&pdev->dev, "Unable to acquire shared state entry\n");
  452. return PTR_ERR(states);
  453. }
  454. /* Acquire the list of interrupt mask vectors */
  455. size = smsm->num_entries * smsm->num_hosts * sizeof(u32);
  456. ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, size);
  457. if (ret < 0 && ret != -EEXIST) {
  458. dev_err(&pdev->dev, "unable to allocate smsm interrupt mask\n");
  459. return ret;
  460. }
  461. intr_mask = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL);
  462. if (IS_ERR(intr_mask)) {
  463. dev_err(&pdev->dev, "unable to acquire shared memory interrupt mask\n");
  464. return PTR_ERR(intr_mask);
  465. }
  466. /* Setup the reference to the local state bits */
  467. smsm->local_state = states + smsm->local_host;
  468. smsm->subscription = intr_mask + smsm->local_host * smsm->num_hosts;
  469. /* Register the outgoing state */
  470. smsm->state = qcom_smem_state_register(local_node, &smsm_state_ops, smsm);
  471. if (IS_ERR(smsm->state)) {
  472. dev_err(smsm->dev, "failed to register qcom_smem_state\n");
  473. return PTR_ERR(smsm->state);
  474. }
  475. /* Register handlers for remote processor entries of interest. */
  476. for_each_available_child_of_node(pdev->dev.of_node, node) {
  477. if (!of_property_read_bool(node, "interrupt-controller"))
  478. continue;
  479. ret = of_property_read_u32(node, "reg", &id);
  480. if (ret || id >= smsm->num_entries) {
  481. dev_err(&pdev->dev, "invalid reg of entry\n");
  482. if (!ret)
  483. ret = -EINVAL;
  484. goto unwind_interfaces;
  485. }
  486. entry = &smsm->entries[id];
  487. entry->smsm = smsm;
  488. entry->remote_state = states + id;
  489. /* Setup subscription pointers and unsubscribe to any kicks */
  490. entry->subscription = intr_mask + id * smsm->num_hosts;
  491. writel(0, entry->subscription + smsm->local_host);
  492. ret = smsm_inbound_entry(smsm, entry, node);
  493. if (ret < 0)
  494. goto unwind_interfaces;
  495. }
  496. platform_set_drvdata(pdev, smsm);
  497. return 0;
  498. unwind_interfaces:
  499. for (id = 0; id < smsm->num_entries; id++)
  500. if (smsm->entries[id].domain)
  501. irq_domain_remove(smsm->entries[id].domain);
  502. qcom_smem_state_unregister(smsm->state);
  503. return ret;
  504. }
  505. static int qcom_smsm_remove(struct platform_device *pdev)
  506. {
  507. struct qcom_smsm *smsm = platform_get_drvdata(pdev);
  508. unsigned id;
  509. for (id = 0; id < smsm->num_entries; id++)
  510. if (smsm->entries[id].domain)
  511. irq_domain_remove(smsm->entries[id].domain);
  512. qcom_smem_state_unregister(smsm->state);
  513. return 0;
  514. }
  515. static const struct of_device_id qcom_smsm_of_match[] = {
  516. { .compatible = "qcom,smsm" },
  517. {}
  518. };
  519. MODULE_DEVICE_TABLE(of, qcom_smsm_of_match);
  520. static struct platform_driver qcom_smsm_driver = {
  521. .probe = qcom_smsm_probe,
  522. .remove = qcom_smsm_remove,
  523. .driver = {
  524. .name = "qcom-smsm",
  525. .of_match_table = qcom_smsm_of_match,
  526. },
  527. };
  528. module_platform_driver(qcom_smsm_driver);
  529. MODULE_DESCRIPTION("Qualcomm Shared Memory State Machine driver");
  530. MODULE_LICENSE("GPL v2");