llcc-qcom.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  4. *
  5. */
  6. #include <linux/bitmap.h>
  7. #include <linux/bitops.h>
  8. #include <linux/device.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/mutex.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/sizes.h>
  17. #include <linux/slab.h>
  18. #include <linux/soc/qcom/llcc-qcom.h>
  19. #define ACTIVATE BIT(0)
  20. #define DEACTIVATE BIT(1)
  21. #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
  22. #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
  23. #define ACT_CTRL_ACT_TRIG BIT(0)
  24. #define ACT_CTRL_OPCODE_SHIFT 0x01
  25. #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
  26. #define ATTR1_FIXED_SIZE_SHIFT 0x03
  27. #define ATTR1_PRIORITY_SHIFT 0x04
  28. #define ATTR1_MAX_CAP_SHIFT 0x10
  29. #define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
  30. #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
  31. #define ATTR0_BONUS_WAYS_SHIFT 0x10
  32. #define LLCC_STATUS_READ_DELAY 100
  33. #define CACHE_LINE_SIZE_SHIFT 6
  34. #define LLCC_COMMON_STATUS0 0x0003000c
  35. #define LLCC_LB_CNT_MASK GENMASK(31, 28)
  36. #define LLCC_LB_CNT_SHIFT 28
  37. #define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
  38. #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
  39. #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
  40. #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
  41. #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
  42. #define BANK_OFFSET_STRIDE 0x80000
  43. /**
  44. * llcc_slice_config - Data associated with the llcc slice
  45. * @usecase_id: Unique id for the client's use case
  46. * @slice_id: llcc slice id for each client
  47. * @max_cap: The maximum capacity of the cache slice provided in KB
  48. * @priority: Priority of the client used to select victim line for replacement
  49. * @fixed_size: Boolean indicating if the slice has a fixed capacity
  50. * @bonus_ways: Bonus ways are additional ways to be used for any slice,
  51. * if client ends up using more than reserved cache ways. Bonus
  52. * ways are allocated only if they are not reserved for some
  53. * other client.
  54. * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
  55. * be used by any other client than the one its assigned to.
  56. * @cache_mode: Each slice operates as a cache, this controls the mode of the
  57. * slice: normal or TCM(Tightly Coupled Memory)
  58. * @probe_target_ways: Determines what ways to probe for access hit. When
  59. * configured to 1 only bonus and reserved ways are probed.
  60. * When configured to 0 all ways in llcc are probed.
  61. * @dis_cap_alloc: Disable capacity based allocation for a client
  62. * @retain_on_pc: If this bit is set and client has maintained active vote
  63. * then the ways assigned to this client are not flushed on power
  64. * collapse.
  65. * @activate_on_init: Activate the slice immediately after it is programmed
  66. */
  67. struct llcc_slice_config {
  68. u32 usecase_id;
  69. u32 slice_id;
  70. u32 max_cap;
  71. u32 priority;
  72. bool fixed_size;
  73. u32 bonus_ways;
  74. u32 res_ways;
  75. u32 cache_mode;
  76. u32 probe_target_ways;
  77. bool dis_cap_alloc;
  78. bool retain_on_pc;
  79. bool activate_on_init;
  80. };
  81. struct qcom_llcc_config {
  82. const struct llcc_slice_config *sct_data;
  83. int size;
  84. };
  85. static const struct llcc_slice_config sc7180_data[] = {
  86. { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
  87. { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
  88. { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
  89. { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
  90. };
  91. static const struct llcc_slice_config sdm845_data[] = {
  92. { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
  93. { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
  94. { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
  95. { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
  96. { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  97. { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  98. { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
  99. { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  100. { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  101. { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
  102. { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
  103. { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
  104. { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  105. { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  106. { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  107. { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
  108. { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
  109. { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
  110. };
  111. static const struct qcom_llcc_config sc7180_cfg = {
  112. .sct_data = sc7180_data,
  113. .size = ARRAY_SIZE(sc7180_data),
  114. };
  115. static const struct qcom_llcc_config sdm845_cfg = {
  116. .sct_data = sdm845_data,
  117. .size = ARRAY_SIZE(sdm845_data),
  118. };
  119. static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
  120. /**
  121. * llcc_slice_getd - get llcc slice descriptor
  122. * @uid: usecase_id for the client
  123. *
  124. * A pointer to llcc slice descriptor will be returned on success and
  125. * and error pointer is returned on failure
  126. */
  127. struct llcc_slice_desc *llcc_slice_getd(u32 uid)
  128. {
  129. const struct llcc_slice_config *cfg;
  130. struct llcc_slice_desc *desc;
  131. u32 sz, count;
  132. if (IS_ERR(drv_data))
  133. return ERR_CAST(drv_data);
  134. cfg = drv_data->cfg;
  135. sz = drv_data->cfg_size;
  136. for (count = 0; cfg && count < sz; count++, cfg++)
  137. if (cfg->usecase_id == uid)
  138. break;
  139. if (count == sz || !cfg)
  140. return ERR_PTR(-ENODEV);
  141. desc = kzalloc(sizeof(*desc), GFP_KERNEL);
  142. if (!desc)
  143. return ERR_PTR(-ENOMEM);
  144. desc->slice_id = cfg->slice_id;
  145. desc->slice_size = cfg->max_cap;
  146. return desc;
  147. }
  148. EXPORT_SYMBOL_GPL(llcc_slice_getd);
  149. /**
  150. * llcc_slice_putd - llcc slice descritpor
  151. * @desc: Pointer to llcc slice descriptor
  152. */
  153. void llcc_slice_putd(struct llcc_slice_desc *desc)
  154. {
  155. if (!IS_ERR_OR_NULL(desc))
  156. kfree(desc);
  157. }
  158. EXPORT_SYMBOL_GPL(llcc_slice_putd);
  159. static int llcc_update_act_ctrl(u32 sid,
  160. u32 act_ctrl_reg_val, u32 status)
  161. {
  162. u32 act_ctrl_reg;
  163. u32 status_reg;
  164. u32 slice_status;
  165. int ret;
  166. if (IS_ERR(drv_data))
  167. return PTR_ERR(drv_data);
  168. act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
  169. status_reg = LLCC_TRP_STATUSn(sid);
  170. /* Set the ACTIVE trigger */
  171. act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
  172. ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
  173. act_ctrl_reg_val);
  174. if (ret)
  175. return ret;
  176. /* Clear the ACTIVE trigger */
  177. act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
  178. ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
  179. act_ctrl_reg_val);
  180. if (ret)
  181. return ret;
  182. ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
  183. slice_status, !(slice_status & status),
  184. 0, LLCC_STATUS_READ_DELAY);
  185. return ret;
  186. }
  187. /**
  188. * llcc_slice_activate - Activate the llcc slice
  189. * @desc: Pointer to llcc slice descriptor
  190. *
  191. * A value of zero will be returned on success and a negative errno will
  192. * be returned in error cases
  193. */
  194. int llcc_slice_activate(struct llcc_slice_desc *desc)
  195. {
  196. int ret;
  197. u32 act_ctrl_val;
  198. if (IS_ERR(drv_data))
  199. return PTR_ERR(drv_data);
  200. if (IS_ERR_OR_NULL(desc))
  201. return -EINVAL;
  202. mutex_lock(&drv_data->lock);
  203. if (test_bit(desc->slice_id, drv_data->bitmap)) {
  204. mutex_unlock(&drv_data->lock);
  205. return 0;
  206. }
  207. act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
  208. ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
  209. DEACTIVATE);
  210. if (ret) {
  211. mutex_unlock(&drv_data->lock);
  212. return ret;
  213. }
  214. __set_bit(desc->slice_id, drv_data->bitmap);
  215. mutex_unlock(&drv_data->lock);
  216. return ret;
  217. }
  218. EXPORT_SYMBOL_GPL(llcc_slice_activate);
  219. /**
  220. * llcc_slice_deactivate - Deactivate the llcc slice
  221. * @desc: Pointer to llcc slice descriptor
  222. *
  223. * A value of zero will be returned on success and a negative errno will
  224. * be returned in error cases
  225. */
  226. int llcc_slice_deactivate(struct llcc_slice_desc *desc)
  227. {
  228. u32 act_ctrl_val;
  229. int ret;
  230. if (IS_ERR(drv_data))
  231. return PTR_ERR(drv_data);
  232. if (IS_ERR_OR_NULL(desc))
  233. return -EINVAL;
  234. mutex_lock(&drv_data->lock);
  235. if (!test_bit(desc->slice_id, drv_data->bitmap)) {
  236. mutex_unlock(&drv_data->lock);
  237. return 0;
  238. }
  239. act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
  240. ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
  241. ACTIVATE);
  242. if (ret) {
  243. mutex_unlock(&drv_data->lock);
  244. return ret;
  245. }
  246. __clear_bit(desc->slice_id, drv_data->bitmap);
  247. mutex_unlock(&drv_data->lock);
  248. return ret;
  249. }
  250. EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
  251. /**
  252. * llcc_get_slice_id - return the slice id
  253. * @desc: Pointer to llcc slice descriptor
  254. */
  255. int llcc_get_slice_id(struct llcc_slice_desc *desc)
  256. {
  257. if (IS_ERR_OR_NULL(desc))
  258. return -EINVAL;
  259. return desc->slice_id;
  260. }
  261. EXPORT_SYMBOL_GPL(llcc_get_slice_id);
  262. /**
  263. * llcc_get_slice_size - return the slice id
  264. * @desc: Pointer to llcc slice descriptor
  265. */
  266. size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
  267. {
  268. if (IS_ERR_OR_NULL(desc))
  269. return 0;
  270. return desc->slice_size;
  271. }
  272. EXPORT_SYMBOL_GPL(llcc_get_slice_size);
  273. static int qcom_llcc_cfg_program(struct platform_device *pdev)
  274. {
  275. int i;
  276. u32 attr1_cfg;
  277. u32 attr0_cfg;
  278. u32 attr1_val;
  279. u32 attr0_val;
  280. u32 max_cap_cacheline;
  281. u32 sz;
  282. int ret = 0;
  283. const struct llcc_slice_config *llcc_table;
  284. struct llcc_slice_desc desc;
  285. sz = drv_data->cfg_size;
  286. llcc_table = drv_data->cfg;
  287. for (i = 0; i < sz; i++) {
  288. attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
  289. attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
  290. attr1_val = llcc_table[i].cache_mode;
  291. attr1_val |= llcc_table[i].probe_target_ways <<
  292. ATTR1_PROBE_TARGET_WAYS_SHIFT;
  293. attr1_val |= llcc_table[i].fixed_size <<
  294. ATTR1_FIXED_SIZE_SHIFT;
  295. attr1_val |= llcc_table[i].priority <<
  296. ATTR1_PRIORITY_SHIFT;
  297. max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
  298. /* LLCC instances can vary for each target.
  299. * The SW writes to broadcast register which gets propagated
  300. * to each llcc instace (llcc0,.. llccN).
  301. * Since the size of the memory is divided equally amongst the
  302. * llcc instances, we need to configure the max cap accordingly.
  303. */
  304. max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
  305. max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
  306. attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
  307. attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
  308. attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
  309. ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
  310. attr1_val);
  311. if (ret)
  312. return ret;
  313. ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
  314. attr0_val);
  315. if (ret)
  316. return ret;
  317. if (llcc_table[i].activate_on_init) {
  318. desc.slice_id = llcc_table[i].slice_id;
  319. ret = llcc_slice_activate(&desc);
  320. }
  321. }
  322. return ret;
  323. }
  324. static int qcom_llcc_remove(struct platform_device *pdev)
  325. {
  326. /* Set the global pointer to a error code to avoid referencing it */
  327. drv_data = ERR_PTR(-ENODEV);
  328. return 0;
  329. }
  330. static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
  331. const char *name)
  332. {
  333. void __iomem *base;
  334. struct regmap_config llcc_regmap_config = {
  335. .reg_bits = 32,
  336. .reg_stride = 4,
  337. .val_bits = 32,
  338. .fast_io = true,
  339. };
  340. base = devm_platform_ioremap_resource_byname(pdev, name);
  341. if (IS_ERR(base))
  342. return ERR_CAST(base);
  343. llcc_regmap_config.name = name;
  344. return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
  345. }
  346. static int qcom_llcc_probe(struct platform_device *pdev)
  347. {
  348. u32 num_banks;
  349. struct device *dev = &pdev->dev;
  350. int ret, i;
  351. struct platform_device *llcc_edac;
  352. const struct qcom_llcc_config *cfg;
  353. const struct llcc_slice_config *llcc_cfg;
  354. u32 sz;
  355. drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
  356. if (!drv_data) {
  357. ret = -ENOMEM;
  358. goto err;
  359. }
  360. drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base");
  361. if (IS_ERR(drv_data->regmap)) {
  362. ret = PTR_ERR(drv_data->regmap);
  363. goto err;
  364. }
  365. drv_data->bcast_regmap =
  366. qcom_llcc_init_mmio(pdev, "llcc_broadcast_base");
  367. if (IS_ERR(drv_data->bcast_regmap)) {
  368. ret = PTR_ERR(drv_data->bcast_regmap);
  369. goto err;
  370. }
  371. ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
  372. &num_banks);
  373. if (ret)
  374. goto err;
  375. num_banks &= LLCC_LB_CNT_MASK;
  376. num_banks >>= LLCC_LB_CNT_SHIFT;
  377. drv_data->num_banks = num_banks;
  378. cfg = of_device_get_match_data(&pdev->dev);
  379. llcc_cfg = cfg->sct_data;
  380. sz = cfg->size;
  381. for (i = 0; i < sz; i++)
  382. if (llcc_cfg[i].slice_id > drv_data->max_slices)
  383. drv_data->max_slices = llcc_cfg[i].slice_id;
  384. drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32),
  385. GFP_KERNEL);
  386. if (!drv_data->offsets) {
  387. ret = -ENOMEM;
  388. goto err;
  389. }
  390. for (i = 0; i < num_banks; i++)
  391. drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
  392. drv_data->bitmap = devm_kcalloc(dev,
  393. BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
  394. GFP_KERNEL);
  395. if (!drv_data->bitmap) {
  396. ret = -ENOMEM;
  397. goto err;
  398. }
  399. drv_data->cfg = llcc_cfg;
  400. drv_data->cfg_size = sz;
  401. mutex_init(&drv_data->lock);
  402. platform_set_drvdata(pdev, drv_data);
  403. ret = qcom_llcc_cfg_program(pdev);
  404. if (ret)
  405. goto err;
  406. drv_data->ecc_irq = platform_get_irq(pdev, 0);
  407. if (drv_data->ecc_irq >= 0) {
  408. llcc_edac = platform_device_register_data(&pdev->dev,
  409. "qcom_llcc_edac", -1, drv_data,
  410. sizeof(*drv_data));
  411. if (IS_ERR(llcc_edac))
  412. dev_err(dev, "Failed to register llcc edac driver\n");
  413. }
  414. return 0;
  415. err:
  416. drv_data = ERR_PTR(-ENODEV);
  417. return ret;
  418. }
  419. static const struct of_device_id qcom_llcc_of_match[] = {
  420. { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
  421. { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
  422. { }
  423. };
  424. static struct platform_driver qcom_llcc_driver = {
  425. .driver = {
  426. .name = "qcom-llcc",
  427. .of_match_table = qcom_llcc_of_match,
  428. },
  429. .probe = qcom_llcc_probe,
  430. .remove = qcom_llcc_remove,
  431. };
  432. module_platform_driver(qcom_llcc_driver);
  433. MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
  434. MODULE_LICENSE("GPL v2");