cpr.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2019, Linaro Limited
  5. */
  6. #include <linux/module.h>
  7. #include <linux/err.h>
  8. #include <linux/debugfs.h>
  9. #include <linux/string.h>
  10. #include <linux/kernel.h>
  11. #include <linux/list.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/bitops.h>
  15. #include <linux/slab.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_domain.h>
  20. #include <linux/pm_opp.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/regmap.h>
  23. #include <linux/mfd/syscon.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <linux/clk.h>
  26. #include <linux/nvmem-consumer.h>
  27. /* Register Offsets for RB-CPR and Bit Definitions */
  28. /* RBCPR Version Register */
  29. #define REG_RBCPR_VERSION 0
  30. #define RBCPR_VER_2 0x02
  31. #define FLAGS_IGNORE_1ST_IRQ_STATUS BIT(0)
  32. /* RBCPR Gate Count and Target Registers */
  33. #define REG_RBCPR_GCNT_TARGET(n) (0x60 + 4 * (n))
  34. #define RBCPR_GCNT_TARGET_TARGET_SHIFT 0
  35. #define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0)
  36. #define RBCPR_GCNT_TARGET_GCNT_SHIFT 12
  37. #define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0)
  38. /* RBCPR Timer Control */
  39. #define REG_RBCPR_TIMER_INTERVAL 0x44
  40. #define REG_RBIF_TIMER_ADJUST 0x4c
  41. #define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0)
  42. #define RBIF_TIMER_ADJ_CONS_UP_SHIFT 0
  43. #define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0)
  44. #define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4
  45. #define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0)
  46. #define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8
  47. /* RBCPR Config Register */
  48. #define REG_RBIF_LIMIT 0x48
  49. #define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0)
  50. #define RBIF_LIMIT_CEILING_SHIFT 6
  51. #define RBIF_LIMIT_FLOOR_BITS 6
  52. #define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0)
  53. #define RBIF_LIMIT_CEILING_DEFAULT RBIF_LIMIT_CEILING_MASK
  54. #define RBIF_LIMIT_FLOOR_DEFAULT 0
  55. #define REG_RBIF_SW_VLEVEL 0x94
  56. #define RBIF_SW_VLEVEL_DEFAULT 0x20
  57. #define REG_RBCPR_STEP_QUOT 0x80
  58. #define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0)
  59. #define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0)
  60. #define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8
  61. /* RBCPR Control Register */
  62. #define REG_RBCPR_CTL 0x90
  63. #define RBCPR_CTL_LOOP_EN BIT(0)
  64. #define RBCPR_CTL_TIMER_EN BIT(3)
  65. #define RBCPR_CTL_SW_AUTO_CONT_ACK_EN BIT(5)
  66. #define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN BIT(6)
  67. #define RBCPR_CTL_COUNT_MODE BIT(10)
  68. #define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0)
  69. #define RBCPR_CTL_UP_THRESHOLD_SHIFT 24
  70. #define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0)
  71. #define RBCPR_CTL_DN_THRESHOLD_SHIFT 28
  72. /* RBCPR Ack/Nack Response */
  73. #define REG_RBIF_CONT_ACK_CMD 0x98
  74. #define REG_RBIF_CONT_NACK_CMD 0x9c
  75. /* RBCPR Result status Register */
  76. #define REG_RBCPR_RESULT_0 0xa0
  77. #define RBCPR_RESULT0_BUSY_SHIFT 19
  78. #define RBCPR_RESULT0_BUSY_MASK BIT(RBCPR_RESULT0_BUSY_SHIFT)
  79. #define RBCPR_RESULT0_ERROR_LT0_SHIFT 18
  80. #define RBCPR_RESULT0_ERROR_SHIFT 6
  81. #define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0)
  82. #define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
  83. #define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)
  84. #define RBCPR_RESULT0_STEP_UP_SHIFT 1
  85. /* RBCPR Interrupt Control Register */
  86. #define REG_RBIF_IRQ_EN(n) (0x100 + 4 * (n))
  87. #define REG_RBIF_IRQ_CLEAR 0x110
  88. #define REG_RBIF_IRQ_STATUS 0x114
  89. #define CPR_INT_DONE BIT(0)
  90. #define CPR_INT_MIN BIT(1)
  91. #define CPR_INT_DOWN BIT(2)
  92. #define CPR_INT_MID BIT(3)
  93. #define CPR_INT_UP BIT(4)
  94. #define CPR_INT_MAX BIT(5)
  95. #define CPR_INT_CLAMP BIT(6)
  96. #define CPR_INT_ALL (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
  97. CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
  98. #define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN)
  99. #define CPR_NUM_RING_OSC 8
  100. /* CPR eFuse parameters */
  101. #define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)
  102. #define CPR_FUSE_MIN_QUOT_DIFF 50
  103. #define FUSE_REVISION_UNKNOWN (-1)
  104. enum voltage_change_dir {
  105. NO_CHANGE,
  106. DOWN,
  107. UP,
  108. };
  109. struct cpr_fuse {
  110. char *ring_osc;
  111. char *init_voltage;
  112. char *quotient;
  113. char *quotient_offset;
  114. };
  115. struct fuse_corner_data {
  116. int ref_uV;
  117. int max_uV;
  118. int min_uV;
  119. int max_volt_scale;
  120. int max_quot_scale;
  121. /* fuse quot */
  122. int quot_offset;
  123. int quot_scale;
  124. int quot_adjust;
  125. /* fuse quot_offset */
  126. int quot_offset_scale;
  127. int quot_offset_adjust;
  128. };
  129. struct cpr_fuses {
  130. int init_voltage_step;
  131. int init_voltage_width;
  132. struct fuse_corner_data *fuse_corner_data;
  133. };
  134. struct corner_data {
  135. unsigned int fuse_corner;
  136. unsigned long freq;
  137. };
  138. struct cpr_desc {
  139. unsigned int num_fuse_corners;
  140. int min_diff_quot;
  141. int *step_quot;
  142. unsigned int timer_delay_us;
  143. unsigned int timer_cons_up;
  144. unsigned int timer_cons_down;
  145. unsigned int up_threshold;
  146. unsigned int down_threshold;
  147. unsigned int idle_clocks;
  148. unsigned int gcnt_us;
  149. unsigned int vdd_apc_step_up_limit;
  150. unsigned int vdd_apc_step_down_limit;
  151. unsigned int clamp_timer_interval;
  152. struct cpr_fuses cpr_fuses;
  153. bool reduce_to_fuse_uV;
  154. bool reduce_to_corner_uV;
  155. };
  156. struct acc_desc {
  157. unsigned int enable_reg;
  158. u32 enable_mask;
  159. struct reg_sequence *config;
  160. struct reg_sequence *settings;
  161. int num_regs_per_fuse;
  162. };
  163. struct cpr_acc_desc {
  164. const struct cpr_desc *cpr_desc;
  165. const struct acc_desc *acc_desc;
  166. };
  167. struct fuse_corner {
  168. int min_uV;
  169. int max_uV;
  170. int uV;
  171. int quot;
  172. int step_quot;
  173. const struct reg_sequence *accs;
  174. int num_accs;
  175. unsigned long max_freq;
  176. u8 ring_osc_idx;
  177. };
  178. struct corner {
  179. int min_uV;
  180. int max_uV;
  181. int uV;
  182. int last_uV;
  183. int quot_adjust;
  184. u32 save_ctl;
  185. u32 save_irq;
  186. unsigned long freq;
  187. struct fuse_corner *fuse_corner;
  188. };
  189. struct cpr_drv {
  190. unsigned int num_corners;
  191. unsigned int ref_clk_khz;
  192. struct generic_pm_domain pd;
  193. struct device *dev;
  194. struct device *attached_cpu_dev;
  195. struct mutex lock;
  196. void __iomem *base;
  197. struct corner *corner;
  198. struct regulator *vdd_apc;
  199. struct clk *cpu_clk;
  200. struct regmap *tcsr;
  201. bool loop_disabled;
  202. u32 gcnt;
  203. unsigned long flags;
  204. struct fuse_corner *fuse_corners;
  205. struct corner *corners;
  206. const struct cpr_desc *desc;
  207. const struct acc_desc *acc_desc;
  208. const struct cpr_fuse *cpr_fuses;
  209. struct dentry *debugfs;
  210. };
  211. static bool cpr_is_allowed(struct cpr_drv *drv)
  212. {
  213. return !drv->loop_disabled;
  214. }
  215. static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
  216. {
  217. writel_relaxed(value, drv->base + offset);
  218. }
  219. static u32 cpr_read(struct cpr_drv *drv, u32 offset)
  220. {
  221. return readl_relaxed(drv->base + offset);
  222. }
  223. static void
  224. cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
  225. {
  226. u32 val;
  227. val = readl_relaxed(drv->base + offset);
  228. val &= ~mask;
  229. val |= value & mask;
  230. writel_relaxed(val, drv->base + offset);
  231. }
  232. static void cpr_irq_clr(struct cpr_drv *drv)
  233. {
  234. cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
  235. }
  236. static void cpr_irq_clr_nack(struct cpr_drv *drv)
  237. {
  238. cpr_irq_clr(drv);
  239. cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
  240. }
  241. static void cpr_irq_clr_ack(struct cpr_drv *drv)
  242. {
  243. cpr_irq_clr(drv);
  244. cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
  245. }
  246. static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
  247. {
  248. cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
  249. }
  250. static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
  251. {
  252. cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
  253. }
  254. static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
  255. {
  256. u32 val, mask;
  257. const struct cpr_desc *desc = drv->desc;
  258. /* Program Consecutive Up & Down */
  259. val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
  260. val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
  261. mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
  262. cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
  263. cpr_masked_write(drv, REG_RBCPR_CTL,
  264. RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
  265. RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
  266. corner->save_ctl);
  267. cpr_irq_set(drv, corner->save_irq);
  268. if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV)
  269. val = RBCPR_CTL_LOOP_EN;
  270. else
  271. val = 0;
  272. cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
  273. }
  274. static void cpr_ctl_disable(struct cpr_drv *drv)
  275. {
  276. cpr_irq_set(drv, 0);
  277. cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
  278. RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
  279. cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
  280. RBIF_TIMER_ADJ_CONS_UP_MASK |
  281. RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
  282. cpr_irq_clr(drv);
  283. cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
  284. cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
  285. cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
  286. }
  287. static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
  288. {
  289. u32 reg_val;
  290. reg_val = cpr_read(drv, REG_RBCPR_CTL);
  291. return reg_val & RBCPR_CTL_LOOP_EN;
  292. }
  293. static bool cpr_ctl_is_busy(struct cpr_drv *drv)
  294. {
  295. u32 reg_val;
  296. reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
  297. return reg_val & RBCPR_RESULT0_BUSY_MASK;
  298. }
  299. static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
  300. {
  301. corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
  302. corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
  303. }
  304. static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
  305. {
  306. u32 gcnt, ctl, irq, ro_sel, step_quot;
  307. struct fuse_corner *fuse = corner->fuse_corner;
  308. const struct cpr_desc *desc = drv->desc;
  309. int i;
  310. ro_sel = fuse->ring_osc_idx;
  311. gcnt = drv->gcnt;
  312. gcnt |= fuse->quot - corner->quot_adjust;
  313. /* Program the step quotient and idle clocks */
  314. step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
  315. step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
  316. cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
  317. /* Clear the target quotient value and gate count of all ROs */
  318. for (i = 0; i < CPR_NUM_RING_OSC; i++)
  319. cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
  320. cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
  321. ctl = corner->save_ctl;
  322. cpr_write(drv, REG_RBCPR_CTL, ctl);
  323. irq = corner->save_irq;
  324. cpr_irq_set(drv, irq);
  325. dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt,
  326. ctl, irq);
  327. }
  328. static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
  329. struct fuse_corner *end)
  330. {
  331. if (f == end)
  332. return;
  333. if (f < end) {
  334. for (f += 1; f <= end; f++)
  335. regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
  336. } else {
  337. for (f -= 1; f >= end; f--)
  338. regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
  339. }
  340. }
  341. static int cpr_pre_voltage(struct cpr_drv *drv,
  342. struct fuse_corner *fuse_corner,
  343. enum voltage_change_dir dir)
  344. {
  345. struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
  346. if (drv->tcsr && dir == DOWN)
  347. cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
  348. return 0;
  349. }
  350. static int cpr_post_voltage(struct cpr_drv *drv,
  351. struct fuse_corner *fuse_corner,
  352. enum voltage_change_dir dir)
  353. {
  354. struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
  355. if (drv->tcsr && dir == UP)
  356. cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
  357. return 0;
  358. }
  359. static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
  360. int new_uV, enum voltage_change_dir dir)
  361. {
  362. int ret;
  363. struct fuse_corner *fuse_corner = corner->fuse_corner;
  364. ret = cpr_pre_voltage(drv, fuse_corner, dir);
  365. if (ret)
  366. return ret;
  367. ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
  368. if (ret) {
  369. dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
  370. new_uV);
  371. return ret;
  372. }
  373. ret = cpr_post_voltage(drv, fuse_corner, dir);
  374. if (ret)
  375. return ret;
  376. return 0;
  377. }
  378. static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv)
  379. {
  380. return drv->corner ? drv->corner - drv->corners + 1 : 0;
  381. }
  382. static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
  383. {
  384. u32 val, error_steps, reg_mask;
  385. int last_uV, new_uV, step_uV, ret;
  386. struct corner *corner;
  387. const struct cpr_desc *desc = drv->desc;
  388. if (dir != UP && dir != DOWN)
  389. return 0;
  390. step_uV = regulator_get_linear_step(drv->vdd_apc);
  391. if (!step_uV)
  392. return -EINVAL;
  393. corner = drv->corner;
  394. val = cpr_read(drv, REG_RBCPR_RESULT_0);
  395. error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
  396. error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
  397. last_uV = corner->last_uV;
  398. if (dir == UP) {
  399. if (desc->clamp_timer_interval &&
  400. error_steps < desc->up_threshold) {
  401. /*
  402. * Handle the case where another measurement started
  403. * after the interrupt was triggered due to a core
  404. * exiting from power collapse.
  405. */
  406. error_steps = max(desc->up_threshold,
  407. desc->vdd_apc_step_up_limit);
  408. }
  409. if (last_uV >= corner->max_uV) {
  410. cpr_irq_clr_nack(drv);
  411. /* Maximize the UP threshold */
  412. reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
  413. reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
  414. val = reg_mask;
  415. cpr_ctl_modify(drv, reg_mask, val);
  416. /* Disable UP interrupt */
  417. cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
  418. return 0;
  419. }
  420. if (error_steps > desc->vdd_apc_step_up_limit)
  421. error_steps = desc->vdd_apc_step_up_limit;
  422. /* Calculate new voltage */
  423. new_uV = last_uV + error_steps * step_uV;
  424. new_uV = min(new_uV, corner->max_uV);
  425. dev_dbg(drv->dev,
  426. "UP: -> new_uV: %d last_uV: %d perf state: %u\n",
  427. new_uV, last_uV, cpr_get_cur_perf_state(drv));
  428. } else {
  429. if (desc->clamp_timer_interval &&
  430. error_steps < desc->down_threshold) {
  431. /*
  432. * Handle the case where another measurement started
  433. * after the interrupt was triggered due to a core
  434. * exiting from power collapse.
  435. */
  436. error_steps = max(desc->down_threshold,
  437. desc->vdd_apc_step_down_limit);
  438. }
  439. if (last_uV <= corner->min_uV) {
  440. cpr_irq_clr_nack(drv);
  441. /* Enable auto nack down */
  442. reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
  443. val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
  444. cpr_ctl_modify(drv, reg_mask, val);
  445. /* Disable DOWN interrupt */
  446. cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
  447. return 0;
  448. }
  449. if (error_steps > desc->vdd_apc_step_down_limit)
  450. error_steps = desc->vdd_apc_step_down_limit;
  451. /* Calculate new voltage */
  452. new_uV = last_uV - error_steps * step_uV;
  453. new_uV = max(new_uV, corner->min_uV);
  454. dev_dbg(drv->dev,
  455. "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n",
  456. new_uV, last_uV, cpr_get_cur_perf_state(drv));
  457. }
  458. ret = cpr_scale_voltage(drv, corner, new_uV, dir);
  459. if (ret) {
  460. cpr_irq_clr_nack(drv);
  461. return ret;
  462. }
  463. drv->corner->last_uV = new_uV;
  464. if (dir == UP) {
  465. /* Disable auto nack down */
  466. reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
  467. val = 0;
  468. } else {
  469. /* Restore default threshold for UP */
  470. reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
  471. reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
  472. val = desc->up_threshold;
  473. val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
  474. }
  475. cpr_ctl_modify(drv, reg_mask, val);
  476. /* Re-enable default interrupts */
  477. cpr_irq_set(drv, CPR_INT_DEFAULT);
  478. /* Ack */
  479. cpr_irq_clr_ack(drv);
  480. return 0;
  481. }
  482. static irqreturn_t cpr_irq_handler(int irq, void *dev)
  483. {
  484. struct cpr_drv *drv = dev;
  485. const struct cpr_desc *desc = drv->desc;
  486. irqreturn_t ret = IRQ_HANDLED;
  487. u32 val;
  488. mutex_lock(&drv->lock);
  489. val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
  490. if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
  491. val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
  492. dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
  493. if (!cpr_ctl_is_enabled(drv)) {
  494. dev_dbg(drv->dev, "CPR is disabled\n");
  495. ret = IRQ_NONE;
  496. } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) {
  497. dev_dbg(drv->dev, "CPR measurement is not ready\n");
  498. } else if (!cpr_is_allowed(drv)) {
  499. val = cpr_read(drv, REG_RBCPR_CTL);
  500. dev_err_ratelimited(drv->dev,
  501. "Interrupt broken? RBCPR_CTL = %#02x\n",
  502. val);
  503. ret = IRQ_NONE;
  504. } else {
  505. /*
  506. * Following sequence of handling is as per each IRQ's
  507. * priority
  508. */
  509. if (val & CPR_INT_UP) {
  510. cpr_scale(drv, UP);
  511. } else if (val & CPR_INT_DOWN) {
  512. cpr_scale(drv, DOWN);
  513. } else if (val & CPR_INT_MIN) {
  514. cpr_irq_clr_nack(drv);
  515. } else if (val & CPR_INT_MAX) {
  516. cpr_irq_clr_nack(drv);
  517. } else if (val & CPR_INT_MID) {
  518. /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
  519. dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
  520. } else {
  521. dev_dbg(drv->dev,
  522. "IRQ occurred for unknown flag (%#08x)\n", val);
  523. }
  524. /* Save register values for the corner */
  525. cpr_corner_save(drv, drv->corner);
  526. }
  527. mutex_unlock(&drv->lock);
  528. return ret;
  529. }
  530. static int cpr_enable(struct cpr_drv *drv)
  531. {
  532. int ret;
  533. ret = regulator_enable(drv->vdd_apc);
  534. if (ret)
  535. return ret;
  536. mutex_lock(&drv->lock);
  537. if (cpr_is_allowed(drv) && drv->corner) {
  538. cpr_irq_clr(drv);
  539. cpr_corner_restore(drv, drv->corner);
  540. cpr_ctl_enable(drv, drv->corner);
  541. }
  542. mutex_unlock(&drv->lock);
  543. return 0;
  544. }
  545. static int cpr_disable(struct cpr_drv *drv)
  546. {
  547. mutex_lock(&drv->lock);
  548. if (cpr_is_allowed(drv)) {
  549. cpr_ctl_disable(drv);
  550. cpr_irq_clr(drv);
  551. }
  552. mutex_unlock(&drv->lock);
  553. return regulator_disable(drv->vdd_apc);
  554. }
  555. static int cpr_config(struct cpr_drv *drv)
  556. {
  557. int i;
  558. u32 val, gcnt;
  559. struct corner *corner;
  560. const struct cpr_desc *desc = drv->desc;
  561. /* Disable interrupt and CPR */
  562. cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
  563. cpr_write(drv, REG_RBCPR_CTL, 0);
  564. /* Program the default HW ceiling, floor and vlevel */
  565. val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
  566. << RBIF_LIMIT_CEILING_SHIFT;
  567. val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
  568. cpr_write(drv, REG_RBIF_LIMIT, val);
  569. cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
  570. /*
  571. * Clear the target quotient value and gate count of all
  572. * ring oscillators
  573. */
  574. for (i = 0; i < CPR_NUM_RING_OSC; i++)
  575. cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
  576. /* Init and save gcnt */
  577. gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000;
  578. gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
  579. gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
  580. drv->gcnt = gcnt;
  581. /* Program the delay count for the timer */
  582. val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
  583. cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
  584. dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
  585. desc->timer_delay_us);
  586. /* Program Consecutive Up & Down */
  587. val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
  588. val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
  589. val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
  590. cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
  591. /* Program the control register */
  592. val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
  593. val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
  594. val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
  595. val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
  596. cpr_write(drv, REG_RBCPR_CTL, val);
  597. for (i = 0; i < drv->num_corners; i++) {
  598. corner = &drv->corners[i];
  599. corner->save_ctl = val;
  600. corner->save_irq = CPR_INT_DEFAULT;
  601. }
  602. cpr_irq_set(drv, CPR_INT_DEFAULT);
  603. val = cpr_read(drv, REG_RBCPR_VERSION);
  604. if (val <= RBCPR_VER_2)
  605. drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
  606. return 0;
  607. }
  608. static int cpr_set_performance_state(struct generic_pm_domain *domain,
  609. unsigned int state)
  610. {
  611. struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
  612. struct corner *corner, *end;
  613. enum voltage_change_dir dir;
  614. int ret = 0, new_uV;
  615. mutex_lock(&drv->lock);
  616. dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n",
  617. __func__, state, cpr_get_cur_perf_state(drv));
  618. /*
  619. * Determine new corner we're going to.
  620. * Remove one since lowest performance state is 1.
  621. */
  622. corner = drv->corners + state - 1;
  623. end = &drv->corners[drv->num_corners - 1];
  624. if (corner > end || corner < drv->corners) {
  625. ret = -EINVAL;
  626. goto unlock;
  627. }
  628. /* Determine direction */
  629. if (drv->corner > corner)
  630. dir = DOWN;
  631. else if (drv->corner < corner)
  632. dir = UP;
  633. else
  634. dir = NO_CHANGE;
  635. if (cpr_is_allowed(drv))
  636. new_uV = corner->last_uV;
  637. else
  638. new_uV = corner->uV;
  639. if (cpr_is_allowed(drv))
  640. cpr_ctl_disable(drv);
  641. ret = cpr_scale_voltage(drv, corner, new_uV, dir);
  642. if (ret)
  643. goto unlock;
  644. if (cpr_is_allowed(drv)) {
  645. cpr_irq_clr(drv);
  646. if (drv->corner != corner)
  647. cpr_corner_restore(drv, corner);
  648. cpr_ctl_enable(drv, corner);
  649. }
  650. drv->corner = corner;
  651. unlock:
  652. mutex_unlock(&drv->lock);
  653. return ret;
  654. }
  655. static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data)
  656. {
  657. struct nvmem_cell *cell;
  658. ssize_t len;
  659. char *ret;
  660. int i;
  661. *data = 0;
  662. cell = nvmem_cell_get(dev, cname);
  663. if (IS_ERR(cell)) {
  664. if (PTR_ERR(cell) != -EPROBE_DEFER)
  665. dev_err(dev, "undefined cell %s\n", cname);
  666. return PTR_ERR(cell);
  667. }
  668. ret = nvmem_cell_read(cell, &len);
  669. nvmem_cell_put(cell);
  670. if (IS_ERR(ret)) {
  671. dev_err(dev, "can't read cell %s\n", cname);
  672. return PTR_ERR(ret);
  673. }
  674. for (i = 0; i < len; i++)
  675. *data |= ret[i] << (8 * i);
  676. kfree(ret);
  677. dev_dbg(dev, "efuse read(%s) = %x, bytes %zd\n", cname, *data, len);
  678. return 0;
  679. }
  680. static int
  681. cpr_populate_ring_osc_idx(struct cpr_drv *drv)
  682. {
  683. struct fuse_corner *fuse = drv->fuse_corners;
  684. struct fuse_corner *end = fuse + drv->desc->num_fuse_corners;
  685. const struct cpr_fuse *fuses = drv->cpr_fuses;
  686. u32 data;
  687. int ret;
  688. for (; fuse < end; fuse++, fuses++) {
  689. ret = cpr_read_efuse(drv->dev, fuses->ring_osc,
  690. &data);
  691. if (ret)
  692. return ret;
  693. fuse->ring_osc_idx = data;
  694. }
  695. return 0;
  696. }
  697. static int cpr_read_fuse_uV(const struct cpr_desc *desc,
  698. const struct fuse_corner_data *fdata,
  699. const char *init_v_efuse,
  700. int step_volt,
  701. struct cpr_drv *drv)
  702. {
  703. int step_size_uV, steps, uV;
  704. u32 bits = 0;
  705. int ret;
  706. ret = cpr_read_efuse(drv->dev, init_v_efuse, &bits);
  707. if (ret)
  708. return ret;
  709. steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);
  710. /* Not two's complement.. instead highest bit is sign bit */
  711. if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1))
  712. steps = -steps;
  713. step_size_uV = desc->cpr_fuses.init_voltage_step;
  714. uV = fdata->ref_uV + steps * step_size_uV;
  715. return DIV_ROUND_UP(uV, step_volt) * step_volt;
  716. }
  717. static int cpr_fuse_corner_init(struct cpr_drv *drv)
  718. {
  719. const struct cpr_desc *desc = drv->desc;
  720. const struct cpr_fuse *fuses = drv->cpr_fuses;
  721. const struct acc_desc *acc_desc = drv->acc_desc;
  722. int i;
  723. unsigned int step_volt;
  724. struct fuse_corner_data *fdata;
  725. struct fuse_corner *fuse, *end;
  726. int uV;
  727. const struct reg_sequence *accs;
  728. int ret;
  729. accs = acc_desc->settings;
  730. step_volt = regulator_get_linear_step(drv->vdd_apc);
  731. if (!step_volt)
  732. return -EINVAL;
  733. /* Populate fuse_corner members */
  734. fuse = drv->fuse_corners;
  735. end = &fuse[desc->num_fuse_corners - 1];
  736. fdata = desc->cpr_fuses.fuse_corner_data;
  737. for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) {
  738. /*
  739. * Update SoC voltages: platforms might choose a different
  740. * regulators than the one used to characterize the algorithms
  741. * (ie, init_voltage_step).
  742. */
  743. fdata->min_uV = roundup(fdata->min_uV, step_volt);
  744. fdata->max_uV = roundup(fdata->max_uV, step_volt);
  745. /* Populate uV */
  746. uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
  747. step_volt, drv);
  748. if (uV < 0)
  749. return uV;
  750. fuse->min_uV = fdata->min_uV;
  751. fuse->max_uV = fdata->max_uV;
  752. fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
  753. if (fuse == end) {
  754. /*
  755. * Allow the highest fuse corner's PVS voltage to
  756. * define the ceiling voltage for that corner in order
  757. * to support SoC's in which variable ceiling values
  758. * are required.
  759. */
  760. end->max_uV = max(end->max_uV, end->uV);
  761. }
  762. /* Populate target quotient by scaling */
  763. ret = cpr_read_efuse(drv->dev, fuses->quotient, &fuse->quot);
  764. if (ret)
  765. return ret;
  766. fuse->quot *= fdata->quot_scale;
  767. fuse->quot += fdata->quot_offset;
  768. fuse->quot += fdata->quot_adjust;
  769. fuse->step_quot = desc->step_quot[fuse->ring_osc_idx];
  770. /* Populate acc settings */
  771. fuse->accs = accs;
  772. fuse->num_accs = acc_desc->num_regs_per_fuse;
  773. accs += acc_desc->num_regs_per_fuse;
  774. }
  775. /*
  776. * Restrict all fuse corner PVS voltages based upon per corner
  777. * ceiling and floor voltages.
  778. */
  779. for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
  780. if (fuse->uV > fuse->max_uV)
  781. fuse->uV = fuse->max_uV;
  782. else if (fuse->uV < fuse->min_uV)
  783. fuse->uV = fuse->min_uV;
  784. ret = regulator_is_supported_voltage(drv->vdd_apc,
  785. fuse->min_uV,
  786. fuse->min_uV);
  787. if (!ret) {
  788. dev_err(drv->dev,
  789. "min uV: %d (fuse corner: %d) not supported by regulator\n",
  790. fuse->min_uV, i);
  791. return -EINVAL;
  792. }
  793. ret = regulator_is_supported_voltage(drv->vdd_apc,
  794. fuse->max_uV,
  795. fuse->max_uV);
  796. if (!ret) {
  797. dev_err(drv->dev,
  798. "max uV: %d (fuse corner: %d) not supported by regulator\n",
  799. fuse->max_uV, i);
  800. return -EINVAL;
  801. }
  802. dev_dbg(drv->dev,
  803. "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n",
  804. i, fuse->min_uV, fuse->uV, fuse->max_uV,
  805. fuse->ring_osc_idx, fuse->quot, fuse->step_quot);
  806. }
  807. return 0;
  808. }
  809. static int cpr_calculate_scaling(const char *quot_offset,
  810. struct cpr_drv *drv,
  811. const struct fuse_corner_data *fdata,
  812. const struct corner *corner)
  813. {
  814. u32 quot_diff = 0;
  815. unsigned long freq_diff;
  816. int scaling;
  817. const struct fuse_corner *fuse, *prev_fuse;
  818. int ret;
  819. fuse = corner->fuse_corner;
  820. prev_fuse = fuse - 1;
  821. if (quot_offset) {
  822. ret = cpr_read_efuse(drv->dev, quot_offset, &quot_diff);
  823. if (ret)
  824. return ret;
  825. quot_diff *= fdata->quot_offset_scale;
  826. quot_diff += fdata->quot_offset_adjust;
  827. } else {
  828. quot_diff = fuse->quot - prev_fuse->quot;
  829. }
  830. freq_diff = fuse->max_freq - prev_fuse->max_freq;
  831. freq_diff /= 1000000; /* Convert to MHz */
  832. scaling = 1000 * quot_diff / freq_diff;
  833. return min(scaling, fdata->max_quot_scale);
  834. }
  835. static int cpr_interpolate(const struct corner *corner, int step_volt,
  836. const struct fuse_corner_data *fdata)
  837. {
  838. unsigned long f_high, f_low, f_diff;
  839. int uV_high, uV_low, uV;
  840. u64 temp, temp_limit;
  841. const struct fuse_corner *fuse, *prev_fuse;
  842. fuse = corner->fuse_corner;
  843. prev_fuse = fuse - 1;
  844. f_high = fuse->max_freq;
  845. f_low = prev_fuse->max_freq;
  846. uV_high = fuse->uV;
  847. uV_low = prev_fuse->uV;
  848. f_diff = fuse->max_freq - corner->freq;
  849. /*
  850. * Don't interpolate in the wrong direction. This could happen
  851. * if the adjusted fuse voltage overlaps with the previous fuse's
  852. * adjusted voltage.
  853. */
  854. if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
  855. return corner->uV;
  856. temp = f_diff * (uV_high - uV_low);
  857. temp = div64_ul(temp, f_high - f_low);
  858. /*
  859. * max_volt_scale has units of uV/MHz while freq values
  860. * have units of Hz. Divide by 1000000 to convert to.
  861. */
  862. temp_limit = f_diff * fdata->max_volt_scale;
  863. do_div(temp_limit, 1000000);
  864. uV = uV_high - min(temp, temp_limit);
  865. return roundup(uV, step_volt);
  866. }
  867. static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
  868. {
  869. struct device_node *np;
  870. unsigned int fuse_corner = 0;
  871. np = dev_pm_opp_get_of_node(opp);
  872. if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner))
  873. pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
  874. __func__);
  875. of_node_put(np);
  876. return fuse_corner;
  877. }
  878. static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref,
  879. struct device *cpu_dev)
  880. {
  881. u64 rate = 0;
  882. struct device_node *ref_np;
  883. struct device_node *desc_np;
  884. struct device_node *child_np = NULL;
  885. struct device_node *child_req_np = NULL;
  886. desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
  887. if (!desc_np)
  888. return 0;
  889. ref_np = dev_pm_opp_get_of_node(ref);
  890. if (!ref_np)
  891. goto out_ref;
  892. do {
  893. of_node_put(child_req_np);
  894. child_np = of_get_next_available_child(desc_np, child_np);
  895. child_req_np = of_parse_phandle(child_np, "required-opps", 0);
  896. } while (child_np && child_req_np != ref_np);
  897. if (child_np && child_req_np == ref_np)
  898. of_property_read_u64(child_np, "opp-hz", &rate);
  899. of_node_put(child_req_np);
  900. of_node_put(child_np);
  901. of_node_put(ref_np);
  902. out_ref:
  903. of_node_put(desc_np);
  904. return (unsigned long) rate;
  905. }
  906. static int cpr_corner_init(struct cpr_drv *drv)
  907. {
  908. const struct cpr_desc *desc = drv->desc;
  909. const struct cpr_fuse *fuses = drv->cpr_fuses;
  910. int i, level, scaling = 0;
  911. unsigned int fnum, fc;
  912. const char *quot_offset;
  913. struct fuse_corner *fuse, *prev_fuse;
  914. struct corner *corner, *end;
  915. struct corner_data *cdata;
  916. const struct fuse_corner_data *fdata;
  917. bool apply_scaling;
  918. unsigned long freq_diff, freq_diff_mhz;
  919. unsigned long freq;
  920. int step_volt = regulator_get_linear_step(drv->vdd_apc);
  921. struct dev_pm_opp *opp;
  922. if (!step_volt)
  923. return -EINVAL;
  924. corner = drv->corners;
  925. end = &corner[drv->num_corners - 1];
  926. cdata = devm_kcalloc(drv->dev, drv->num_corners,
  927. sizeof(struct corner_data),
  928. GFP_KERNEL);
  929. if (!cdata)
  930. return -ENOMEM;
  931. /*
  932. * Store maximum frequency for each fuse corner based on the frequency
  933. * plan
  934. */
  935. for (level = 1; level <= drv->num_corners; level++) {
  936. opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level);
  937. if (IS_ERR(opp))
  938. return -EINVAL;
  939. fc = cpr_get_fuse_corner(opp);
  940. if (!fc) {
  941. dev_pm_opp_put(opp);
  942. return -EINVAL;
  943. }
  944. fnum = fc - 1;
  945. freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev);
  946. if (!freq) {
  947. dev_pm_opp_put(opp);
  948. return -EINVAL;
  949. }
  950. cdata[level - 1].fuse_corner = fnum;
  951. cdata[level - 1].freq = freq;
  952. fuse = &drv->fuse_corners[fnum];
  953. dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
  954. freq, dev_pm_opp_get_level(opp) - 1, fnum);
  955. if (freq > fuse->max_freq)
  956. fuse->max_freq = freq;
  957. dev_pm_opp_put(opp);
  958. }
  959. /*
  960. * Get the quotient adjustment scaling factor, according to:
  961. *
  962. * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
  963. * / (freq(corner_N) - freq(corner_N-1)), max_factor)
  964. *
  965. * QUOT(corner_N): quotient read from fuse for fuse corner N
  966. * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1)
  967. * freq(corner_N): max frequency in MHz supported by fuse corner N
  968. * freq(corner_N-1): max frequency in MHz supported by fuse corner
  969. * (N - 1)
  970. *
  971. * Then walk through the corners mapped to each fuse corner
  972. * and calculate the quotient adjustment for each one using the
  973. * following formula:
  974. *
  975. * quot_adjust = (freq_max - freq_corner) * scaling / 1000
  976. *
  977. * freq_max: max frequency in MHz supported by the fuse corner
  978. * freq_corner: frequency in MHz corresponding to the corner
  979. * scaling: calculated from above equation
  980. *
  981. *
  982. * + +
  983. * | v |
  984. * q | f c o | f c
  985. * u | c l | c
  986. * o | f t | f
  987. * t | c a | c
  988. * | c f g | c f
  989. * | e |
  990. * +--------------- +----------------
  991. * 0 1 2 3 4 5 6 0 1 2 3 4 5 6
  992. * corner corner
  993. *
  994. * c = corner
  995. * f = fuse corner
  996. *
  997. */
  998. for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
  999. fnum = cdata[i].fuse_corner;
  1000. fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
  1001. quot_offset = fuses[fnum].quotient_offset;
  1002. fuse = &drv->fuse_corners[fnum];
  1003. if (fnum)
  1004. prev_fuse = &drv->fuse_corners[fnum - 1];
  1005. else
  1006. prev_fuse = NULL;
  1007. corner->fuse_corner = fuse;
  1008. corner->freq = cdata[i].freq;
  1009. corner->uV = fuse->uV;
  1010. if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
  1011. scaling = cpr_calculate_scaling(quot_offset, drv,
  1012. fdata, corner);
  1013. if (scaling < 0)
  1014. return scaling;
  1015. apply_scaling = true;
  1016. } else if (corner->freq == fuse->max_freq) {
  1017. /* This is a fuse corner; don't scale anything */
  1018. apply_scaling = false;
  1019. }
  1020. if (apply_scaling) {
  1021. freq_diff = fuse->max_freq - corner->freq;
  1022. freq_diff_mhz = freq_diff / 1000000;
  1023. corner->quot_adjust = scaling * freq_diff_mhz / 1000;
  1024. corner->uV = cpr_interpolate(corner, step_volt, fdata);
  1025. }
  1026. corner->max_uV = fuse->max_uV;
  1027. corner->min_uV = fuse->min_uV;
  1028. corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
  1029. corner->last_uV = corner->uV;
  1030. /* Reduce the ceiling voltage if needed */
  1031. if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
  1032. corner->max_uV = corner->uV;
  1033. else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
  1034. corner->max_uV = max(corner->min_uV, fuse->uV);
  1035. dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
  1036. corner->min_uV, corner->uV, corner->max_uV,
  1037. fuse->quot - corner->quot_adjust);
  1038. }
  1039. return 0;
  1040. }
  1041. static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
  1042. {
  1043. const struct cpr_desc *desc = drv->desc;
  1044. struct cpr_fuse *fuses;
  1045. int i;
  1046. fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners,
  1047. sizeof(struct cpr_fuse),
  1048. GFP_KERNEL);
  1049. if (!fuses)
  1050. return ERR_PTR(-ENOMEM);
  1051. for (i = 0; i < desc->num_fuse_corners; i++) {
  1052. char tbuf[32];
  1053. snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
  1054. fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
  1055. if (!fuses[i].ring_osc)
  1056. return ERR_PTR(-ENOMEM);
  1057. snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
  1058. fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
  1059. GFP_KERNEL);
  1060. if (!fuses[i].init_voltage)
  1061. return ERR_PTR(-ENOMEM);
  1062. snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
  1063. fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
  1064. if (!fuses[i].quotient)
  1065. return ERR_PTR(-ENOMEM);
  1066. snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
  1067. fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
  1068. GFP_KERNEL);
  1069. if (!fuses[i].quotient_offset)
  1070. return ERR_PTR(-ENOMEM);
  1071. }
  1072. return fuses;
  1073. }
  1074. static void cpr_set_loop_allowed(struct cpr_drv *drv)
  1075. {
  1076. drv->loop_disabled = false;
  1077. }
  1078. static int cpr_init_parameters(struct cpr_drv *drv)
  1079. {
  1080. const struct cpr_desc *desc = drv->desc;
  1081. struct clk *clk;
  1082. clk = clk_get(drv->dev, "ref");
  1083. if (IS_ERR(clk))
  1084. return PTR_ERR(clk);
  1085. drv->ref_clk_khz = clk_get_rate(clk) / 1000;
  1086. clk_put(clk);
  1087. if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK ||
  1088. desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK ||
  1089. desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK ||
  1090. desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK ||
  1091. desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK ||
  1092. desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK)
  1093. return -EINVAL;
  1094. dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
  1095. desc->up_threshold, desc->down_threshold);
  1096. return 0;
  1097. }
  1098. static int cpr_find_initial_corner(struct cpr_drv *drv)
  1099. {
  1100. unsigned long rate;
  1101. const struct corner *end;
  1102. struct corner *iter;
  1103. unsigned int i = 0;
  1104. if (!drv->cpu_clk) {
  1105. dev_err(drv->dev, "cannot get rate from NULL clk\n");
  1106. return -EINVAL;
  1107. }
  1108. end = &drv->corners[drv->num_corners - 1];
  1109. rate = clk_get_rate(drv->cpu_clk);
  1110. /*
  1111. * Some bootloaders set a CPU clock frequency that is not defined
  1112. * in the OPP table. When running at an unlisted frequency,
  1113. * cpufreq_online() will change to the OPP which has the lowest
  1114. * frequency, at or above the unlisted frequency.
  1115. * Since cpufreq_online() always "rounds up" in the case of an
  1116. * unlisted frequency, this function always "rounds down" in case
  1117. * of an unlisted frequency. That way, when cpufreq_online()
  1118. * triggers the first ever call to cpr_set_performance_state(),
  1119. * it will correctly determine the direction as UP.
  1120. */
  1121. for (iter = drv->corners; iter <= end; iter++) {
  1122. if (iter->freq > rate)
  1123. break;
  1124. i++;
  1125. if (iter->freq == rate) {
  1126. drv->corner = iter;
  1127. break;
  1128. }
  1129. if (iter->freq < rate)
  1130. drv->corner = iter;
  1131. }
  1132. if (!drv->corner) {
  1133. dev_err(drv->dev, "boot up corner not found\n");
  1134. return -EINVAL;
  1135. }
  1136. dev_dbg(drv->dev, "boot up perf state: %u\n", i);
  1137. return 0;
  1138. }
  1139. static const struct cpr_desc qcs404_cpr_desc = {
  1140. .num_fuse_corners = 3,
  1141. .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
  1142. .step_quot = (int []){ 25, 25, 25, },
  1143. .timer_delay_us = 5000,
  1144. .timer_cons_up = 0,
  1145. .timer_cons_down = 2,
  1146. .up_threshold = 1,
  1147. .down_threshold = 3,
  1148. .idle_clocks = 15,
  1149. .gcnt_us = 1,
  1150. .vdd_apc_step_up_limit = 1,
  1151. .vdd_apc_step_down_limit = 1,
  1152. .cpr_fuses = {
  1153. .init_voltage_step = 8000,
  1154. .init_voltage_width = 6,
  1155. .fuse_corner_data = (struct fuse_corner_data[]){
  1156. /* fuse corner 0 */
  1157. {
  1158. .ref_uV = 1224000,
  1159. .max_uV = 1224000,
  1160. .min_uV = 1048000,
  1161. .max_volt_scale = 0,
  1162. .max_quot_scale = 0,
  1163. .quot_offset = 0,
  1164. .quot_scale = 1,
  1165. .quot_adjust = 0,
  1166. .quot_offset_scale = 5,
  1167. .quot_offset_adjust = 0,
  1168. },
  1169. /* fuse corner 1 */
  1170. {
  1171. .ref_uV = 1288000,
  1172. .max_uV = 1288000,
  1173. .min_uV = 1048000,
  1174. .max_volt_scale = 2000,
  1175. .max_quot_scale = 1400,
  1176. .quot_offset = 0,
  1177. .quot_scale = 1,
  1178. .quot_adjust = -20,
  1179. .quot_offset_scale = 5,
  1180. .quot_offset_adjust = 0,
  1181. },
  1182. /* fuse corner 2 */
  1183. {
  1184. .ref_uV = 1352000,
  1185. .max_uV = 1384000,
  1186. .min_uV = 1088000,
  1187. .max_volt_scale = 2000,
  1188. .max_quot_scale = 1400,
  1189. .quot_offset = 0,
  1190. .quot_scale = 1,
  1191. .quot_adjust = 0,
  1192. .quot_offset_scale = 5,
  1193. .quot_offset_adjust = 0,
  1194. },
  1195. },
  1196. },
  1197. };
  1198. static const struct acc_desc qcs404_acc_desc = {
  1199. .settings = (struct reg_sequence[]){
  1200. { 0xb120, 0x1041040 },
  1201. { 0xb124, 0x41 },
  1202. { 0xb120, 0x0 },
  1203. { 0xb124, 0x0 },
  1204. { 0xb120, 0x0 },
  1205. { 0xb124, 0x0 },
  1206. },
  1207. .config = (struct reg_sequence[]){
  1208. { 0xb138, 0xff },
  1209. { 0xb130, 0x5555 },
  1210. },
  1211. .num_regs_per_fuse = 2,
  1212. };
  1213. static const struct cpr_acc_desc qcs404_cpr_acc_desc = {
  1214. .cpr_desc = &qcs404_cpr_desc,
  1215. .acc_desc = &qcs404_acc_desc,
  1216. };
  1217. static unsigned int cpr_get_performance_state(struct generic_pm_domain *genpd,
  1218. struct dev_pm_opp *opp)
  1219. {
  1220. return dev_pm_opp_get_level(opp);
  1221. }
  1222. static int cpr_power_off(struct generic_pm_domain *domain)
  1223. {
  1224. struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
  1225. return cpr_disable(drv);
  1226. }
  1227. static int cpr_power_on(struct generic_pm_domain *domain)
  1228. {
  1229. struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
  1230. return cpr_enable(drv);
  1231. }
  1232. static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
  1233. struct device *dev)
  1234. {
  1235. struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
  1236. const struct acc_desc *acc_desc = drv->acc_desc;
  1237. int ret = 0;
  1238. mutex_lock(&drv->lock);
  1239. dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
  1240. /*
  1241. * This driver only supports scaling voltage for a CPU cluster
  1242. * where all CPUs in the cluster share a single regulator.
  1243. * Therefore, save the struct device pointer only for the first
  1244. * CPU device that gets attached. There is no need to do any
  1245. * additional initialization when further CPUs get attached.
  1246. */
  1247. if (drv->attached_cpu_dev)
  1248. goto unlock;
  1249. /*
  1250. * cpr_scale_voltage() requires the direction (if we are changing
  1251. * to a higher or lower OPP). The first time
  1252. * cpr_set_performance_state() is called, there is no previous
  1253. * performance state defined. Therefore, we call
  1254. * cpr_find_initial_corner() that gets the CPU clock frequency
  1255. * set by the bootloader, so that we can determine the direction
  1256. * the first time cpr_set_performance_state() is called.
  1257. */
  1258. drv->cpu_clk = devm_clk_get(dev, NULL);
  1259. if (IS_ERR(drv->cpu_clk)) {
  1260. ret = PTR_ERR(drv->cpu_clk);
  1261. if (ret != -EPROBE_DEFER)
  1262. dev_err(drv->dev, "could not get cpu clk: %d\n", ret);
  1263. goto unlock;
  1264. }
  1265. drv->attached_cpu_dev = dev;
  1266. dev_dbg(drv->dev, "using cpu clk from: %s\n",
  1267. dev_name(drv->attached_cpu_dev));
  1268. /*
  1269. * Everything related to (virtual) corners has to be initialized
  1270. * here, when attaching to the power domain, since we need to know
  1271. * the maximum frequency for each fuse corner, and this is only
  1272. * available after the cpufreq driver has attached to us.
  1273. * The reason for this is that we need to know the highest
  1274. * frequency associated with each fuse corner.
  1275. */
  1276. ret = dev_pm_opp_get_opp_count(&drv->pd.dev);
  1277. if (ret < 0) {
  1278. dev_err(drv->dev, "could not get OPP count\n");
  1279. goto unlock;
  1280. }
  1281. drv->num_corners = ret;
  1282. if (drv->num_corners < 2) {
  1283. dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
  1284. ret = -EINVAL;
  1285. goto unlock;
  1286. }
  1287. drv->corners = devm_kcalloc(drv->dev, drv->num_corners,
  1288. sizeof(*drv->corners),
  1289. GFP_KERNEL);
  1290. if (!drv->corners) {
  1291. ret = -ENOMEM;
  1292. goto unlock;
  1293. }
  1294. ret = cpr_corner_init(drv);
  1295. if (ret)
  1296. goto unlock;
  1297. cpr_set_loop_allowed(drv);
  1298. ret = cpr_init_parameters(drv);
  1299. if (ret)
  1300. goto unlock;
  1301. /* Configure CPR HW but keep it disabled */
  1302. ret = cpr_config(drv);
  1303. if (ret)
  1304. goto unlock;
  1305. ret = cpr_find_initial_corner(drv);
  1306. if (ret)
  1307. goto unlock;
  1308. if (acc_desc->config)
  1309. regmap_multi_reg_write(drv->tcsr, acc_desc->config,
  1310. acc_desc->num_regs_per_fuse);
  1311. /* Enable ACC if required */
  1312. if (acc_desc->enable_mask)
  1313. regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
  1314. acc_desc->enable_mask,
  1315. acc_desc->enable_mask);
  1316. dev_info(drv->dev, "driver initialized with %u OPPs\n",
  1317. drv->num_corners);
  1318. unlock:
  1319. mutex_unlock(&drv->lock);
  1320. return ret;
  1321. }
  1322. static int cpr_debug_info_show(struct seq_file *s, void *unused)
  1323. {
  1324. u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
  1325. u32 step_dn, step_up, error, error_lt0, busy;
  1326. struct cpr_drv *drv = s->private;
  1327. struct fuse_corner *fuse_corner;
  1328. struct corner *corner;
  1329. corner = drv->corner;
  1330. fuse_corner = corner->fuse_corner;
  1331. seq_printf(s, "corner, current_volt = %d uV\n",
  1332. corner->last_uV);
  1333. ro_sel = fuse_corner->ring_osc_idx;
  1334. gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
  1335. seq_printf(s, "rbcpr_gcnt_target (%u) = %#02X\n", ro_sel, gcnt);
  1336. ctl = cpr_read(drv, REG_RBCPR_CTL);
  1337. seq_printf(s, "rbcpr_ctl = %#02X\n", ctl);
  1338. irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
  1339. seq_printf(s, "rbcpr_irq_status = %#02X\n", irq_status);
  1340. reg = cpr_read(drv, REG_RBCPR_RESULT_0);
  1341. seq_printf(s, "rbcpr_result_0 = %#02X\n", reg);
  1342. step_dn = reg & 0x01;
  1343. step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
  1344. seq_printf(s, " [step_dn = %u", step_dn);
  1345. seq_printf(s, ", step_up = %u", step_up);
  1346. error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
  1347. & RBCPR_RESULT0_ERROR_STEPS_MASK;
  1348. seq_printf(s, ", error_steps = %u", error_steps);
  1349. error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
  1350. seq_printf(s, ", error = %u", error);
  1351. error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
  1352. seq_printf(s, ", error_lt_0 = %u", error_lt0);
  1353. busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
  1354. seq_printf(s, ", busy = %u]\n", busy);
  1355. return 0;
  1356. }
  1357. DEFINE_SHOW_ATTRIBUTE(cpr_debug_info);
  1358. static void cpr_debugfs_init(struct cpr_drv *drv)
  1359. {
  1360. drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
  1361. debugfs_create_file("debug_info", 0444, drv->debugfs,
  1362. drv, &cpr_debug_info_fops);
  1363. }
  1364. static int cpr_probe(struct platform_device *pdev)
  1365. {
  1366. struct resource *res;
  1367. struct device *dev = &pdev->dev;
  1368. struct cpr_drv *drv;
  1369. int irq, ret;
  1370. const struct cpr_acc_desc *data;
  1371. struct device_node *np;
  1372. u32 cpr_rev = FUSE_REVISION_UNKNOWN;
  1373. data = of_device_get_match_data(dev);
  1374. if (!data || !data->cpr_desc || !data->acc_desc)
  1375. return -EINVAL;
  1376. drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
  1377. if (!drv)
  1378. return -ENOMEM;
  1379. drv->dev = dev;
  1380. drv->desc = data->cpr_desc;
  1381. drv->acc_desc = data->acc_desc;
  1382. drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners,
  1383. sizeof(*drv->fuse_corners),
  1384. GFP_KERNEL);
  1385. if (!drv->fuse_corners)
  1386. return -ENOMEM;
  1387. np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
  1388. if (!np)
  1389. return -ENODEV;
  1390. drv->tcsr = syscon_node_to_regmap(np);
  1391. of_node_put(np);
  1392. if (IS_ERR(drv->tcsr))
  1393. return PTR_ERR(drv->tcsr);
  1394. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1395. drv->base = devm_ioremap_resource(dev, res);
  1396. if (IS_ERR(drv->base))
  1397. return PTR_ERR(drv->base);
  1398. irq = platform_get_irq(pdev, 0);
  1399. if (irq < 0)
  1400. return -EINVAL;
  1401. drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
  1402. if (IS_ERR(drv->vdd_apc))
  1403. return PTR_ERR(drv->vdd_apc);
  1404. /*
  1405. * Initialize fuse corners, since it simply depends
  1406. * on data in efuses.
  1407. * Everything related to (virtual) corners has to be
  1408. * initialized after attaching to the power domain,
  1409. * since it depends on the CPU's OPP table.
  1410. */
  1411. ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev);
  1412. if (ret)
  1413. return ret;
  1414. drv->cpr_fuses = cpr_get_fuses(drv);
  1415. if (IS_ERR(drv->cpr_fuses))
  1416. return PTR_ERR(drv->cpr_fuses);
  1417. ret = cpr_populate_ring_osc_idx(drv);
  1418. if (ret)
  1419. return ret;
  1420. ret = cpr_fuse_corner_init(drv);
  1421. if (ret)
  1422. return ret;
  1423. mutex_init(&drv->lock);
  1424. ret = devm_request_threaded_irq(dev, irq, NULL,
  1425. cpr_irq_handler,
  1426. IRQF_ONESHOT | IRQF_TRIGGER_RISING,
  1427. "cpr", drv);
  1428. if (ret)
  1429. return ret;
  1430. drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
  1431. GFP_KERNEL);
  1432. if (!drv->pd.name)
  1433. return -EINVAL;
  1434. drv->pd.power_off = cpr_power_off;
  1435. drv->pd.power_on = cpr_power_on;
  1436. drv->pd.set_performance_state = cpr_set_performance_state;
  1437. drv->pd.opp_to_performance_state = cpr_get_performance_state;
  1438. drv->pd.attach_dev = cpr_pd_attach_dev;
  1439. ret = pm_genpd_init(&drv->pd, NULL, true);
  1440. if (ret)
  1441. return ret;
  1442. ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
  1443. if (ret)
  1444. return ret;
  1445. platform_set_drvdata(pdev, drv);
  1446. cpr_debugfs_init(drv);
  1447. return 0;
  1448. }
  1449. static int cpr_remove(struct platform_device *pdev)
  1450. {
  1451. struct cpr_drv *drv = platform_get_drvdata(pdev);
  1452. if (cpr_is_allowed(drv)) {
  1453. cpr_ctl_disable(drv);
  1454. cpr_irq_set(drv, 0);
  1455. }
  1456. of_genpd_del_provider(pdev->dev.of_node);
  1457. pm_genpd_remove(&drv->pd);
  1458. debugfs_remove_recursive(drv->debugfs);
  1459. return 0;
  1460. }
  1461. static const struct of_device_id cpr_match_table[] = {
  1462. { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
  1463. { }
  1464. };
  1465. MODULE_DEVICE_TABLE(of, cpr_match_table);
  1466. static struct platform_driver cpr_driver = {
  1467. .probe = cpr_probe,
  1468. .remove = cpr_remove,
  1469. .driver = {
  1470. .name = "qcom-cpr",
  1471. .of_match_table = cpr_match_table,
  1472. },
  1473. };
  1474. module_platform_driver(cpr_driver);
  1475. MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
  1476. MODULE_LICENSE("GPL v2");