k210-sysctl.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2019 Christoph Hellwig.
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. */
  6. #include <linux/types.h>
  7. #include <linux/io.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/bitfield.h>
  13. #include <asm/soc.h>
  14. #define K210_SYSCTL_CLK0_FREQ 26000000UL
  15. /* Registers base address */
  16. #define K210_SYSCTL_SYSCTL_BASE_ADDR 0x50440000ULL
  17. /* Registers */
  18. #define K210_SYSCTL_PLL0 0x08
  19. #define K210_SYSCTL_PLL1 0x0c
  20. /* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
  21. #define PLL_RESET (1 << 20)
  22. #define PLL_PWR (1 << 21)
  23. #define PLL_INTFB (1 << 22)
  24. #define PLL_BYPASS (1 << 23)
  25. #define PLL_TEST (1 << 24)
  26. #define PLL_OUT_EN (1 << 25)
  27. #define PLL_TEST_EN (1 << 26)
  28. #define K210_SYSCTL_PLL_LOCK 0x18
  29. #define PLL0_LOCK1 (1 << 0)
  30. #define PLL0_LOCK2 (1 << 1)
  31. #define PLL0_SLIP_CLEAR (1 << 2)
  32. #define PLL0_TEST_CLK_OUT (1 << 3)
  33. #define PLL1_LOCK1 (1 << 8)
  34. #define PLL1_LOCK2 (1 << 9)
  35. #define PLL1_SLIP_CLEAR (1 << 10)
  36. #define PLL1_TEST_CLK_OUT (1 << 11)
  37. #define PLL2_LOCK1 (1 << 16)
  38. #define PLL2_LOCK2 (1 << 16)
  39. #define PLL2_SLIP_CLEAR (1 << 18)
  40. #define PLL2_TEST_CLK_OUT (1 << 19)
  41. #define K210_SYSCTL_CLKSEL0 0x20
  42. #define CLKSEL_ACLK (1 << 0)
  43. #define K210_SYSCTL_CLKEN_CENT 0x28
  44. #define CLKEN_CPU (1 << 0)
  45. #define CLKEN_SRAM0 (1 << 1)
  46. #define CLKEN_SRAM1 (1 << 2)
  47. #define CLKEN_APB0 (1 << 3)
  48. #define CLKEN_APB1 (1 << 4)
  49. #define CLKEN_APB2 (1 << 5)
  50. #define K210_SYSCTL_CLKEN_PERI 0x2c
  51. #define CLKEN_ROM (1 << 0)
  52. #define CLKEN_DMA (1 << 1)
  53. #define CLKEN_AI (1 << 2)
  54. #define CLKEN_DVP (1 << 3)
  55. #define CLKEN_FFT (1 << 4)
  56. #define CLKEN_GPIO (1 << 5)
  57. #define CLKEN_SPI0 (1 << 6)
  58. #define CLKEN_SPI1 (1 << 7)
  59. #define CLKEN_SPI2 (1 << 8)
  60. #define CLKEN_SPI3 (1 << 9)
  61. #define CLKEN_I2S0 (1 << 10)
  62. #define CLKEN_I2S1 (1 << 11)
  63. #define CLKEN_I2S2 (1 << 12)
  64. #define CLKEN_I2C0 (1 << 13)
  65. #define CLKEN_I2C1 (1 << 14)
  66. #define CLKEN_I2C2 (1 << 15)
  67. #define CLKEN_UART1 (1 << 16)
  68. #define CLKEN_UART2 (1 << 17)
  69. #define CLKEN_UART3 (1 << 18)
  70. #define CLKEN_AES (1 << 19)
  71. #define CLKEN_FPIO (1 << 20)
  72. #define CLKEN_TIMER0 (1 << 21)
  73. #define CLKEN_TIMER1 (1 << 22)
  74. #define CLKEN_TIMER2 (1 << 23)
  75. #define CLKEN_WDT0 (1 << 24)
  76. #define CLKEN_WDT1 (1 << 25)
  77. #define CLKEN_SHA (1 << 26)
  78. #define CLKEN_OTP (1 << 27)
  79. #define CLKEN_RTC (1 << 29)
  80. struct k210_sysctl {
  81. void __iomem *regs;
  82. struct clk_hw hw;
  83. };
  84. static void k210_set_bits(u32 val, void __iomem *reg)
  85. {
  86. writel(readl(reg) | val, reg);
  87. }
  88. static void k210_clear_bits(u32 val, void __iomem *reg)
  89. {
  90. writel(readl(reg) & ~val, reg);
  91. }
  92. static void k210_pll1_enable(void __iomem *regs)
  93. {
  94. u32 val;
  95. val = readl(regs + K210_SYSCTL_PLL1);
  96. val &= ~GENMASK(19, 0); /* clkr1 = 0 */
  97. val |= FIELD_PREP(GENMASK(9, 4), 0x3B); /* clkf1 = 59 */
  98. val |= FIELD_PREP(GENMASK(13, 10), 0x3); /* clkod1 = 3 */
  99. val |= FIELD_PREP(GENMASK(19, 14), 0x3B); /* bwadj1 = 59 */
  100. writel(val, regs + K210_SYSCTL_PLL1);
  101. k210_clear_bits(PLL_BYPASS, regs + K210_SYSCTL_PLL1);
  102. k210_set_bits(PLL_PWR, regs + K210_SYSCTL_PLL1);
  103. /*
  104. * Reset the pll. The magic NOPs come from the Kendryte reference SDK.
  105. */
  106. k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
  107. k210_set_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
  108. nop();
  109. nop();
  110. k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
  111. for (;;) {
  112. val = readl(regs + K210_SYSCTL_PLL_LOCK);
  113. if (val & PLL1_LOCK2)
  114. break;
  115. writel(val | PLL1_SLIP_CLEAR, regs + K210_SYSCTL_PLL_LOCK);
  116. }
  117. k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL1);
  118. }
  119. static unsigned long k210_sysctl_clk_recalc_rate(struct clk_hw *hw,
  120. unsigned long parent_rate)
  121. {
  122. struct k210_sysctl *s = container_of(hw, struct k210_sysctl, hw);
  123. u32 clksel0, pll0;
  124. u64 pll0_freq, clkr0, clkf0, clkod0;
  125. /*
  126. * If the clock selector is not set, use the base frequency.
  127. * Otherwise, use PLL0 frequency with a frequency divisor.
  128. */
  129. clksel0 = readl(s->regs + K210_SYSCTL_CLKSEL0);
  130. if (!(clksel0 & CLKSEL_ACLK))
  131. return K210_SYSCTL_CLK0_FREQ;
  132. /*
  133. * Get PLL0 frequency:
  134. * freq = base frequency * clkf0 / (clkr0 * clkod0)
  135. */
  136. pll0 = readl(s->regs + K210_SYSCTL_PLL0);
  137. clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0);
  138. clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0);
  139. clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0);
  140. pll0_freq = clkf0 * K210_SYSCTL_CLK0_FREQ / (clkr0 * clkod0);
  141. /* Get the frequency divisor from the clock selector */
  142. return pll0_freq / (2ULL << FIELD_GET(0x00000006, clksel0));
  143. }
  144. static const struct clk_ops k210_sysctl_clk_ops = {
  145. .recalc_rate = k210_sysctl_clk_recalc_rate,
  146. };
  147. static const struct clk_init_data k210_clk_init_data = {
  148. .name = "k210-sysctl-pll1",
  149. .ops = &k210_sysctl_clk_ops,
  150. };
  151. static int k210_sysctl_probe(struct platform_device *pdev)
  152. {
  153. struct k210_sysctl *s;
  154. int error;
  155. pr_info("Kendryte K210 SoC sysctl\n");
  156. s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
  157. if (!s)
  158. return -ENOMEM;
  159. s->regs = devm_ioremap_resource(&pdev->dev,
  160. platform_get_resource(pdev, IORESOURCE_MEM, 0));
  161. if (IS_ERR(s->regs))
  162. return PTR_ERR(s->regs);
  163. s->hw.init = &k210_clk_init_data;
  164. error = devm_clk_hw_register(&pdev->dev, &s->hw);
  165. if (error) {
  166. dev_err(&pdev->dev, "failed to register clk");
  167. return error;
  168. }
  169. error = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
  170. &s->hw);
  171. if (error) {
  172. dev_err(&pdev->dev, "adding clk provider failed\n");
  173. return error;
  174. }
  175. return 0;
  176. }
  177. static const struct of_device_id k210_sysctl_of_match[] = {
  178. { .compatible = "kendryte,k210-sysctl", },
  179. {}
  180. };
  181. static struct platform_driver k210_sysctl_driver = {
  182. .driver = {
  183. .name = "k210-sysctl",
  184. .of_match_table = k210_sysctl_of_match,
  185. },
  186. .probe = k210_sysctl_probe,
  187. };
  188. static int __init k210_sysctl_init(void)
  189. {
  190. return platform_driver_register(&k210_sysctl_driver);
  191. }
  192. core_initcall(k210_sysctl_init);
  193. /*
  194. * This needs to be called very early during initialization, given that
  195. * PLL1 needs to be enabled to be able to use all SRAM.
  196. */
  197. static void __init k210_soc_early_init(const void *fdt)
  198. {
  199. void __iomem *regs;
  200. regs = ioremap(K210_SYSCTL_SYSCTL_BASE_ADDR, 0x1000);
  201. if (!regs)
  202. panic("K210 sysctl ioremap");
  203. /* Enable PLL1 to make the KPU SRAM useable */
  204. k210_pll1_enable(regs);
  205. k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL0);
  206. k210_set_bits(CLKEN_CPU | CLKEN_SRAM0 | CLKEN_SRAM1,
  207. regs + K210_SYSCTL_CLKEN_CENT);
  208. k210_set_bits(CLKEN_ROM | CLKEN_TIMER0 | CLKEN_RTC,
  209. regs + K210_SYSCTL_CLKEN_PERI);
  210. k210_set_bits(CLKSEL_ACLK, regs + K210_SYSCTL_CLKSEL0);
  211. iounmap(regs);
  212. }
  213. SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init);
  214. #ifdef CONFIG_SOC_KENDRYTE_K210_DTB_BUILTIN
  215. /*
  216. * Generic entry for the default k210.dtb embedded DTB for boards with:
  217. * - Vendor ID: 0x4B5
  218. * - Arch ID: 0xE59889E6A5A04149 (= "Canaan AI" in UTF-8 encoded Chinese)
  219. * - Impl ID: 0x4D41495832303030 (= "MAIX2000")
  220. * These values are reported by the SiPEED MAXDUINO, SiPEED MAIX GO and
  221. * SiPEED Dan dock boards.
  222. */
  223. SOC_BUILTIN_DTB_DECLARE(k210, 0x4B5, 0xE59889E6A5A04149, 0x4D41495832303030);
  224. #endif