bcm2835-power.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Power domain driver for Broadcom BCM2835
  4. *
  5. * Copyright (C) 2018 Broadcom
  6. */
  7. #include <dt-bindings/soc/bcm2835-pm.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/io.h>
  11. #include <linux/mfd/bcm2835-pm.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pm_domain.h>
  15. #include <linux/reset-controller.h>
  16. #include <linux/types.h>
  17. #define PM_GNRIC 0x00
  18. #define PM_AUDIO 0x04
  19. #define PM_STATUS 0x18
  20. #define PM_RSTC 0x1c
  21. #define PM_RSTS 0x20
  22. #define PM_WDOG 0x24
  23. #define PM_PADS0 0x28
  24. #define PM_PADS2 0x2c
  25. #define PM_PADS3 0x30
  26. #define PM_PADS4 0x34
  27. #define PM_PADS5 0x38
  28. #define PM_PADS6 0x3c
  29. #define PM_CAM0 0x44
  30. #define PM_CAM0_LDOHPEN BIT(2)
  31. #define PM_CAM0_LDOLPEN BIT(1)
  32. #define PM_CAM0_CTRLEN BIT(0)
  33. #define PM_CAM1 0x48
  34. #define PM_CAM1_LDOHPEN BIT(2)
  35. #define PM_CAM1_LDOLPEN BIT(1)
  36. #define PM_CAM1_CTRLEN BIT(0)
  37. #define PM_CCP2TX 0x4c
  38. #define PM_CCP2TX_LDOEN BIT(1)
  39. #define PM_CCP2TX_CTRLEN BIT(0)
  40. #define PM_DSI0 0x50
  41. #define PM_DSI0_LDOHPEN BIT(2)
  42. #define PM_DSI0_LDOLPEN BIT(1)
  43. #define PM_DSI0_CTRLEN BIT(0)
  44. #define PM_DSI1 0x54
  45. #define PM_DSI1_LDOHPEN BIT(2)
  46. #define PM_DSI1_LDOLPEN BIT(1)
  47. #define PM_DSI1_CTRLEN BIT(0)
  48. #define PM_HDMI 0x58
  49. #define PM_HDMI_RSTDR BIT(19)
  50. #define PM_HDMI_LDOPD BIT(1)
  51. #define PM_HDMI_CTRLEN BIT(0)
  52. #define PM_USB 0x5c
  53. /* The power gates must be enabled with this bit before enabling the LDO in the
  54. * USB block.
  55. */
  56. #define PM_USB_CTRLEN BIT(0)
  57. #define PM_PXLDO 0x60
  58. #define PM_PXBG 0x64
  59. #define PM_DFT 0x68
  60. #define PM_SMPS 0x6c
  61. #define PM_XOSC 0x70
  62. #define PM_SPAREW 0x74
  63. #define PM_SPARER 0x78
  64. #define PM_AVS_RSTDR 0x7c
  65. #define PM_AVS_STAT 0x80
  66. #define PM_AVS_EVENT 0x84
  67. #define PM_AVS_INTEN 0x88
  68. #define PM_DUMMY 0xfc
  69. #define PM_IMAGE 0x108
  70. #define PM_GRAFX 0x10c
  71. #define PM_PROC 0x110
  72. #define PM_ENAB BIT(12)
  73. #define PM_ISPRSTN BIT(8)
  74. #define PM_H264RSTN BIT(7)
  75. #define PM_PERIRSTN BIT(6)
  76. #define PM_V3DRSTN BIT(6)
  77. #define PM_ISFUNC BIT(5)
  78. #define PM_MRDONE BIT(4)
  79. #define PM_MEMREP BIT(3)
  80. #define PM_ISPOW BIT(2)
  81. #define PM_POWOK BIT(1)
  82. #define PM_POWUP BIT(0)
  83. #define PM_INRUSH_SHIFT 13
  84. #define PM_INRUSH_3_5_MA 0
  85. #define PM_INRUSH_5_MA 1
  86. #define PM_INRUSH_10_MA 2
  87. #define PM_INRUSH_20_MA 3
  88. #define PM_INRUSH_MASK (3 << PM_INRUSH_SHIFT)
  89. #define PM_PASSWORD 0x5a000000
  90. #define PM_WDOG_TIME_SET 0x000fffff
  91. #define PM_RSTC_WRCFG_CLR 0xffffffcf
  92. #define PM_RSTS_HADWRH_SET 0x00000040
  93. #define PM_RSTC_WRCFG_SET 0x00000030
  94. #define PM_RSTC_WRCFG_FULL_RESET 0x00000020
  95. #define PM_RSTC_RESET 0x00000102
  96. #define PM_READ(reg) readl(power->base + (reg))
  97. #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
  98. #define ASB_BRDG_VERSION 0x00
  99. #define ASB_CPR_CTRL 0x04
  100. #define ASB_V3D_S_CTRL 0x08
  101. #define ASB_V3D_M_CTRL 0x0c
  102. #define ASB_ISP_S_CTRL 0x10
  103. #define ASB_ISP_M_CTRL 0x14
  104. #define ASB_H264_S_CTRL 0x18
  105. #define ASB_H264_M_CTRL 0x1c
  106. #define ASB_REQ_STOP BIT(0)
  107. #define ASB_ACK BIT(1)
  108. #define ASB_EMPTY BIT(2)
  109. #define ASB_FULL BIT(3)
  110. #define ASB_AXI_BRDG_ID 0x20
  111. #define ASB_READ(reg) readl(power->asb + (reg))
  112. #define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg))
  113. struct bcm2835_power_domain {
  114. struct generic_pm_domain base;
  115. struct bcm2835_power *power;
  116. u32 domain;
  117. struct clk *clk;
  118. };
  119. struct bcm2835_power {
  120. struct device *dev;
  121. /* PM registers. */
  122. void __iomem *base;
  123. /* AXI Async bridge registers. */
  124. void __iomem *asb;
  125. struct genpd_onecell_data pd_xlate;
  126. struct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT];
  127. struct reset_controller_dev reset;
  128. };
  129. static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg)
  130. {
  131. u64 start;
  132. if (!reg)
  133. return 0;
  134. start = ktime_get_ns();
  135. /* Enable the module's async AXI bridges. */
  136. ASB_WRITE(reg, ASB_READ(reg) & ~ASB_REQ_STOP);
  137. while (ASB_READ(reg) & ASB_ACK) {
  138. cpu_relax();
  139. if (ktime_get_ns() - start >= 1000)
  140. return -ETIMEDOUT;
  141. }
  142. return 0;
  143. }
  144. static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg)
  145. {
  146. u64 start;
  147. if (!reg)
  148. return 0;
  149. start = ktime_get_ns();
  150. /* Enable the module's async AXI bridges. */
  151. ASB_WRITE(reg, ASB_READ(reg) | ASB_REQ_STOP);
  152. while (!(ASB_READ(reg) & ASB_ACK)) {
  153. cpu_relax();
  154. if (ktime_get_ns() - start >= 1000)
  155. return -ETIMEDOUT;
  156. }
  157. return 0;
  158. }
  159. static int bcm2835_power_power_off(struct bcm2835_power_domain *pd, u32 pm_reg)
  160. {
  161. struct bcm2835_power *power = pd->power;
  162. /* Enable functional isolation */
  163. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC);
  164. /* Enable electrical isolation */
  165. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
  166. /* Open the power switches. */
  167. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_POWUP);
  168. return 0;
  169. }
  170. static int bcm2835_power_power_on(struct bcm2835_power_domain *pd, u32 pm_reg)
  171. {
  172. struct bcm2835_power *power = pd->power;
  173. struct device *dev = power->dev;
  174. u64 start;
  175. int ret;
  176. int inrush;
  177. bool powok;
  178. /* If it was already powered on by the fw, leave it that way. */
  179. if (PM_READ(pm_reg) & PM_POWUP)
  180. return 0;
  181. /* Enable power. Allowing too much current at once may result
  182. * in POWOK never getting set, so start low and ramp it up as
  183. * necessary to succeed.
  184. */
  185. powok = false;
  186. for (inrush = PM_INRUSH_3_5_MA; inrush <= PM_INRUSH_20_MA; inrush++) {
  187. PM_WRITE(pm_reg,
  188. (PM_READ(pm_reg) & ~PM_INRUSH_MASK) |
  189. (inrush << PM_INRUSH_SHIFT) |
  190. PM_POWUP);
  191. start = ktime_get_ns();
  192. while (!(powok = !!(PM_READ(pm_reg) & PM_POWOK))) {
  193. cpu_relax();
  194. if (ktime_get_ns() - start >= 3000)
  195. break;
  196. }
  197. }
  198. if (!powok) {
  199. dev_err(dev, "Timeout waiting for %s power OK\n",
  200. pd->base.name);
  201. ret = -ETIMEDOUT;
  202. goto err_disable_powup;
  203. }
  204. /* Disable electrical isolation */
  205. PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISPOW);
  206. /* Repair memory */
  207. PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_MEMREP);
  208. start = ktime_get_ns();
  209. while (!(PM_READ(pm_reg) & PM_MRDONE)) {
  210. cpu_relax();
  211. if (ktime_get_ns() - start >= 1000) {
  212. dev_err(dev, "Timeout waiting for %s memory repair\n",
  213. pd->base.name);
  214. ret = -ETIMEDOUT;
  215. goto err_disable_ispow;
  216. }
  217. }
  218. /* Disable functional isolation */
  219. PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISFUNC);
  220. return 0;
  221. err_disable_ispow:
  222. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
  223. err_disable_powup:
  224. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~(PM_POWUP | PM_INRUSH_MASK));
  225. return ret;
  226. }
  227. static int bcm2835_asb_power_on(struct bcm2835_power_domain *pd,
  228. u32 pm_reg,
  229. u32 asb_m_reg,
  230. u32 asb_s_reg,
  231. u32 reset_flags)
  232. {
  233. struct bcm2835_power *power = pd->power;
  234. int ret;
  235. ret = clk_prepare_enable(pd->clk);
  236. if (ret) {
  237. dev_err(power->dev, "Failed to enable clock for %s\n",
  238. pd->base.name);
  239. return ret;
  240. }
  241. /* Wait 32 clocks for reset to propagate, 1 us will be enough */
  242. udelay(1);
  243. clk_disable_unprepare(pd->clk);
  244. /* Deassert the resets. */
  245. PM_WRITE(pm_reg, PM_READ(pm_reg) | reset_flags);
  246. ret = clk_prepare_enable(pd->clk);
  247. if (ret) {
  248. dev_err(power->dev, "Failed to enable clock for %s\n",
  249. pd->base.name);
  250. goto err_enable_resets;
  251. }
  252. ret = bcm2835_asb_enable(power, asb_m_reg);
  253. if (ret) {
  254. dev_err(power->dev, "Failed to enable ASB master for %s\n",
  255. pd->base.name);
  256. goto err_disable_clk;
  257. }
  258. ret = bcm2835_asb_enable(power, asb_s_reg);
  259. if (ret) {
  260. dev_err(power->dev, "Failed to enable ASB slave for %s\n",
  261. pd->base.name);
  262. goto err_disable_asb_master;
  263. }
  264. return 0;
  265. err_disable_asb_master:
  266. bcm2835_asb_disable(power, asb_m_reg);
  267. err_disable_clk:
  268. clk_disable_unprepare(pd->clk);
  269. err_enable_resets:
  270. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
  271. return ret;
  272. }
  273. static int bcm2835_asb_power_off(struct bcm2835_power_domain *pd,
  274. u32 pm_reg,
  275. u32 asb_m_reg,
  276. u32 asb_s_reg,
  277. u32 reset_flags)
  278. {
  279. struct bcm2835_power *power = pd->power;
  280. int ret;
  281. ret = bcm2835_asb_disable(power, asb_s_reg);
  282. if (ret) {
  283. dev_warn(power->dev, "Failed to disable ASB slave for %s\n",
  284. pd->base.name);
  285. return ret;
  286. }
  287. ret = bcm2835_asb_disable(power, asb_m_reg);
  288. if (ret) {
  289. dev_warn(power->dev, "Failed to disable ASB master for %s\n",
  290. pd->base.name);
  291. bcm2835_asb_enable(power, asb_s_reg);
  292. return ret;
  293. }
  294. clk_disable_unprepare(pd->clk);
  295. /* Assert the resets. */
  296. PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
  297. return 0;
  298. }
  299. static int bcm2835_power_pd_power_on(struct generic_pm_domain *domain)
  300. {
  301. struct bcm2835_power_domain *pd =
  302. container_of(domain, struct bcm2835_power_domain, base);
  303. struct bcm2835_power *power = pd->power;
  304. switch (pd->domain) {
  305. case BCM2835_POWER_DOMAIN_GRAFX:
  306. return bcm2835_power_power_on(pd, PM_GRAFX);
  307. case BCM2835_POWER_DOMAIN_GRAFX_V3D:
  308. return bcm2835_asb_power_on(pd, PM_GRAFX,
  309. ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
  310. PM_V3DRSTN);
  311. case BCM2835_POWER_DOMAIN_IMAGE:
  312. return bcm2835_power_power_on(pd, PM_IMAGE);
  313. case BCM2835_POWER_DOMAIN_IMAGE_PERI:
  314. return bcm2835_asb_power_on(pd, PM_IMAGE,
  315. 0, 0,
  316. PM_PERIRSTN);
  317. case BCM2835_POWER_DOMAIN_IMAGE_ISP:
  318. return bcm2835_asb_power_on(pd, PM_IMAGE,
  319. ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
  320. PM_ISPRSTN);
  321. case BCM2835_POWER_DOMAIN_IMAGE_H264:
  322. return bcm2835_asb_power_on(pd, PM_IMAGE,
  323. ASB_H264_M_CTRL, ASB_H264_S_CTRL,
  324. PM_H264RSTN);
  325. case BCM2835_POWER_DOMAIN_USB:
  326. PM_WRITE(PM_USB, PM_USB_CTRLEN);
  327. return 0;
  328. case BCM2835_POWER_DOMAIN_DSI0:
  329. PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
  330. PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN | PM_DSI0_LDOHPEN);
  331. return 0;
  332. case BCM2835_POWER_DOMAIN_DSI1:
  333. PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
  334. PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN | PM_DSI1_LDOHPEN);
  335. return 0;
  336. case BCM2835_POWER_DOMAIN_CCP2TX:
  337. PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
  338. PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN | PM_CCP2TX_LDOEN);
  339. return 0;
  340. case BCM2835_POWER_DOMAIN_HDMI:
  341. PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_RSTDR);
  342. PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_CTRLEN);
  343. PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_LDOPD);
  344. usleep_range(100, 200);
  345. PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_RSTDR);
  346. return 0;
  347. default:
  348. dev_err(power->dev, "Invalid domain %d\n", pd->domain);
  349. return -EINVAL;
  350. }
  351. }
  352. static int bcm2835_power_pd_power_off(struct generic_pm_domain *domain)
  353. {
  354. struct bcm2835_power_domain *pd =
  355. container_of(domain, struct bcm2835_power_domain, base);
  356. struct bcm2835_power *power = pd->power;
  357. switch (pd->domain) {
  358. case BCM2835_POWER_DOMAIN_GRAFX:
  359. return bcm2835_power_power_off(pd, PM_GRAFX);
  360. case BCM2835_POWER_DOMAIN_GRAFX_V3D:
  361. return bcm2835_asb_power_off(pd, PM_GRAFX,
  362. ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
  363. PM_V3DRSTN);
  364. case BCM2835_POWER_DOMAIN_IMAGE:
  365. return bcm2835_power_power_off(pd, PM_IMAGE);
  366. case BCM2835_POWER_DOMAIN_IMAGE_PERI:
  367. return bcm2835_asb_power_off(pd, PM_IMAGE,
  368. 0, 0,
  369. PM_PERIRSTN);
  370. case BCM2835_POWER_DOMAIN_IMAGE_ISP:
  371. return bcm2835_asb_power_off(pd, PM_IMAGE,
  372. ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
  373. PM_ISPRSTN);
  374. case BCM2835_POWER_DOMAIN_IMAGE_H264:
  375. return bcm2835_asb_power_off(pd, PM_IMAGE,
  376. ASB_H264_M_CTRL, ASB_H264_S_CTRL,
  377. PM_H264RSTN);
  378. case BCM2835_POWER_DOMAIN_USB:
  379. PM_WRITE(PM_USB, 0);
  380. return 0;
  381. case BCM2835_POWER_DOMAIN_DSI0:
  382. PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
  383. PM_WRITE(PM_DSI0, 0);
  384. return 0;
  385. case BCM2835_POWER_DOMAIN_DSI1:
  386. PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
  387. PM_WRITE(PM_DSI1, 0);
  388. return 0;
  389. case BCM2835_POWER_DOMAIN_CCP2TX:
  390. PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
  391. PM_WRITE(PM_CCP2TX, 0);
  392. return 0;
  393. case BCM2835_POWER_DOMAIN_HDMI:
  394. PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_LDOPD);
  395. PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_CTRLEN);
  396. return 0;
  397. default:
  398. dev_err(power->dev, "Invalid domain %d\n", pd->domain);
  399. return -EINVAL;
  400. }
  401. }
  402. static int
  403. bcm2835_init_power_domain(struct bcm2835_power *power,
  404. int pd_xlate_index, const char *name)
  405. {
  406. struct device *dev = power->dev;
  407. struct bcm2835_power_domain *dom = &power->domains[pd_xlate_index];
  408. dom->clk = devm_clk_get(dev->parent, name);
  409. if (IS_ERR(dom->clk)) {
  410. int ret = PTR_ERR(dom->clk);
  411. if (ret == -EPROBE_DEFER)
  412. return ret;
  413. /* Some domains don't have a clk, so make sure that we
  414. * don't deref an error pointer later.
  415. */
  416. dom->clk = NULL;
  417. }
  418. dom->base.name = name;
  419. dom->base.power_on = bcm2835_power_pd_power_on;
  420. dom->base.power_off = bcm2835_power_pd_power_off;
  421. dom->domain = pd_xlate_index;
  422. dom->power = power;
  423. /* XXX: on/off at boot? */
  424. pm_genpd_init(&dom->base, NULL, true);
  425. power->pd_xlate.domains[pd_xlate_index] = &dom->base;
  426. return 0;
  427. }
  428. /** bcm2835_reset_reset - Resets a block that has a reset line in the
  429. * PM block.
  430. *
  431. * The consumer of the reset controller must have the power domain up
  432. * -- there's no reset ability with the power domain down. To reset
  433. * the sub-block, we just disable its access to memory through the
  434. * ASB, reset, and re-enable.
  435. */
  436. static int bcm2835_reset_reset(struct reset_controller_dev *rcdev,
  437. unsigned long id)
  438. {
  439. struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
  440. reset);
  441. struct bcm2835_power_domain *pd;
  442. int ret;
  443. switch (id) {
  444. case BCM2835_RESET_V3D:
  445. pd = &power->domains[BCM2835_POWER_DOMAIN_GRAFX_V3D];
  446. break;
  447. case BCM2835_RESET_H264:
  448. pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_H264];
  449. break;
  450. case BCM2835_RESET_ISP:
  451. pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_ISP];
  452. break;
  453. default:
  454. dev_err(power->dev, "Bad reset id %ld\n", id);
  455. return -EINVAL;
  456. }
  457. ret = bcm2835_power_pd_power_off(&pd->base);
  458. if (ret)
  459. return ret;
  460. return bcm2835_power_pd_power_on(&pd->base);
  461. }
  462. static int bcm2835_reset_status(struct reset_controller_dev *rcdev,
  463. unsigned long id)
  464. {
  465. struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
  466. reset);
  467. switch (id) {
  468. case BCM2835_RESET_V3D:
  469. return !PM_READ(PM_GRAFX & PM_V3DRSTN);
  470. case BCM2835_RESET_H264:
  471. return !PM_READ(PM_IMAGE & PM_H264RSTN);
  472. case BCM2835_RESET_ISP:
  473. return !PM_READ(PM_IMAGE & PM_ISPRSTN);
  474. default:
  475. return -EINVAL;
  476. }
  477. }
  478. static const struct reset_control_ops bcm2835_reset_ops = {
  479. .reset = bcm2835_reset_reset,
  480. .status = bcm2835_reset_status,
  481. };
  482. static const char *const power_domain_names[] = {
  483. [BCM2835_POWER_DOMAIN_GRAFX] = "grafx",
  484. [BCM2835_POWER_DOMAIN_GRAFX_V3D] = "v3d",
  485. [BCM2835_POWER_DOMAIN_IMAGE] = "image",
  486. [BCM2835_POWER_DOMAIN_IMAGE_PERI] = "peri_image",
  487. [BCM2835_POWER_DOMAIN_IMAGE_H264] = "h264",
  488. [BCM2835_POWER_DOMAIN_IMAGE_ISP] = "isp",
  489. [BCM2835_POWER_DOMAIN_USB] = "usb",
  490. [BCM2835_POWER_DOMAIN_DSI0] = "dsi0",
  491. [BCM2835_POWER_DOMAIN_DSI1] = "dsi1",
  492. [BCM2835_POWER_DOMAIN_CAM0] = "cam0",
  493. [BCM2835_POWER_DOMAIN_CAM1] = "cam1",
  494. [BCM2835_POWER_DOMAIN_CCP2TX] = "ccp2tx",
  495. [BCM2835_POWER_DOMAIN_HDMI] = "hdmi",
  496. };
  497. static int bcm2835_power_probe(struct platform_device *pdev)
  498. {
  499. struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
  500. struct device *dev = &pdev->dev;
  501. struct bcm2835_power *power;
  502. static const struct {
  503. int parent, child;
  504. } domain_deps[] = {
  505. { BCM2835_POWER_DOMAIN_GRAFX, BCM2835_POWER_DOMAIN_GRAFX_V3D },
  506. { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_PERI },
  507. { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_H264 },
  508. { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_ISP },
  509. { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_USB },
  510. { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM0 },
  511. { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM1 },
  512. };
  513. int ret = 0, i;
  514. u32 id;
  515. power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
  516. if (!power)
  517. return -ENOMEM;
  518. platform_set_drvdata(pdev, power);
  519. power->dev = dev;
  520. power->base = pm->base;
  521. power->asb = pm->asb;
  522. id = ASB_READ(ASB_AXI_BRDG_ID);
  523. if (id != 0x62726467 /* "BRDG" */) {
  524. dev_err(dev, "ASB register ID returned 0x%08x\n", id);
  525. return -ENODEV;
  526. }
  527. power->pd_xlate.domains = devm_kcalloc(dev,
  528. ARRAY_SIZE(power_domain_names),
  529. sizeof(*power->pd_xlate.domains),
  530. GFP_KERNEL);
  531. if (!power->pd_xlate.domains)
  532. return -ENOMEM;
  533. power->pd_xlate.num_domains = ARRAY_SIZE(power_domain_names);
  534. for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
  535. ret = bcm2835_init_power_domain(power, i, power_domain_names[i]);
  536. if (ret)
  537. goto fail;
  538. }
  539. for (i = 0; i < ARRAY_SIZE(domain_deps); i++) {
  540. pm_genpd_add_subdomain(&power->domains[domain_deps[i].parent].base,
  541. &power->domains[domain_deps[i].child].base);
  542. }
  543. power->reset.owner = THIS_MODULE;
  544. power->reset.nr_resets = BCM2835_RESET_COUNT;
  545. power->reset.ops = &bcm2835_reset_ops;
  546. power->reset.of_node = dev->parent->of_node;
  547. ret = devm_reset_controller_register(dev, &power->reset);
  548. if (ret)
  549. goto fail;
  550. of_genpd_add_provider_onecell(dev->parent->of_node, &power->pd_xlate);
  551. dev_info(dev, "Broadcom BCM2835 power domains driver");
  552. return 0;
  553. fail:
  554. for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
  555. struct generic_pm_domain *dom = &power->domains[i].base;
  556. if (dom->name)
  557. pm_genpd_remove(dom);
  558. }
  559. return ret;
  560. }
  561. static int bcm2835_power_remove(struct platform_device *pdev)
  562. {
  563. return 0;
  564. }
  565. static struct platform_driver bcm2835_power_driver = {
  566. .probe = bcm2835_power_probe,
  567. .remove = bcm2835_power_remove,
  568. .driver = {
  569. .name = "bcm2835-power",
  570. },
  571. };
  572. module_platform_driver(bcm2835_power_driver);
  573. MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
  574. MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM power domains and reset");
  575. MODULE_LICENSE("GPL");