soc.c 8.7 KB

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  1. /*
  2. * Copyright (C) 2015 Atmel
  3. *
  4. * Alexandre Belloni <alexandre.belloni@free-electrons.com
  5. * Boris Brezillon <boris.brezillon@free-electrons.com
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. *
  11. */
  12. #define pr_fmt(fmt) "AT91: " fmt
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/slab.h>
  18. #include <linux/sys_soc.h>
  19. #include "soc.h"
  20. #define AT91_DBGU_CIDR 0x40
  21. #define AT91_DBGU_EXID 0x44
  22. #define AT91_CHIPID_CIDR 0x00
  23. #define AT91_CHIPID_EXID 0x04
  24. #define AT91_CIDR_VERSION(x) ((x) & 0x1f)
  25. #define AT91_CIDR_EXT BIT(31)
  26. #define AT91_CIDR_MATCH_MASK 0x7fffffe0
  27. static const struct at91_soc __initconst socs[] = {
  28. #ifdef CONFIG_SOC_AT91RM9200
  29. AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
  30. #endif
  31. #ifdef CONFIG_SOC_AT91SAM9
  32. AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
  33. AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
  34. AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
  35. AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
  36. AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
  37. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
  38. "at91sam9m11", "at91sam9g45"),
  39. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
  40. "at91sam9m10", "at91sam9g45"),
  41. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
  42. "at91sam9g46", "at91sam9g45"),
  43. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
  44. "at91sam9g45", "at91sam9g45"),
  45. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
  46. "at91sam9g15", "at91sam9x5"),
  47. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
  48. "at91sam9g35", "at91sam9x5"),
  49. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
  50. "at91sam9x35", "at91sam9x5"),
  51. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
  52. "at91sam9g25", "at91sam9x5"),
  53. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
  54. "at91sam9x25", "at91sam9x5"),
  55. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
  56. "at91sam9cn12", "at91sam9n12"),
  57. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
  58. "at91sam9n12", "at91sam9n12"),
  59. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
  60. "at91sam9cn11", "at91sam9n12"),
  61. AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
  62. AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
  63. AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
  64. #endif
  65. #ifdef CONFIG_SOC_SAM9X60
  66. AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
  67. #endif
  68. #ifdef CONFIG_SOC_SAMA5
  69. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
  70. "sama5d21", "sama5d2"),
  71. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
  72. "sama5d22", "sama5d2"),
  73. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,
  74. "sama5d225c 16MiB SiP", "sama5d2"),
  75. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
  76. "sama5d23", "sama5d2"),
  77. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
  78. "sama5d24", "sama5d2"),
  79. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
  80. "sama5d24", "sama5d2"),
  81. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
  82. "sama5d26", "sama5d2"),
  83. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
  84. "sama5d27", "sama5d2"),
  85. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
  86. "sama5d27", "sama5d2"),
  87. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,
  88. "sama5d27c 128MiB SiP", "sama5d2"),
  89. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,
  90. "sama5d27c 64MiB SiP", "sama5d2"),
  91. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,
  92. "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
  93. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,
  94. "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
  95. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
  96. "sama5d28", "sama5d2"),
  97. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
  98. "sama5d28", "sama5d2"),
  99. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,
  100. "sama5d28c 128MiB SiP", "sama5d2"),
  101. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,
  102. "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
  103. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,
  104. "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
  105. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
  106. "sama5d31", "sama5d3"),
  107. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
  108. "sama5d33", "sama5d3"),
  109. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
  110. "sama5d34", "sama5d3"),
  111. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
  112. "sama5d35", "sama5d3"),
  113. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
  114. "sama5d36", "sama5d3"),
  115. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
  116. "sama5d41", "sama5d4"),
  117. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
  118. "sama5d42", "sama5d4"),
  119. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
  120. "sama5d43", "sama5d4"),
  121. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
  122. "sama5d44", "sama5d4"),
  123. #endif
  124. #ifdef CONFIG_SOC_SAMV7
  125. AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
  126. "same70q21", "same7"),
  127. AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
  128. "same70q20", "same7"),
  129. AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
  130. "same70q19", "same7"),
  131. AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
  132. "sams70q21", "sams7"),
  133. AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
  134. "sams70q20", "sams7"),
  135. AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
  136. "sams70q19", "sams7"),
  137. AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
  138. "samv71q21", "samv7"),
  139. AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
  140. "samv71q20", "samv7"),
  141. AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
  142. "samv71q19", "samv7"),
  143. AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,
  144. "samv70q20", "samv7"),
  145. AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,
  146. "samv70q19", "samv7"),
  147. #endif
  148. { /* sentinel */ },
  149. };
  150. static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
  151. {
  152. struct device_node *np;
  153. void __iomem *regs;
  154. np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
  155. if (!np)
  156. np = of_find_compatible_node(NULL, NULL,
  157. "atmel,at91sam9260-dbgu");
  158. if (!np)
  159. return -ENODEV;
  160. regs = of_iomap(np, 0);
  161. of_node_put(np);
  162. if (!regs) {
  163. pr_warn("Could not map DBGU iomem range");
  164. return -ENXIO;
  165. }
  166. *cidr = readl(regs + AT91_DBGU_CIDR);
  167. *exid = readl(regs + AT91_DBGU_EXID);
  168. iounmap(regs);
  169. return 0;
  170. }
  171. static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
  172. {
  173. struct device_node *np;
  174. void __iomem *regs;
  175. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
  176. if (!np)
  177. return -ENODEV;
  178. regs = of_iomap(np, 0);
  179. of_node_put(np);
  180. if (!regs) {
  181. pr_warn("Could not map DBGU iomem range");
  182. return -ENXIO;
  183. }
  184. *cidr = readl(regs + AT91_CHIPID_CIDR);
  185. *exid = readl(regs + AT91_CHIPID_EXID);
  186. iounmap(regs);
  187. return 0;
  188. }
  189. struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
  190. {
  191. struct soc_device_attribute *soc_dev_attr;
  192. const struct at91_soc *soc;
  193. struct soc_device *soc_dev;
  194. u32 cidr, exid;
  195. int ret;
  196. /*
  197. * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
  198. * in the dbgu device but in the chipid device whose purpose is only
  199. * to expose these two registers.
  200. */
  201. ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
  202. if (ret)
  203. ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
  204. if (ret) {
  205. if (ret == -ENODEV)
  206. pr_warn("Could not find identification node");
  207. return NULL;
  208. }
  209. for (soc = socs; soc->name; soc++) {
  210. if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
  211. continue;
  212. if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
  213. break;
  214. }
  215. if (!soc->name) {
  216. pr_warn("Could not find matching SoC description\n");
  217. return NULL;
  218. }
  219. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  220. if (!soc_dev_attr)
  221. return NULL;
  222. soc_dev_attr->family = soc->family;
  223. soc_dev_attr->soc_id = soc->name;
  224. soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
  225. AT91_CIDR_VERSION(cidr));
  226. soc_dev = soc_device_register(soc_dev_attr);
  227. if (IS_ERR(soc_dev)) {
  228. kfree(soc_dev_attr->revision);
  229. kfree(soc_dev_attr);
  230. pr_warn("Could not register SoC device\n");
  231. return NULL;
  232. }
  233. if (soc->family)
  234. pr_info("Detected SoC family: %s\n", soc->family);
  235. pr_info("Detected SoC: %s, revision %X\n", soc->name,
  236. AT91_CIDR_VERSION(cidr));
  237. return soc_dev;
  238. }
  239. static const struct of_device_id at91_soc_allowed_list[] __initconst = {
  240. { .compatible = "atmel,at91rm9200", },
  241. { .compatible = "atmel,at91sam9", },
  242. { .compatible = "atmel,sama5", },
  243. { .compatible = "atmel,samv7", },
  244. { }
  245. };
  246. static int __init atmel_soc_device_init(void)
  247. {
  248. struct device_node *np = of_find_node_by_path("/");
  249. if (!of_match_node(at91_soc_allowed_list, np))
  250. return 0;
  251. at91_soc_init(socs);
  252. return 0;
  253. }
  254. subsys_initcall(atmel_soc_device_init);