qcom-ngd-ctrl.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
  3. // Copyright (c) 2018, Linaro Limited
  4. #include <linux/irq.h>
  5. #include <linux/kernel.h>
  6. #include <linux/init.h>
  7. #include <linux/slab.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/slimbus.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/of.h>
  16. #include <linux/io.h>
  17. #include <linux/soc/qcom/qmi.h>
  18. #include <net/sock.h>
  19. #include "slimbus.h"
  20. /* NGD (Non-ported Generic Device) registers */
  21. #define NGD_CFG 0x0
  22. #define NGD_CFG_ENABLE BIT(0)
  23. #define NGD_CFG_RX_MSGQ_EN BIT(1)
  24. #define NGD_CFG_TX_MSGQ_EN BIT(2)
  25. #define NGD_STATUS 0x4
  26. #define NGD_LADDR BIT(1)
  27. #define NGD_RX_MSGQ_CFG 0x8
  28. #define NGD_INT_EN 0x10
  29. #define NGD_INT_RECFG_DONE BIT(24)
  30. #define NGD_INT_TX_NACKED_2 BIT(25)
  31. #define NGD_INT_MSG_BUF_CONTE BIT(26)
  32. #define NGD_INT_MSG_TX_INVAL BIT(27)
  33. #define NGD_INT_IE_VE_CHG BIT(28)
  34. #define NGD_INT_DEV_ERR BIT(29)
  35. #define NGD_INT_RX_MSG_RCVD BIT(30)
  36. #define NGD_INT_TX_MSG_SENT BIT(31)
  37. #define NGD_INT_STAT 0x14
  38. #define NGD_INT_CLR 0x18
  39. #define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \
  40. NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \
  41. NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \
  42. NGD_INT_RX_MSG_RCVD)
  43. /* Slimbus QMI service */
  44. #define SLIMBUS_QMI_SVC_ID 0x0301
  45. #define SLIMBUS_QMI_SVC_V1 1
  46. #define SLIMBUS_QMI_INS_ID 0
  47. #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020
  48. #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020
  49. #define SLIMBUS_QMI_POWER_REQ_V01 0x0021
  50. #define SLIMBUS_QMI_POWER_RESP_V01 0x0021
  51. #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022
  52. #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022
  53. #define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14
  54. #define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7
  55. #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14
  56. #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7
  57. #define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7
  58. /* QMI response timeout of 500ms */
  59. #define SLIMBUS_QMI_RESP_TOUT 1000
  60. /* User defined commands */
  61. #define SLIM_USR_MC_GENERIC_ACK 0x25
  62. #define SLIM_USR_MC_MASTER_CAPABILITY 0x0
  63. #define SLIM_USR_MC_REPORT_SATELLITE 0x1
  64. #define SLIM_USR_MC_ADDR_QUERY 0xD
  65. #define SLIM_USR_MC_ADDR_REPLY 0xE
  66. #define SLIM_USR_MC_DEFINE_CHAN 0x20
  67. #define SLIM_USR_MC_DEF_ACT_CHAN 0x21
  68. #define SLIM_USR_MC_CHAN_CTRL 0x23
  69. #define SLIM_USR_MC_RECONFIG_NOW 0x24
  70. #define SLIM_USR_MC_REQ_BW 0x28
  71. #define SLIM_USR_MC_CONNECT_SRC 0x2C
  72. #define SLIM_USR_MC_CONNECT_SINK 0x2D
  73. #define SLIM_USR_MC_DISCONNECT_PORT 0x2E
  74. #define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0
  75. #define QCOM_SLIM_NGD_AUTOSUSPEND MSEC_PER_SEC
  76. #define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000
  77. #define SLIM_LA_MGR 0xFF
  78. #define SLIM_ROOT_FREQ 24576000
  79. #define LADDR_RETRY 5
  80. /* Per spec.max 40 bytes per received message */
  81. #define SLIM_MSGQ_BUF_LEN 40
  82. #define QCOM_SLIM_NGD_DESC_NUM 32
  83. #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
  84. ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
  85. #define INIT_MX_RETRIES 10
  86. #define DEF_RETRY_MS 10
  87. #define SAT_MAGIC_LSB 0xD9
  88. #define SAT_MAGIC_MSB 0xC5
  89. #define SAT_MSG_VER 0x1
  90. #define SAT_MSG_PROT 0x1
  91. #define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev)
  92. struct ngd_reg_offset_data {
  93. u32 offset, size;
  94. };
  95. static const struct ngd_reg_offset_data ngd_v1_5_offset_info = {
  96. .offset = 0x1000,
  97. .size = 0x1000,
  98. };
  99. enum qcom_slim_ngd_state {
  100. QCOM_SLIM_NGD_CTRL_AWAKE,
  101. QCOM_SLIM_NGD_CTRL_IDLE,
  102. QCOM_SLIM_NGD_CTRL_ASLEEP,
  103. QCOM_SLIM_NGD_CTRL_DOWN,
  104. };
  105. struct qcom_slim_ngd_qmi {
  106. struct qmi_handle qmi;
  107. struct sockaddr_qrtr svc_info;
  108. struct qmi_handle svc_event_hdl;
  109. struct qmi_response_type_v01 resp;
  110. struct qmi_handle *handle;
  111. struct completion qmi_comp;
  112. };
  113. struct qcom_slim_ngd_ctrl;
  114. struct qcom_slim_ngd;
  115. struct qcom_slim_ngd_dma_desc {
  116. struct dma_async_tx_descriptor *desc;
  117. struct qcom_slim_ngd_ctrl *ctrl;
  118. struct completion *comp;
  119. dma_cookie_t cookie;
  120. dma_addr_t phys;
  121. void *base;
  122. };
  123. struct qcom_slim_ngd {
  124. struct platform_device *pdev;
  125. void __iomem *base;
  126. int id;
  127. };
  128. struct qcom_slim_ngd_ctrl {
  129. struct slim_framer framer;
  130. struct slim_controller ctrl;
  131. struct qcom_slim_ngd_qmi qmi;
  132. struct qcom_slim_ngd *ngd;
  133. struct device *dev;
  134. void __iomem *base;
  135. struct dma_chan *dma_rx_channel;
  136. struct dma_chan *dma_tx_channel;
  137. struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM];
  138. struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
  139. struct completion reconf;
  140. struct work_struct m_work;
  141. struct workqueue_struct *mwq;
  142. spinlock_t tx_buf_lock;
  143. enum qcom_slim_ngd_state state;
  144. dma_addr_t rx_phys_base;
  145. dma_addr_t tx_phys_base;
  146. void *rx_base;
  147. void *tx_base;
  148. int tx_tail;
  149. int tx_head;
  150. u32 ver;
  151. };
  152. enum slimbus_mode_enum_type_v01 {
  153. /* To force a 32 bit signed enum. Do not change or use*/
  154. SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
  155. SLIMBUS_MODE_SATELLITE_V01 = 1,
  156. SLIMBUS_MODE_MASTER_V01 = 2,
  157. SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
  158. };
  159. enum slimbus_pm_enum_type_v01 {
  160. /* To force a 32 bit signed enum. Do not change or use*/
  161. SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
  162. SLIMBUS_PM_INACTIVE_V01 = 1,
  163. SLIMBUS_PM_ACTIVE_V01 = 2,
  164. SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
  165. };
  166. enum slimbus_resp_enum_type_v01 {
  167. SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN,
  168. SLIMBUS_RESP_SYNCHRONOUS_V01 = 1,
  169. SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX,
  170. };
  171. struct slimbus_select_inst_req_msg_v01 {
  172. uint32_t instance;
  173. uint8_t mode_valid;
  174. enum slimbus_mode_enum_type_v01 mode;
  175. };
  176. struct slimbus_select_inst_resp_msg_v01 {
  177. struct qmi_response_type_v01 resp;
  178. };
  179. struct slimbus_power_req_msg_v01 {
  180. enum slimbus_pm_enum_type_v01 pm_req;
  181. uint8_t resp_type_valid;
  182. enum slimbus_resp_enum_type_v01 resp_type;
  183. };
  184. struct slimbus_power_resp_msg_v01 {
  185. struct qmi_response_type_v01 resp;
  186. };
  187. static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = {
  188. {
  189. .data_type = QMI_UNSIGNED_4_BYTE,
  190. .elem_len = 1,
  191. .elem_size = sizeof(uint32_t),
  192. .array_type = NO_ARRAY,
  193. .tlv_type = 0x01,
  194. .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
  195. instance),
  196. .ei_array = NULL,
  197. },
  198. {
  199. .data_type = QMI_OPT_FLAG,
  200. .elem_len = 1,
  201. .elem_size = sizeof(uint8_t),
  202. .array_type = NO_ARRAY,
  203. .tlv_type = 0x10,
  204. .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
  205. mode_valid),
  206. .ei_array = NULL,
  207. },
  208. {
  209. .data_type = QMI_UNSIGNED_4_BYTE,
  210. .elem_len = 1,
  211. .elem_size = sizeof(enum slimbus_mode_enum_type_v01),
  212. .array_type = NO_ARRAY,
  213. .tlv_type = 0x10,
  214. .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
  215. mode),
  216. .ei_array = NULL,
  217. },
  218. {
  219. .data_type = QMI_EOTI,
  220. .elem_len = 0,
  221. .elem_size = 0,
  222. .array_type = NO_ARRAY,
  223. .tlv_type = 0x00,
  224. .offset = 0,
  225. .ei_array = NULL,
  226. },
  227. };
  228. static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
  229. {
  230. .data_type = QMI_STRUCT,
  231. .elem_len = 1,
  232. .elem_size = sizeof(struct qmi_response_type_v01),
  233. .array_type = NO_ARRAY,
  234. .tlv_type = 0x02,
  235. .offset = offsetof(struct slimbus_select_inst_resp_msg_v01,
  236. resp),
  237. .ei_array = qmi_response_type_v01_ei,
  238. },
  239. {
  240. .data_type = QMI_EOTI,
  241. .elem_len = 0,
  242. .elem_size = 0,
  243. .array_type = NO_ARRAY,
  244. .tlv_type = 0x00,
  245. .offset = 0,
  246. .ei_array = NULL,
  247. },
  248. };
  249. static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = {
  250. {
  251. .data_type = QMI_UNSIGNED_4_BYTE,
  252. .elem_len = 1,
  253. .elem_size = sizeof(enum slimbus_pm_enum_type_v01),
  254. .array_type = NO_ARRAY,
  255. .tlv_type = 0x01,
  256. .offset = offsetof(struct slimbus_power_req_msg_v01,
  257. pm_req),
  258. .ei_array = NULL,
  259. },
  260. {
  261. .data_type = QMI_OPT_FLAG,
  262. .elem_len = 1,
  263. .elem_size = sizeof(uint8_t),
  264. .array_type = NO_ARRAY,
  265. .tlv_type = 0x10,
  266. .offset = offsetof(struct slimbus_power_req_msg_v01,
  267. resp_type_valid),
  268. },
  269. {
  270. .data_type = QMI_SIGNED_4_BYTE_ENUM,
  271. .elem_len = 1,
  272. .elem_size = sizeof(enum slimbus_resp_enum_type_v01),
  273. .array_type = NO_ARRAY,
  274. .tlv_type = 0x10,
  275. .offset = offsetof(struct slimbus_power_req_msg_v01,
  276. resp_type),
  277. },
  278. {
  279. .data_type = QMI_EOTI,
  280. .elem_len = 0,
  281. .elem_size = 0,
  282. .array_type = NO_ARRAY,
  283. .tlv_type = 0x00,
  284. .offset = 0,
  285. .ei_array = NULL,
  286. },
  287. };
  288. static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = {
  289. {
  290. .data_type = QMI_STRUCT,
  291. .elem_len = 1,
  292. .elem_size = sizeof(struct qmi_response_type_v01),
  293. .array_type = NO_ARRAY,
  294. .tlv_type = 0x02,
  295. .offset = offsetof(struct slimbus_power_resp_msg_v01, resp),
  296. .ei_array = qmi_response_type_v01_ei,
  297. },
  298. {
  299. .data_type = QMI_EOTI,
  300. .elem_len = 0,
  301. .elem_size = 0,
  302. .array_type = NO_ARRAY,
  303. .tlv_type = 0x00,
  304. .offset = 0,
  305. .ei_array = NULL,
  306. },
  307. };
  308. static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl,
  309. struct slimbus_select_inst_req_msg_v01 *req)
  310. {
  311. struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
  312. struct qmi_txn txn;
  313. int rc;
  314. rc = qmi_txn_init(ctrl->qmi.handle, &txn,
  315. slimbus_select_inst_resp_msg_v01_ei, &resp);
  316. if (rc < 0) {
  317. dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc);
  318. return rc;
  319. }
  320. rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
  321. SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01,
  322. SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN,
  323. slimbus_select_inst_req_msg_v01_ei, req);
  324. if (rc < 0) {
  325. dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
  326. qmi_txn_cancel(&txn);
  327. return rc;
  328. }
  329. rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
  330. if (rc < 0) {
  331. dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
  332. return rc;
  333. }
  334. /* Check the response */
  335. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  336. dev_err(ctrl->dev, "QMI request failed 0x%x\n",
  337. resp.resp.result);
  338. return -EREMOTEIO;
  339. }
  340. return 0;
  341. }
  342. static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle,
  343. struct sockaddr_qrtr *sq,
  344. struct qmi_txn *txn, const void *data)
  345. {
  346. struct slimbus_power_resp_msg_v01 *resp;
  347. resp = (struct slimbus_power_resp_msg_v01 *)data;
  348. if (resp->resp.result != QMI_RESULT_SUCCESS_V01)
  349. pr_err("QMI power request failed 0x%x\n",
  350. resp->resp.result);
  351. complete(&txn->completion);
  352. }
  353. static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl,
  354. struct slimbus_power_req_msg_v01 *req)
  355. {
  356. struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
  357. struct qmi_txn txn;
  358. int rc;
  359. rc = qmi_txn_init(ctrl->qmi.handle, &txn,
  360. slimbus_power_resp_msg_v01_ei, &resp);
  361. rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
  362. SLIMBUS_QMI_POWER_REQ_V01,
  363. SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
  364. slimbus_power_req_msg_v01_ei, req);
  365. if (rc < 0) {
  366. dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
  367. qmi_txn_cancel(&txn);
  368. return rc;
  369. }
  370. rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
  371. if (rc < 0) {
  372. dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
  373. return rc;
  374. }
  375. /* Check the response */
  376. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  377. dev_err(ctrl->dev, "QMI request failed 0x%x\n",
  378. resp.resp.result);
  379. return -EREMOTEIO;
  380. }
  381. return 0;
  382. }
  383. static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
  384. {
  385. .type = QMI_RESPONSE,
  386. .msg_id = SLIMBUS_QMI_POWER_RESP_V01,
  387. .ei = slimbus_power_resp_msg_v01_ei,
  388. .decoded_size = sizeof(struct slimbus_power_resp_msg_v01),
  389. .fn = qcom_slim_qmi_power_resp_cb,
  390. },
  391. {}
  392. };
  393. static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl,
  394. bool apps_is_master)
  395. {
  396. struct slimbus_select_inst_req_msg_v01 req;
  397. struct qmi_handle *handle;
  398. int rc;
  399. handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL);
  400. if (!handle)
  401. return -ENOMEM;
  402. rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
  403. NULL, qcom_slim_qmi_msg_handlers);
  404. if (rc < 0) {
  405. dev_err(ctrl->dev, "QMI client init failed: %d\n", rc);
  406. goto qmi_handle_init_failed;
  407. }
  408. rc = kernel_connect(handle->sock,
  409. (struct sockaddr *)&ctrl->qmi.svc_info,
  410. sizeof(ctrl->qmi.svc_info), 0);
  411. if (rc < 0) {
  412. dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc);
  413. goto qmi_connect_to_service_failed;
  414. }
  415. /* Instance is 0 based */
  416. req.instance = (ctrl->ngd->id >> 1);
  417. req.mode_valid = 1;
  418. /* Mode indicates the role of the ADSP */
  419. if (apps_is_master)
  420. req.mode = SLIMBUS_MODE_SATELLITE_V01;
  421. else
  422. req.mode = SLIMBUS_MODE_MASTER_V01;
  423. ctrl->qmi.handle = handle;
  424. rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req);
  425. if (rc) {
  426. dev_err(ctrl->dev, "failed to select h/w instance\n");
  427. goto qmi_select_instance_failed;
  428. }
  429. return 0;
  430. qmi_select_instance_failed:
  431. ctrl->qmi.handle = NULL;
  432. qmi_connect_to_service_failed:
  433. qmi_handle_release(handle);
  434. qmi_handle_init_failed:
  435. devm_kfree(ctrl->dev, handle);
  436. return rc;
  437. }
  438. static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl)
  439. {
  440. if (!ctrl->qmi.handle)
  441. return;
  442. qmi_handle_release(ctrl->qmi.handle);
  443. devm_kfree(ctrl->dev, ctrl->qmi.handle);
  444. ctrl->qmi.handle = NULL;
  445. }
  446. static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl,
  447. bool active)
  448. {
  449. struct slimbus_power_req_msg_v01 req;
  450. if (active)
  451. req.pm_req = SLIMBUS_PM_ACTIVE_V01;
  452. else
  453. req.pm_req = SLIMBUS_PM_INACTIVE_V01;
  454. req.resp_type_valid = 0;
  455. return qcom_slim_qmi_send_power_request(ctrl, &req);
  456. }
  457. static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len,
  458. struct completion *comp)
  459. {
  460. struct qcom_slim_ngd_dma_desc *desc;
  461. unsigned long flags;
  462. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  463. if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) {
  464. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  465. return NULL;
  466. }
  467. desc = &ctrl->txdesc[ctrl->tx_tail];
  468. desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN;
  469. desc->comp = comp;
  470. ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM;
  471. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  472. return desc->base;
  473. }
  474. static void qcom_slim_ngd_tx_msg_dma_cb(void *args)
  475. {
  476. struct qcom_slim_ngd_dma_desc *desc = args;
  477. struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
  478. unsigned long flags;
  479. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  480. if (desc->comp) {
  481. complete(desc->comp);
  482. desc->comp = NULL;
  483. }
  484. ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM;
  485. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  486. }
  487. static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl,
  488. void *buf, int len)
  489. {
  490. struct qcom_slim_ngd_dma_desc *desc;
  491. unsigned long flags;
  492. int index, offset;
  493. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  494. offset = buf - ctrl->tx_base;
  495. index = offset/SLIM_MSGQ_BUF_LEN;
  496. desc = &ctrl->txdesc[index];
  497. desc->phys = ctrl->tx_phys_base + offset;
  498. desc->base = ctrl->tx_base + offset;
  499. desc->ctrl = ctrl;
  500. len = (len + 3) & 0xfc;
  501. desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel,
  502. desc->phys, len,
  503. DMA_MEM_TO_DEV,
  504. DMA_PREP_INTERRUPT);
  505. if (!desc->desc) {
  506. dev_err(ctrl->dev, "unable to prepare channel\n");
  507. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  508. return -EINVAL;
  509. }
  510. desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb;
  511. desc->desc->callback_param = desc;
  512. desc->desc->cookie = dmaengine_submit(desc->desc);
  513. dma_async_issue_pending(ctrl->dma_tx_channel);
  514. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  515. return 0;
  516. }
  517. static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf)
  518. {
  519. u8 mc, mt, len;
  520. mt = SLIM_HEADER_GET_MT(buf[0]);
  521. len = SLIM_HEADER_GET_RL(buf[0]);
  522. mc = SLIM_HEADER_GET_MC(buf[1]);
  523. if (mc == SLIM_USR_MC_MASTER_CAPABILITY &&
  524. mt == SLIM_MSG_MT_SRC_REFERRED_USER)
  525. queue_work(ctrl->mwq, &ctrl->m_work);
  526. if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
  527. mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY &&
  528. mt == SLIM_MSG_MT_SRC_REFERRED_USER) ||
  529. (mc == SLIM_USR_MC_GENERIC_ACK &&
  530. mt == SLIM_MSG_MT_SRC_REFERRED_USER)) {
  531. slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4);
  532. pm_runtime_mark_last_busy(ctrl->dev);
  533. }
  534. }
  535. static void qcom_slim_ngd_rx_msgq_cb(void *args)
  536. {
  537. struct qcom_slim_ngd_dma_desc *desc = args;
  538. struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
  539. qcom_slim_ngd_rx(ctrl, (u8 *)desc->base);
  540. /* Add descriptor back to the queue */
  541. desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
  542. desc->phys, SLIM_MSGQ_BUF_LEN,
  543. DMA_DEV_TO_MEM,
  544. DMA_PREP_INTERRUPT);
  545. if (!desc->desc) {
  546. dev_err(ctrl->dev, "Unable to prepare rx channel\n");
  547. return;
  548. }
  549. desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
  550. desc->desc->callback_param = desc;
  551. desc->desc->cookie = dmaengine_submit(desc->desc);
  552. dma_async_issue_pending(ctrl->dma_rx_channel);
  553. }
  554. static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
  555. {
  556. struct qcom_slim_ngd_dma_desc *desc;
  557. int i;
  558. for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) {
  559. desc = &ctrl->rx_desc[i];
  560. desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN;
  561. desc->ctrl = ctrl;
  562. desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN;
  563. desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
  564. desc->phys, SLIM_MSGQ_BUF_LEN,
  565. DMA_DEV_TO_MEM,
  566. DMA_PREP_INTERRUPT);
  567. if (!desc->desc) {
  568. dev_err(ctrl->dev, "Unable to prepare rx channel\n");
  569. return -EINVAL;
  570. }
  571. desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
  572. desc->desc->callback_param = desc;
  573. desc->desc->cookie = dmaengine_submit(desc->desc);
  574. }
  575. dma_async_issue_pending(ctrl->dma_rx_channel);
  576. return 0;
  577. }
  578. static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
  579. {
  580. struct device *dev = ctrl->dev;
  581. int ret, size;
  582. ctrl->dma_rx_channel = dma_request_chan(dev, "rx");
  583. if (IS_ERR(ctrl->dma_rx_channel)) {
  584. dev_err(dev, "Failed to request RX dma channel");
  585. ret = PTR_ERR(ctrl->dma_rx_channel);
  586. ctrl->dma_rx_channel = NULL;
  587. return ret;
  588. }
  589. size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
  590. ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base,
  591. GFP_KERNEL);
  592. if (!ctrl->rx_base) {
  593. dev_err(dev, "dma_alloc_coherent failed\n");
  594. ret = -ENOMEM;
  595. goto rel_rx;
  596. }
  597. ret = qcom_slim_ngd_post_rx_msgq(ctrl);
  598. if (ret) {
  599. dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret);
  600. goto rx_post_err;
  601. }
  602. return 0;
  603. rx_post_err:
  604. dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
  605. rel_rx:
  606. dma_release_channel(ctrl->dma_rx_channel);
  607. return ret;
  608. }
  609. static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
  610. {
  611. struct device *dev = ctrl->dev;
  612. unsigned long flags;
  613. int ret = 0;
  614. int size;
  615. ctrl->dma_tx_channel = dma_request_chan(dev, "tx");
  616. if (IS_ERR(ctrl->dma_tx_channel)) {
  617. dev_err(dev, "Failed to request TX dma channel");
  618. ret = PTR_ERR(ctrl->dma_tx_channel);
  619. ctrl->dma_tx_channel = NULL;
  620. return ret;
  621. }
  622. size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
  623. ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base,
  624. GFP_KERNEL);
  625. if (!ctrl->tx_base) {
  626. dev_err(dev, "dma_alloc_coherent failed\n");
  627. ret = -EINVAL;
  628. goto rel_tx;
  629. }
  630. spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
  631. ctrl->tx_tail = 0;
  632. ctrl->tx_head = 0;
  633. spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
  634. return 0;
  635. rel_tx:
  636. dma_release_channel(ctrl->dma_tx_channel);
  637. return ret;
  638. }
  639. static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl)
  640. {
  641. int ret = 0;
  642. ret = qcom_slim_ngd_init_rx_msgq(ctrl);
  643. if (ret) {
  644. dev_err(ctrl->dev, "rx dma init failed\n");
  645. return ret;
  646. }
  647. ret = qcom_slim_ngd_init_tx_msgq(ctrl);
  648. if (ret)
  649. dev_err(ctrl->dev, "tx dma init failed\n");
  650. return ret;
  651. }
  652. static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d)
  653. {
  654. struct qcom_slim_ngd_ctrl *ctrl = d;
  655. void __iomem *base = ctrl->ngd->base;
  656. u32 stat = readl(base + NGD_INT_STAT);
  657. if ((stat & NGD_INT_MSG_BUF_CONTE) ||
  658. (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) ||
  659. (stat & NGD_INT_TX_NACKED_2)) {
  660. dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat);
  661. }
  662. writel(stat, base + NGD_INT_CLR);
  663. return IRQ_HANDLED;
  664. }
  665. static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl,
  666. struct slim_msg_txn *txn)
  667. {
  668. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
  669. DECLARE_COMPLETION_ONSTACK(tx_sent);
  670. DECLARE_COMPLETION_ONSTACK(done);
  671. int ret, timeout, i;
  672. u8 wbuf[SLIM_MSGQ_BUF_LEN];
  673. u8 rbuf[SLIM_MSGQ_BUF_LEN];
  674. u32 *pbuf;
  675. u8 *puc;
  676. u8 la = txn->la;
  677. bool usr_msg = false;
  678. if (txn->mt == SLIM_MSG_MT_CORE &&
  679. (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
  680. txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
  681. return 0;
  682. if (txn->dt == SLIM_MSG_DEST_ENUMADDR)
  683. return -EPROTONOSUPPORT;
  684. if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN ||
  685. txn->rl > SLIM_MSGQ_BUF_LEN) {
  686. dev_err(ctrl->dev, "msg exceeds HW limit\n");
  687. return -EINVAL;
  688. }
  689. pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent);
  690. if (!pbuf) {
  691. dev_err(ctrl->dev, "Message buffer unavailable\n");
  692. return -ENOMEM;
  693. }
  694. if (txn->mt == SLIM_MSG_MT_CORE &&
  695. (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE ||
  696. txn->mc == SLIM_MSG_MC_CONNECT_SINK ||
  697. txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) {
  698. txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  699. switch (txn->mc) {
  700. case SLIM_MSG_MC_CONNECT_SOURCE:
  701. txn->mc = SLIM_USR_MC_CONNECT_SRC;
  702. break;
  703. case SLIM_MSG_MC_CONNECT_SINK:
  704. txn->mc = SLIM_USR_MC_CONNECT_SINK;
  705. break;
  706. case SLIM_MSG_MC_DISCONNECT_PORT:
  707. txn->mc = SLIM_USR_MC_DISCONNECT_PORT;
  708. break;
  709. default:
  710. return -EINVAL;
  711. }
  712. usr_msg = true;
  713. i = 0;
  714. wbuf[i++] = txn->la;
  715. la = SLIM_LA_MGR;
  716. wbuf[i++] = txn->msg->wbuf[0];
  717. if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT)
  718. wbuf[i++] = txn->msg->wbuf[1];
  719. txn->comp = &done;
  720. ret = slim_alloc_txn_tid(sctrl, txn);
  721. if (ret) {
  722. dev_err(ctrl->dev, "Unable to allocate TID\n");
  723. return ret;
  724. }
  725. wbuf[i++] = txn->tid;
  726. txn->msg->num_bytes = i;
  727. txn->msg->wbuf = wbuf;
  728. txn->msg->rbuf = rbuf;
  729. txn->rl = txn->msg->num_bytes + 4;
  730. }
  731. /* HW expects length field to be excluded */
  732. txn->rl--;
  733. puc = (u8 *)pbuf;
  734. *pbuf = 0;
  735. if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
  736. *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0,
  737. la);
  738. puc += 3;
  739. } else {
  740. *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1,
  741. la);
  742. puc += 2;
  743. }
  744. if (slim_tid_txn(txn->mt, txn->mc))
  745. *(puc++) = txn->tid;
  746. if (slim_ec_txn(txn->mt, txn->mc)) {
  747. *(puc++) = (txn->ec & 0xFF);
  748. *(puc++) = (txn->ec >> 8) & 0xFF;
  749. }
  750. if (txn->msg && txn->msg->wbuf)
  751. memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
  752. ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
  753. if (ret)
  754. return ret;
  755. timeout = wait_for_completion_timeout(&tx_sent, HZ);
  756. if (!timeout) {
  757. dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
  758. txn->mt);
  759. return -ETIMEDOUT;
  760. }
  761. if (usr_msg) {
  762. timeout = wait_for_completion_timeout(&done, HZ);
  763. if (!timeout) {
  764. dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
  765. txn->mc, txn->mt);
  766. return -ETIMEDOUT;
  767. }
  768. }
  769. return 0;
  770. }
  771. static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl,
  772. struct slim_msg_txn *txn)
  773. {
  774. DECLARE_COMPLETION_ONSTACK(done);
  775. int ret, timeout;
  776. pm_runtime_get_sync(ctrl->dev);
  777. txn->comp = &done;
  778. ret = qcom_slim_ngd_xfer_msg(ctrl, txn);
  779. if (ret)
  780. return ret;
  781. timeout = wait_for_completion_timeout(&done, HZ);
  782. if (!timeout) {
  783. dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
  784. txn->mt);
  785. return -ETIMEDOUT;
  786. }
  787. return 0;
  788. }
  789. static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt)
  790. {
  791. struct slim_device *sdev = rt->dev;
  792. struct slim_controller *ctrl = sdev->ctrl;
  793. struct slim_val_inf msg = {0};
  794. u8 wbuf[SLIM_MSGQ_BUF_LEN];
  795. u8 rbuf[SLIM_MSGQ_BUF_LEN];
  796. struct slim_msg_txn txn = {0,};
  797. int i, ret;
  798. txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  799. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  800. txn.la = SLIM_LA_MGR;
  801. txn.ec = 0;
  802. txn.msg = &msg;
  803. txn.msg->num_bytes = 0;
  804. txn.msg->wbuf = wbuf;
  805. txn.msg->rbuf = rbuf;
  806. for (i = 0; i < rt->num_ports; i++) {
  807. struct slim_port *port = &rt->ports[i];
  808. if (txn.msg->num_bytes == 0) {
  809. int seg_interval = SLIM_SLOTS_PER_SUPERFRAME/rt->ratem;
  810. int exp;
  811. wbuf[txn.msg->num_bytes++] = sdev->laddr;
  812. wbuf[txn.msg->num_bytes] = rt->bps >> 2 |
  813. (port->ch.aux_fmt << 6);
  814. /* Data channel segment interval not multiple of 3 */
  815. exp = seg_interval % 3;
  816. if (exp)
  817. wbuf[txn.msg->num_bytes] |= BIT(5);
  818. txn.msg->num_bytes++;
  819. wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot;
  820. if (rt->prot == SLIM_PROTO_ISO)
  821. wbuf[txn.msg->num_bytes++] =
  822. port->ch.prrate |
  823. SLIM_CHANNEL_CONTENT_FL;
  824. else
  825. wbuf[txn.msg->num_bytes++] = port->ch.prrate;
  826. ret = slim_alloc_txn_tid(ctrl, &txn);
  827. if (ret) {
  828. dev_err(&sdev->dev, "Fail to allocate TID\n");
  829. return -ENXIO;
  830. }
  831. wbuf[txn.msg->num_bytes++] = txn.tid;
  832. }
  833. wbuf[txn.msg->num_bytes++] = port->ch.id;
  834. }
  835. txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
  836. txn.rl = txn.msg->num_bytes + 4;
  837. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  838. if (ret) {
  839. slim_free_txn_tid(ctrl, &txn);
  840. dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
  841. txn.mt);
  842. return ret;
  843. }
  844. txn.mc = SLIM_USR_MC_RECONFIG_NOW;
  845. txn.msg->num_bytes = 2;
  846. wbuf[1] = sdev->laddr;
  847. txn.rl = txn.msg->num_bytes + 4;
  848. ret = slim_alloc_txn_tid(ctrl, &txn);
  849. if (ret) {
  850. dev_err(ctrl->dev, "Fail to allocate TID\n");
  851. return ret;
  852. }
  853. wbuf[0] = txn.tid;
  854. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  855. if (ret) {
  856. slim_free_txn_tid(ctrl, &txn);
  857. dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
  858. txn.mt);
  859. }
  860. return ret;
  861. }
  862. static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl,
  863. struct slim_eaddr *ea, u8 *laddr)
  864. {
  865. struct slim_val_inf msg = {0};
  866. u8 failed_ea[6] = {0, 0, 0, 0, 0, 0};
  867. struct slim_msg_txn txn;
  868. u8 wbuf[10] = {0};
  869. u8 rbuf[10] = {0};
  870. int ret;
  871. txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
  872. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  873. txn.la = SLIM_LA_MGR;
  874. txn.ec = 0;
  875. txn.mc = SLIM_USR_MC_ADDR_QUERY;
  876. txn.rl = 11;
  877. txn.msg = &msg;
  878. txn.msg->num_bytes = 7;
  879. txn.msg->wbuf = wbuf;
  880. txn.msg->rbuf = rbuf;
  881. ret = slim_alloc_txn_tid(ctrl, &txn);
  882. if (ret < 0)
  883. return ret;
  884. wbuf[0] = (u8)txn.tid;
  885. memcpy(&wbuf[1], ea, sizeof(*ea));
  886. ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
  887. if (ret) {
  888. slim_free_txn_tid(ctrl, &txn);
  889. return ret;
  890. }
  891. if (!memcmp(rbuf, failed_ea, 6))
  892. return -ENXIO;
  893. *laddr = rbuf[6];
  894. return ret;
  895. }
  896. static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl)
  897. {
  898. if (ctrl->dma_rx_channel) {
  899. dmaengine_terminate_sync(ctrl->dma_rx_channel);
  900. dma_release_channel(ctrl->dma_rx_channel);
  901. }
  902. if (ctrl->dma_tx_channel) {
  903. dmaengine_terminate_sync(ctrl->dma_tx_channel);
  904. dma_release_channel(ctrl->dma_tx_channel);
  905. }
  906. ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL;
  907. return 0;
  908. }
  909. static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl)
  910. {
  911. u32 cfg = readl_relaxed(ctrl->ngd->base);
  912. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN ||
  913. ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP)
  914. qcom_slim_ngd_init_dma(ctrl);
  915. /* By default enable message queues */
  916. cfg |= NGD_CFG_RX_MSGQ_EN;
  917. cfg |= NGD_CFG_TX_MSGQ_EN;
  918. /* Enable NGD if it's not already enabled*/
  919. if (!(cfg & NGD_CFG_ENABLE))
  920. cfg |= NGD_CFG_ENABLE;
  921. writel_relaxed(cfg, ctrl->ngd->base);
  922. }
  923. static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl)
  924. {
  925. enum qcom_slim_ngd_state cur_state = ctrl->state;
  926. struct qcom_slim_ngd *ngd = ctrl->ngd;
  927. u32 laddr, rx_msgq;
  928. int timeout, ret = 0;
  929. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
  930. timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ);
  931. if (!timeout)
  932. return -EREMOTEIO;
  933. }
  934. if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP ||
  935. ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
  936. ret = qcom_slim_qmi_power_request(ctrl, true);
  937. if (ret) {
  938. dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n",
  939. ret);
  940. return ret;
  941. }
  942. }
  943. ctrl->ver = readl_relaxed(ctrl->base);
  944. /* Version info in 16 MSbits */
  945. ctrl->ver >>= 16;
  946. laddr = readl_relaxed(ngd->base + NGD_STATUS);
  947. if (laddr & NGD_LADDR) {
  948. /*
  949. * external MDM restart case where ADSP itself was active framer
  950. * For example, modem restarted when playback was active
  951. */
  952. if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) {
  953. dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n");
  954. return 0;
  955. }
  956. qcom_slim_ngd_setup(ctrl);
  957. return 0;
  958. }
  959. writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
  960. rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG);
  961. writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
  962. ngd->base + NGD_RX_MSGQ_CFG);
  963. qcom_slim_ngd_setup(ctrl);
  964. timeout = wait_for_completion_timeout(&ctrl->reconf, HZ);
  965. if (!timeout) {
  966. dev_err(ctrl->dev, "capability exchange timed-out\n");
  967. return -ETIMEDOUT;
  968. }
  969. return 0;
  970. }
  971. static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
  972. {
  973. struct slim_device *sbdev;
  974. struct device_node *node;
  975. for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) {
  976. sbdev = of_slim_get_device(&ctrl->ctrl, node);
  977. if (!sbdev)
  978. continue;
  979. if (slim_get_logical_addr(sbdev))
  980. dev_err(ctrl->dev, "Failed to get logical address\n");
  981. }
  982. }
  983. static void qcom_slim_ngd_master_worker(struct work_struct *work)
  984. {
  985. struct qcom_slim_ngd_ctrl *ctrl;
  986. struct slim_msg_txn txn;
  987. struct slim_val_inf msg = {0};
  988. int retries = 0;
  989. u8 wbuf[8];
  990. int ret = 0;
  991. ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work);
  992. txn.dt = SLIM_MSG_DEST_LOGICALADDR;
  993. txn.ec = 0;
  994. txn.mc = SLIM_USR_MC_REPORT_SATELLITE;
  995. txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
  996. txn.la = SLIM_LA_MGR;
  997. wbuf[0] = SAT_MAGIC_LSB;
  998. wbuf[1] = SAT_MAGIC_MSB;
  999. wbuf[2] = SAT_MSG_VER;
  1000. wbuf[3] = SAT_MSG_PROT;
  1001. txn.msg = &msg;
  1002. txn.msg->wbuf = wbuf;
  1003. txn.msg->num_bytes = 4;
  1004. txn.rl = 8;
  1005. dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n");
  1006. capability_retry:
  1007. ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn);
  1008. if (!ret) {
  1009. if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
  1010. complete(&ctrl->reconf);
  1011. else
  1012. dev_err(ctrl->dev, "unexpected state:%d\n",
  1013. ctrl->state);
  1014. if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
  1015. qcom_slim_ngd_notify_slaves(ctrl);
  1016. } else if (ret == -EIO) {
  1017. dev_err(ctrl->dev, "capability message NACKed, retrying\n");
  1018. if (retries < INIT_MX_RETRIES) {
  1019. msleep(DEF_RETRY_MS);
  1020. retries++;
  1021. goto capability_retry;
  1022. }
  1023. } else {
  1024. dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret);
  1025. }
  1026. }
  1027. static int qcom_slim_ngd_runtime_resume(struct device *dev)
  1028. {
  1029. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
  1030. int ret = 0;
  1031. if (!ctrl->qmi.handle)
  1032. return 0;
  1033. if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
  1034. ret = qcom_slim_ngd_power_up(ctrl);
  1035. if (ret) {
  1036. /* Did SSR cause this power up failure */
  1037. if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN)
  1038. ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
  1039. else
  1040. dev_err(ctrl->dev, "HW wakeup attempt during SSR\n");
  1041. } else {
  1042. ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE;
  1043. }
  1044. return 0;
  1045. }
  1046. static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable)
  1047. {
  1048. if (enable) {
  1049. int ret = qcom_slim_qmi_init(ctrl, false);
  1050. if (ret) {
  1051. dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n",
  1052. ret, ctrl->state);
  1053. return ret;
  1054. }
  1055. /* controller state should be in sync with framework state */
  1056. complete(&ctrl->qmi.qmi_comp);
  1057. if (!pm_runtime_enabled(ctrl->dev) ||
  1058. !pm_runtime_suspended(ctrl->dev))
  1059. qcom_slim_ngd_runtime_resume(ctrl->dev);
  1060. else
  1061. pm_runtime_resume(ctrl->dev);
  1062. pm_runtime_mark_last_busy(ctrl->dev);
  1063. pm_runtime_put(ctrl->dev);
  1064. ret = slim_register_controller(&ctrl->ctrl);
  1065. if (ret) {
  1066. dev_err(ctrl->dev, "error adding slim controller\n");
  1067. return ret;
  1068. }
  1069. dev_info(ctrl->dev, "SLIM controller Registered\n");
  1070. } else {
  1071. qcom_slim_qmi_exit(ctrl);
  1072. slim_unregister_controller(&ctrl->ctrl);
  1073. }
  1074. return 0;
  1075. }
  1076. static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl,
  1077. struct qmi_service *service)
  1078. {
  1079. struct qcom_slim_ngd_qmi *qmi =
  1080. container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
  1081. struct qcom_slim_ngd_ctrl *ctrl =
  1082. container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
  1083. qmi->svc_info.sq_family = AF_QIPCRTR;
  1084. qmi->svc_info.sq_node = service->node;
  1085. qmi->svc_info.sq_port = service->port;
  1086. qcom_slim_ngd_enable(ctrl, true);
  1087. return 0;
  1088. }
  1089. static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl,
  1090. struct qmi_service *service)
  1091. {
  1092. struct qcom_slim_ngd_qmi *qmi =
  1093. container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
  1094. struct qcom_slim_ngd_ctrl *ctrl =
  1095. container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
  1096. qmi->svc_info.sq_node = 0;
  1097. qmi->svc_info.sq_port = 0;
  1098. qcom_slim_ngd_enable(ctrl, false);
  1099. }
  1100. static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
  1101. .new_server = qcom_slim_ngd_qmi_new_server,
  1102. .del_server = qcom_slim_ngd_qmi_del_server,
  1103. };
  1104. static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl)
  1105. {
  1106. struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi;
  1107. int ret;
  1108. ret = qmi_handle_init(&qmi->svc_event_hdl, 0,
  1109. &qcom_slim_ngd_qmi_svc_event_ops, NULL);
  1110. if (ret < 0) {
  1111. dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret);
  1112. return ret;
  1113. }
  1114. ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID,
  1115. SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID);
  1116. if (ret < 0) {
  1117. dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret);
  1118. qmi_handle_release(&qmi->svc_event_hdl);
  1119. }
  1120. return ret;
  1121. }
  1122. static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi)
  1123. {
  1124. qmi_handle_release(&qmi->svc_event_hdl);
  1125. }
  1126. static struct platform_driver qcom_slim_ngd_driver;
  1127. #define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd"
  1128. static const struct of_device_id qcom_slim_ngd_dt_match[] = {
  1129. {
  1130. .compatible = "qcom,slim-ngd-v1.5.0",
  1131. .data = &ngd_v1_5_offset_info,
  1132. },{
  1133. .compatible = "qcom,slim-ngd-v2.1.0",
  1134. .data = &ngd_v1_5_offset_info,
  1135. },
  1136. {}
  1137. };
  1138. MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
  1139. static int of_qcom_slim_ngd_register(struct device *parent,
  1140. struct qcom_slim_ngd_ctrl *ctrl)
  1141. {
  1142. const struct ngd_reg_offset_data *data;
  1143. struct qcom_slim_ngd *ngd;
  1144. const struct of_device_id *match;
  1145. struct device_node *node;
  1146. u32 id;
  1147. match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node);
  1148. data = match->data;
  1149. for_each_available_child_of_node(parent->of_node, node) {
  1150. if (of_property_read_u32(node, "reg", &id))
  1151. continue;
  1152. ngd = kzalloc(sizeof(*ngd), GFP_KERNEL);
  1153. if (!ngd) {
  1154. of_node_put(node);
  1155. return -ENOMEM;
  1156. }
  1157. ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id);
  1158. if (!ngd->pdev) {
  1159. kfree(ngd);
  1160. of_node_put(node);
  1161. return -ENOMEM;
  1162. }
  1163. ngd->id = id;
  1164. ngd->pdev->dev.parent = parent;
  1165. ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME;
  1166. ngd->pdev->dev.of_node = node;
  1167. ctrl->ngd = ngd;
  1168. platform_device_add(ngd->pdev);
  1169. ngd->base = ctrl->base + ngd->id * data->offset +
  1170. (ngd->id - 1) * data->size;
  1171. return 0;
  1172. }
  1173. return -ENODEV;
  1174. }
  1175. static int qcom_slim_ngd_probe(struct platform_device *pdev)
  1176. {
  1177. struct device *dev = &pdev->dev;
  1178. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent);
  1179. int ret;
  1180. ctrl->ctrl.dev = dev;
  1181. platform_set_drvdata(pdev, ctrl);
  1182. pm_runtime_use_autosuspend(dev);
  1183. pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND);
  1184. pm_runtime_set_suspended(dev);
  1185. pm_runtime_enable(dev);
  1186. pm_runtime_get_noresume(dev);
  1187. ret = qcom_slim_ngd_qmi_svc_event_init(ctrl);
  1188. if (ret) {
  1189. dev_err(&pdev->dev, "QMI service registration failed:%d", ret);
  1190. return ret;
  1191. }
  1192. INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker);
  1193. ctrl->mwq = create_singlethread_workqueue("ngd_master");
  1194. if (!ctrl->mwq) {
  1195. dev_err(&pdev->dev, "Failed to start master worker\n");
  1196. ret = -ENOMEM;
  1197. goto wq_err;
  1198. }
  1199. return 0;
  1200. wq_err:
  1201. qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
  1202. if (ctrl->mwq)
  1203. destroy_workqueue(ctrl->mwq);
  1204. return ret;
  1205. }
  1206. static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev)
  1207. {
  1208. struct device *dev = &pdev->dev;
  1209. struct qcom_slim_ngd_ctrl *ctrl;
  1210. struct resource *res;
  1211. int ret;
  1212. ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
  1213. if (!ctrl)
  1214. return -ENOMEM;
  1215. dev_set_drvdata(dev, ctrl);
  1216. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1217. ctrl->base = devm_ioremap_resource(dev, res);
  1218. if (IS_ERR(ctrl->base))
  1219. return PTR_ERR(ctrl->base);
  1220. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1221. if (!res) {
  1222. dev_err(&pdev->dev, "no slimbus IRQ resource\n");
  1223. return -ENODEV;
  1224. }
  1225. ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt,
  1226. IRQF_TRIGGER_HIGH, "slim-ngd", ctrl);
  1227. if (ret) {
  1228. dev_err(&pdev->dev, "request IRQ failed\n");
  1229. return ret;
  1230. }
  1231. ctrl->dev = dev;
  1232. ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3;
  1233. ctrl->framer.superfreq =
  1234. ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
  1235. ctrl->ctrl.a_framer = &ctrl->framer;
  1236. ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR;
  1237. ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr;
  1238. ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream;
  1239. ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg;
  1240. ctrl->ctrl.wakeup = NULL;
  1241. ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
  1242. spin_lock_init(&ctrl->tx_buf_lock);
  1243. init_completion(&ctrl->reconf);
  1244. init_completion(&ctrl->qmi.qmi_comp);
  1245. platform_driver_register(&qcom_slim_ngd_driver);
  1246. return of_qcom_slim_ngd_register(dev, ctrl);
  1247. }
  1248. static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev)
  1249. {
  1250. platform_driver_unregister(&qcom_slim_ngd_driver);
  1251. return 0;
  1252. }
  1253. static int qcom_slim_ngd_remove(struct platform_device *pdev)
  1254. {
  1255. struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
  1256. pm_runtime_disable(&pdev->dev);
  1257. qcom_slim_ngd_enable(ctrl, false);
  1258. qcom_slim_ngd_exit_dma(ctrl);
  1259. qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
  1260. if (ctrl->mwq)
  1261. destroy_workqueue(ctrl->mwq);
  1262. kfree(ctrl->ngd);
  1263. ctrl->ngd = NULL;
  1264. return 0;
  1265. }
  1266. static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev)
  1267. {
  1268. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
  1269. if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE)
  1270. ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE;
  1271. pm_request_autosuspend(dev);
  1272. return -EAGAIN;
  1273. }
  1274. static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev)
  1275. {
  1276. struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
  1277. int ret = 0;
  1278. qcom_slim_ngd_exit_dma(ctrl);
  1279. if (!ctrl->qmi.handle)
  1280. return 0;
  1281. ret = qcom_slim_qmi_power_request(ctrl, false);
  1282. if (ret && ret != -EBUSY)
  1283. dev_info(ctrl->dev, "slim resource not idle:%d\n", ret);
  1284. if (!ret || ret == -ETIMEDOUT)
  1285. ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
  1286. return ret;
  1287. }
  1288. static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = {
  1289. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1290. pm_runtime_force_resume)
  1291. SET_RUNTIME_PM_OPS(
  1292. qcom_slim_ngd_runtime_suspend,
  1293. qcom_slim_ngd_runtime_resume,
  1294. qcom_slim_ngd_runtime_idle
  1295. )
  1296. };
  1297. static struct platform_driver qcom_slim_ngd_ctrl_driver = {
  1298. .probe = qcom_slim_ngd_ctrl_probe,
  1299. .remove = qcom_slim_ngd_ctrl_remove,
  1300. .driver = {
  1301. .name = "qcom,slim-ngd-ctrl",
  1302. .of_match_table = qcom_slim_ngd_dt_match,
  1303. },
  1304. };
  1305. static struct platform_driver qcom_slim_ngd_driver = {
  1306. .probe = qcom_slim_ngd_probe,
  1307. .remove = qcom_slim_ngd_remove,
  1308. .driver = {
  1309. .name = QCOM_SLIM_NGD_DRV_NAME,
  1310. .pm = &qcom_slim_ngd_dev_pm_ops,
  1311. },
  1312. };
  1313. module_platform_driver(qcom_slim_ngd_ctrl_driver);
  1314. MODULE_LICENSE("GPL v2");
  1315. MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller");