qcom-ctrl.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2011-2017, The Linux Foundation
  4. */
  5. #include <linux/irq.h>
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/io.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/delay.h>
  13. #include <linux/clk.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_runtime.h>
  16. #include "slimbus.h"
  17. /* Manager registers */
  18. #define MGR_CFG 0x200
  19. #define MGR_STATUS 0x204
  20. #define MGR_INT_EN 0x210
  21. #define MGR_INT_STAT 0x214
  22. #define MGR_INT_CLR 0x218
  23. #define MGR_TX_MSG 0x230
  24. #define MGR_RX_MSG 0x270
  25. #define MGR_IE_STAT 0x2F0
  26. #define MGR_VE_STAT 0x300
  27. #define MGR_CFG_ENABLE 1
  28. /* Framer registers */
  29. #define FRM_CFG 0x400
  30. #define FRM_STAT 0x404
  31. #define FRM_INT_EN 0x410
  32. #define FRM_INT_STAT 0x414
  33. #define FRM_INT_CLR 0x418
  34. #define FRM_WAKEUP 0x41C
  35. #define FRM_CLKCTL_DONE 0x420
  36. #define FRM_IE_STAT 0x430
  37. #define FRM_VE_STAT 0x440
  38. /* Interface registers */
  39. #define INTF_CFG 0x600
  40. #define INTF_STAT 0x604
  41. #define INTF_INT_EN 0x610
  42. #define INTF_INT_STAT 0x614
  43. #define INTF_INT_CLR 0x618
  44. #define INTF_IE_STAT 0x630
  45. #define INTF_VE_STAT 0x640
  46. /* Interrupt status bits */
  47. #define MGR_INT_TX_NACKED_2 BIT(25)
  48. #define MGR_INT_MSG_BUF_CONTE BIT(26)
  49. #define MGR_INT_RX_MSG_RCVD BIT(30)
  50. #define MGR_INT_TX_MSG_SENT BIT(31)
  51. /* Framer config register settings */
  52. #define FRM_ACTIVE 1
  53. #define CLK_GEAR 7
  54. #define ROOT_FREQ 11
  55. #define REF_CLK_GEAR 15
  56. #define INTR_WAKE 19
  57. #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
  58. ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
  59. #define SLIM_ROOT_FREQ 24576000
  60. #define QCOM_SLIM_AUTOSUSPEND 1000
  61. /* MAX message size over control channel */
  62. #define SLIM_MSGQ_BUF_LEN 40
  63. #define QCOM_TX_MSGS 2
  64. #define QCOM_RX_MSGS 8
  65. #define QCOM_BUF_ALLOC_RETRIES 10
  66. #define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))
  67. /* V2 Component registers */
  68. #define CFG_PORT_V2(r) ((r ## _V2))
  69. #define COMP_CFG_V2 4
  70. #define COMP_TRUST_CFG_V2 0x3000
  71. /* V1 Component registers */
  72. #define CFG_PORT_V1(r) ((r ## _V1))
  73. #define COMP_CFG_V1 0
  74. #define COMP_TRUST_CFG_V1 0x14
  75. /* Resource group info for manager, and non-ported generic device-components */
  76. #define EE_MGR_RSC_GRP (1 << 10)
  77. #define EE_NGD_2 (2 << 6)
  78. #define EE_NGD_1 0
  79. struct slim_ctrl_buf {
  80. void *base;
  81. spinlock_t lock;
  82. int head;
  83. int tail;
  84. int sl_sz;
  85. int n;
  86. };
  87. struct qcom_slim_ctrl {
  88. struct slim_controller ctrl;
  89. struct slim_framer framer;
  90. struct device *dev;
  91. void __iomem *base;
  92. void __iomem *slew_reg;
  93. struct slim_ctrl_buf rx;
  94. struct slim_ctrl_buf tx;
  95. struct completion **wr_comp;
  96. int irq;
  97. struct workqueue_struct *rxwq;
  98. struct work_struct wd;
  99. struct clk *rclk;
  100. struct clk *hclk;
  101. };
  102. static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf,
  103. u8 len, u32 tx_reg)
  104. {
  105. int count = (len + 3) >> 2;
  106. __iowrite32_copy(ctrl->base + tx_reg, buf, count);
  107. /* Ensure Oder of subsequent writes */
  108. mb();
  109. }
  110. static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl)
  111. {
  112. unsigned long flags;
  113. int idx;
  114. spin_lock_irqsave(&ctrl->rx.lock, flags);
  115. if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) {
  116. spin_unlock_irqrestore(&ctrl->rx.lock, flags);
  117. dev_err(ctrl->dev, "RX QUEUE full!");
  118. return NULL;
  119. }
  120. idx = ctrl->rx.tail;
  121. ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n;
  122. spin_unlock_irqrestore(&ctrl->rx.lock, flags);
  123. return ctrl->rx.base + (idx * ctrl->rx.sl_sz);
  124. }
  125. static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err)
  126. {
  127. struct completion *comp;
  128. unsigned long flags;
  129. int idx;
  130. spin_lock_irqsave(&ctrl->tx.lock, flags);
  131. idx = ctrl->tx.head;
  132. ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n;
  133. spin_unlock_irqrestore(&ctrl->tx.lock, flags);
  134. comp = ctrl->wr_comp[idx];
  135. ctrl->wr_comp[idx] = NULL;
  136. complete(comp);
  137. }
  138. static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl,
  139. u32 stat)
  140. {
  141. int err = 0;
  142. if (stat & MGR_INT_TX_MSG_SENT)
  143. writel_relaxed(MGR_INT_TX_MSG_SENT,
  144. ctrl->base + MGR_INT_CLR);
  145. if (stat & MGR_INT_TX_NACKED_2) {
  146. u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS);
  147. u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT);
  148. u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT);
  149. u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG);
  150. u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT);
  151. u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT);
  152. u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT);
  153. u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT);
  154. u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT);
  155. writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR);
  156. dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n",
  157. stat, mgr_stat);
  158. dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat);
  159. dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n",
  160. frm_intr_stat, frm_stat);
  161. dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n",
  162. frm_cfg, frm_ie_stat);
  163. dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n",
  164. intf_intr_stat, intf_stat);
  165. dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n",
  166. intf_ie_stat);
  167. err = -ENOTCONN;
  168. }
  169. slim_ack_txn(ctrl, err);
  170. return IRQ_HANDLED;
  171. }
  172. static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl,
  173. u32 stat)
  174. {
  175. u32 *rx_buf, pkt[10];
  176. bool q_rx = false;
  177. u8 mc, mt, len;
  178. pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG);
  179. mt = SLIM_HEADER_GET_MT(pkt[0]);
  180. len = SLIM_HEADER_GET_RL(pkt[0]);
  181. mc = SLIM_HEADER_GET_MC(pkt[0]>>8);
  182. /*
  183. * this message cannot be handled by ISR, so
  184. * let work-queue handle it
  185. */
  186. if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) {
  187. rx_buf = (u32 *)slim_alloc_rxbuf(ctrl);
  188. if (!rx_buf) {
  189. dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n",
  190. pkt[0]);
  191. goto rx_ret_irq;
  192. }
  193. rx_buf[0] = pkt[0];
  194. } else {
  195. rx_buf = pkt;
  196. }
  197. __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4,
  198. DIV_ROUND_UP(len, 4));
  199. switch (mc) {
  200. case SLIM_MSG_MC_REPORT_PRESENT:
  201. q_rx = true;
  202. break;
  203. case SLIM_MSG_MC_REPLY_INFORMATION:
  204. case SLIM_MSG_MC_REPLY_VALUE:
  205. slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1),
  206. (u8)(*rx_buf >> 24), (len - 4));
  207. break;
  208. default:
  209. dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n",
  210. mc, mt);
  211. break;
  212. }
  213. rx_ret_irq:
  214. writel(MGR_INT_RX_MSG_RCVD, ctrl->base +
  215. MGR_INT_CLR);
  216. if (q_rx)
  217. queue_work(ctrl->rxwq, &ctrl->wd);
  218. return IRQ_HANDLED;
  219. }
  220. static irqreturn_t qcom_slim_interrupt(int irq, void *d)
  221. {
  222. struct qcom_slim_ctrl *ctrl = d;
  223. u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT);
  224. int ret = IRQ_NONE;
  225. if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2)
  226. ret = qcom_slim_handle_tx_irq(ctrl, stat);
  227. if (stat & MGR_INT_RX_MSG_RCVD)
  228. ret = qcom_slim_handle_rx_irq(ctrl, stat);
  229. return ret;
  230. }
  231. static int qcom_clk_pause_wakeup(struct slim_controller *sctrl)
  232. {
  233. struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
  234. clk_prepare_enable(ctrl->hclk);
  235. clk_prepare_enable(ctrl->rclk);
  236. enable_irq(ctrl->irq);
  237. writel_relaxed(1, ctrl->base + FRM_WAKEUP);
  238. /* Make sure framer wakeup write goes through before ISR fires */
  239. mb();
  240. /*
  241. * HW Workaround: Currently, slave is reporting lost-sync messages
  242. * after SLIMbus comes out of clock pause.
  243. * Transaction with slave fail before slave reports that message
  244. * Give some time for that report to come
  245. * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe
  246. * being 250 usecs, we wait for 5-10 superframes here to ensure
  247. * we get the message
  248. */
  249. usleep_range(1250, 2500);
  250. return 0;
  251. }
  252. static void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl,
  253. struct slim_msg_txn *txn,
  254. struct completion *done)
  255. {
  256. unsigned long flags;
  257. int idx;
  258. spin_lock_irqsave(&ctrl->tx.lock, flags);
  259. if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) {
  260. spin_unlock_irqrestore(&ctrl->tx.lock, flags);
  261. dev_err(ctrl->dev, "controller TX buf unavailable");
  262. return NULL;
  263. }
  264. idx = ctrl->tx.tail;
  265. ctrl->wr_comp[idx] = done;
  266. ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n;
  267. spin_unlock_irqrestore(&ctrl->tx.lock, flags);
  268. return ctrl->tx.base + (idx * ctrl->tx.sl_sz);
  269. }
  270. static int qcom_xfer_msg(struct slim_controller *sctrl,
  271. struct slim_msg_txn *txn)
  272. {
  273. struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
  274. DECLARE_COMPLETION_ONSTACK(done);
  275. void *pbuf = slim_alloc_txbuf(ctrl, txn, &done);
  276. unsigned long ms = txn->rl + HZ;
  277. u8 *puc;
  278. int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES;
  279. u8 la = txn->la;
  280. u32 *head;
  281. /* HW expects length field to be excluded */
  282. txn->rl--;
  283. /* spin till buffer is made available */
  284. if (!pbuf) {
  285. while (retries--) {
  286. usleep_range(10000, 15000);
  287. pbuf = slim_alloc_txbuf(ctrl, txn, &done);
  288. if (pbuf)
  289. break;
  290. }
  291. }
  292. if (retries < 0 && !pbuf)
  293. return -ENOMEM;
  294. puc = (u8 *)pbuf;
  295. head = (u32 *)pbuf;
  296. if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
  297. *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
  298. txn->mc, 0, la);
  299. puc += 3;
  300. } else {
  301. *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
  302. txn->mc, 1, la);
  303. puc += 2;
  304. }
  305. if (slim_tid_txn(txn->mt, txn->mc))
  306. *(puc++) = txn->tid;
  307. if (slim_ec_txn(txn->mt, txn->mc)) {
  308. *(puc++) = (txn->ec & 0xFF);
  309. *(puc++) = (txn->ec >> 8) & 0xFF;
  310. }
  311. if (txn->msg && txn->msg->wbuf)
  312. memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
  313. qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG);
  314. timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms));
  315. if (!timeout) {
  316. dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
  317. txn->mt);
  318. ret = -ETIMEDOUT;
  319. }
  320. return ret;
  321. }
  322. static int qcom_set_laddr(struct slim_controller *sctrl,
  323. struct slim_eaddr *ead, u8 laddr)
  324. {
  325. struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
  326. struct {
  327. __be16 manf_id;
  328. __be16 prod_code;
  329. u8 dev_index;
  330. u8 instance;
  331. u8 laddr;
  332. } __packed p;
  333. struct slim_val_inf msg = {0};
  334. DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS,
  335. 10, laddr, &msg);
  336. int ret;
  337. p.manf_id = cpu_to_be16(ead->manf_id);
  338. p.prod_code = cpu_to_be16(ead->prod_code);
  339. p.dev_index = ead->dev_index;
  340. p.instance = ead->instance;
  341. p.laddr = laddr;
  342. msg.wbuf = (void *)&p;
  343. msg.num_bytes = 7;
  344. ret = slim_do_transfer(&ctrl->ctrl, &txn);
  345. if (ret)
  346. dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n",
  347. laddr, ret);
  348. return ret;
  349. }
  350. static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf)
  351. {
  352. unsigned long flags;
  353. spin_lock_irqsave(&ctrl->rx.lock, flags);
  354. if (ctrl->rx.tail == ctrl->rx.head) {
  355. spin_unlock_irqrestore(&ctrl->rx.lock, flags);
  356. return -ENODATA;
  357. }
  358. memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz),
  359. ctrl->rx.sl_sz);
  360. ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n;
  361. spin_unlock_irqrestore(&ctrl->rx.lock, flags);
  362. return 0;
  363. }
  364. static void qcom_slim_rxwq(struct work_struct *work)
  365. {
  366. u8 buf[SLIM_MSGQ_BUF_LEN];
  367. u8 mc, mt;
  368. int ret;
  369. struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl,
  370. wd);
  371. while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) {
  372. mt = SLIM_HEADER_GET_MT(buf[0]);
  373. mc = SLIM_HEADER_GET_MC(buf[1]);
  374. if (mt == SLIM_MSG_MT_CORE &&
  375. mc == SLIM_MSG_MC_REPORT_PRESENT) {
  376. struct slim_eaddr ea;
  377. u8 laddr;
  378. ea.manf_id = be16_to_cpup((__be16 *)&buf[2]);
  379. ea.prod_code = be16_to_cpup((__be16 *)&buf[4]);
  380. ea.dev_index = buf[6];
  381. ea.instance = buf[7];
  382. ret = slim_device_report_present(&ctrl->ctrl, &ea,
  383. &laddr);
  384. if (ret < 0)
  385. dev_err(ctrl->dev, "assign laddr failed:%d\n",
  386. ret);
  387. } else {
  388. dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n",
  389. mc, mt);
  390. }
  391. }
  392. }
  393. static void qcom_slim_prg_slew(struct platform_device *pdev,
  394. struct qcom_slim_ctrl *ctrl)
  395. {
  396. if (!ctrl->slew_reg) {
  397. /* SLEW RATE register for this SLIMbus */
  398. ctrl->slew_reg = devm_platform_ioremap_resource_byname(pdev, "slew");
  399. if (IS_ERR(ctrl->slew_reg))
  400. return;
  401. }
  402. writel_relaxed(1, ctrl->slew_reg);
  403. /* Make sure SLIMbus-slew rate enabling goes through */
  404. wmb();
  405. }
  406. static int qcom_slim_probe(struct platform_device *pdev)
  407. {
  408. struct qcom_slim_ctrl *ctrl;
  409. struct slim_controller *sctrl;
  410. struct resource *slim_mem;
  411. int ret, ver;
  412. ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
  413. if (!ctrl)
  414. return -ENOMEM;
  415. ctrl->hclk = devm_clk_get(&pdev->dev, "iface");
  416. if (IS_ERR(ctrl->hclk))
  417. return PTR_ERR(ctrl->hclk);
  418. ctrl->rclk = devm_clk_get(&pdev->dev, "core");
  419. if (IS_ERR(ctrl->rclk))
  420. return PTR_ERR(ctrl->rclk);
  421. ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ);
  422. if (ret) {
  423. dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret);
  424. return ret;
  425. }
  426. ctrl->irq = platform_get_irq(pdev, 0);
  427. if (!ctrl->irq) {
  428. dev_err(&pdev->dev, "no slimbus IRQ\n");
  429. return -ENODEV;
  430. }
  431. sctrl = &ctrl->ctrl;
  432. sctrl->dev = &pdev->dev;
  433. ctrl->dev = &pdev->dev;
  434. platform_set_drvdata(pdev, ctrl);
  435. dev_set_drvdata(ctrl->dev, ctrl);
  436. slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
  437. ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem);
  438. if (IS_ERR(ctrl->base))
  439. return PTR_ERR(ctrl->base);
  440. sctrl->set_laddr = qcom_set_laddr;
  441. sctrl->xfer_msg = qcom_xfer_msg;
  442. sctrl->wakeup = qcom_clk_pause_wakeup;
  443. ctrl->tx.n = QCOM_TX_MSGS;
  444. ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
  445. ctrl->rx.n = QCOM_RX_MSGS;
  446. ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN;
  447. ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *),
  448. GFP_KERNEL);
  449. if (!ctrl->wr_comp)
  450. return -ENOMEM;
  451. spin_lock_init(&ctrl->rx.lock);
  452. spin_lock_init(&ctrl->tx.lock);
  453. INIT_WORK(&ctrl->wd, qcom_slim_rxwq);
  454. ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx");
  455. if (!ctrl->rxwq) {
  456. dev_err(ctrl->dev, "Failed to start Rx WQ\n");
  457. return -ENOMEM;
  458. }
  459. ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8;
  460. ctrl->framer.superfreq =
  461. ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
  462. sctrl->a_framer = &ctrl->framer;
  463. sctrl->clkgear = SLIM_MAX_CLK_GEAR;
  464. qcom_slim_prg_slew(pdev, ctrl);
  465. ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt,
  466. IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl);
  467. if (ret) {
  468. dev_err(&pdev->dev, "request IRQ failed\n");
  469. goto err_request_irq_failed;
  470. }
  471. ret = clk_prepare_enable(ctrl->hclk);
  472. if (ret)
  473. goto err_hclk_enable_failed;
  474. ret = clk_prepare_enable(ctrl->rclk);
  475. if (ret)
  476. goto err_rclk_enable_failed;
  477. ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz,
  478. GFP_KERNEL);
  479. if (!ctrl->tx.base) {
  480. ret = -ENOMEM;
  481. goto err;
  482. }
  483. ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz,
  484. GFP_KERNEL);
  485. if (!ctrl->rx.base) {
  486. ret = -ENOMEM;
  487. goto err;
  488. }
  489. /* Register with framework before enabling frame, clock */
  490. ret = slim_register_controller(&ctrl->ctrl);
  491. if (ret) {
  492. dev_err(ctrl->dev, "error adding controller\n");
  493. goto err;
  494. }
  495. ver = readl_relaxed(ctrl->base);
  496. /* Version info in 16 MSbits */
  497. ver >>= 16;
  498. /* Component register initialization */
  499. writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
  500. writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1),
  501. ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver));
  502. writel((MGR_INT_TX_NACKED_2 |
  503. MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD |
  504. MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN);
  505. writel(1, ctrl->base + MGR_CFG);
  506. /* Framer register initialization */
  507. writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) |
  508. (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1,
  509. ctrl->base + FRM_CFG);
  510. writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG);
  511. writel(1, ctrl->base + INTF_CFG);
  512. writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
  513. pm_runtime_use_autosuspend(&pdev->dev);
  514. pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND);
  515. pm_runtime_set_active(&pdev->dev);
  516. pm_runtime_mark_last_busy(&pdev->dev);
  517. pm_runtime_enable(&pdev->dev);
  518. dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver);
  519. return 0;
  520. err:
  521. clk_disable_unprepare(ctrl->rclk);
  522. err_rclk_enable_failed:
  523. clk_disable_unprepare(ctrl->hclk);
  524. err_hclk_enable_failed:
  525. err_request_irq_failed:
  526. destroy_workqueue(ctrl->rxwq);
  527. return ret;
  528. }
  529. static int qcom_slim_remove(struct platform_device *pdev)
  530. {
  531. struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
  532. pm_runtime_disable(&pdev->dev);
  533. slim_unregister_controller(&ctrl->ctrl);
  534. clk_disable_unprepare(ctrl->rclk);
  535. clk_disable_unprepare(ctrl->hclk);
  536. destroy_workqueue(ctrl->rxwq);
  537. return 0;
  538. }
  539. /*
  540. * If PM_RUNTIME is not defined, these 2 functions become helper
  541. * functions to be called from system suspend/resume.
  542. */
  543. #ifdef CONFIG_PM
  544. static int qcom_slim_runtime_suspend(struct device *device)
  545. {
  546. struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
  547. int ret;
  548. dev_dbg(device, "pm_runtime: suspending...\n");
  549. ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED);
  550. if (ret) {
  551. dev_err(device, "clk pause not entered:%d", ret);
  552. } else {
  553. disable_irq(ctrl->irq);
  554. clk_disable_unprepare(ctrl->hclk);
  555. clk_disable_unprepare(ctrl->rclk);
  556. }
  557. return ret;
  558. }
  559. static int qcom_slim_runtime_resume(struct device *device)
  560. {
  561. struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
  562. int ret = 0;
  563. dev_dbg(device, "pm_runtime: resuming...\n");
  564. ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0);
  565. if (ret)
  566. dev_err(device, "clk pause not exited:%d", ret);
  567. return ret;
  568. }
  569. #endif
  570. #ifdef CONFIG_PM_SLEEP
  571. static int qcom_slim_suspend(struct device *dev)
  572. {
  573. int ret = 0;
  574. if (!pm_runtime_enabled(dev) ||
  575. (!pm_runtime_suspended(dev))) {
  576. dev_dbg(dev, "system suspend");
  577. ret = qcom_slim_runtime_suspend(dev);
  578. }
  579. return ret;
  580. }
  581. static int qcom_slim_resume(struct device *dev)
  582. {
  583. if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
  584. int ret;
  585. dev_dbg(dev, "system resume");
  586. ret = qcom_slim_runtime_resume(dev);
  587. if (!ret) {
  588. pm_runtime_mark_last_busy(dev);
  589. pm_request_autosuspend(dev);
  590. }
  591. return ret;
  592. }
  593. return 0;
  594. }
  595. #endif /* CONFIG_PM_SLEEP */
  596. static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
  597. SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
  598. SET_RUNTIME_PM_OPS(
  599. qcom_slim_runtime_suspend,
  600. qcom_slim_runtime_resume,
  601. NULL
  602. )
  603. };
  604. static const struct of_device_id qcom_slim_dt_match[] = {
  605. { .compatible = "qcom,slim", },
  606. { .compatible = "qcom,apq8064-slim", },
  607. {}
  608. };
  609. static struct platform_driver qcom_slim_driver = {
  610. .probe = qcom_slim_probe,
  611. .remove = qcom_slim_remove,
  612. .driver = {
  613. .name = "qcom_slim_ctrl",
  614. .of_match_table = qcom_slim_dt_match,
  615. .pm = &qcom_slim_dev_pm_ops,
  616. },
  617. };
  618. module_platform_driver(qcom_slim_driver);
  619. MODULE_LICENSE("GPL v2");
  620. MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");