wd719x.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards
  4. * Copyright 2013 Ondrej Zary
  5. *
  6. * Original driver by
  7. * Aaron Dewell <dewell@woods.net>
  8. * Gaerti <Juergen.Gaertner@mbox.si.uni-hannover.de>
  9. *
  10. * HW documentation available in book:
  11. *
  12. * SPIDER Command Protocol
  13. * by Chandru M. Sippy
  14. * SCSI Storage Products (MCP)
  15. * Western Digital Corporation
  16. * 09-15-95
  17. *
  18. * http://web.archive.org/web/20070717175254/http://sun1.rrzn.uni-hannover.de/gaertner.juergen/wd719x/Linux/Docu/Spider/
  19. */
  20. /*
  21. * Driver workflow:
  22. * 1. SCSI command is transformed to SCB (Spider Control Block) by the
  23. * queuecommand function.
  24. * 2. The address of the SCB is stored in a list to be able to access it, if
  25. * something goes wrong.
  26. * 3. The address of the SCB is written to the Controller, which loads the SCB
  27. * via BM-DMA and processes it.
  28. * 4. After it has finished, it generates an interrupt, and sets registers.
  29. *
  30. * flaws:
  31. * - abort/reset functions
  32. *
  33. * ToDo:
  34. * - tagged queueing
  35. */
  36. #include <linux/interrupt.h>
  37. #include <linux/module.h>
  38. #include <linux/delay.h>
  39. #include <linux/pci.h>
  40. #include <linux/firmware.h>
  41. #include <linux/eeprom_93cx6.h>
  42. #include <scsi/scsi_cmnd.h>
  43. #include <scsi/scsi_device.h>
  44. #include <scsi/scsi_host.h>
  45. #include "wd719x.h"
  46. /* low-level register access */
  47. static inline u8 wd719x_readb(struct wd719x *wd, u8 reg)
  48. {
  49. return ioread8(wd->base + reg);
  50. }
  51. static inline u32 wd719x_readl(struct wd719x *wd, u8 reg)
  52. {
  53. return ioread32(wd->base + reg);
  54. }
  55. static inline void wd719x_writeb(struct wd719x *wd, u8 reg, u8 val)
  56. {
  57. iowrite8(val, wd->base + reg);
  58. }
  59. static inline void wd719x_writew(struct wd719x *wd, u8 reg, u16 val)
  60. {
  61. iowrite16(val, wd->base + reg);
  62. }
  63. static inline void wd719x_writel(struct wd719x *wd, u8 reg, u32 val)
  64. {
  65. iowrite32(val, wd->base + reg);
  66. }
  67. /* wait until the command register is ready */
  68. static inline int wd719x_wait_ready(struct wd719x *wd)
  69. {
  70. int i = 0;
  71. do {
  72. if (wd719x_readb(wd, WD719X_AMR_COMMAND) == WD719X_CMD_READY)
  73. return 0;
  74. udelay(1);
  75. } while (i++ < WD719X_WAIT_FOR_CMD_READY);
  76. dev_err(&wd->pdev->dev, "command register is not ready: 0x%02x\n",
  77. wd719x_readb(wd, WD719X_AMR_COMMAND));
  78. return -ETIMEDOUT;
  79. }
  80. /* poll interrupt status register until command finishes */
  81. static inline int wd719x_wait_done(struct wd719x *wd, int timeout)
  82. {
  83. u8 status;
  84. while (timeout > 0) {
  85. status = wd719x_readb(wd, WD719X_AMR_INT_STATUS);
  86. if (status)
  87. break;
  88. timeout--;
  89. udelay(1);
  90. }
  91. if (timeout <= 0) {
  92. dev_err(&wd->pdev->dev, "direct command timed out\n");
  93. return -ETIMEDOUT;
  94. }
  95. if (status != WD719X_INT_NOERRORS) {
  96. u8 sue = wd719x_readb(wd, WD719X_AMR_SCB_ERROR);
  97. /* we get this after wd719x_dev_reset, it's not an error */
  98. if (sue == WD719X_SUE_TERM)
  99. return 0;
  100. /* we get this after wd719x_bus_reset, it's not an error */
  101. if (sue == WD719X_SUE_RESET)
  102. return 0;
  103. dev_err(&wd->pdev->dev, "direct command failed, status 0x%02x, SUE 0x%02x\n",
  104. status, sue);
  105. return -EIO;
  106. }
  107. return 0;
  108. }
  109. static int wd719x_direct_cmd(struct wd719x *wd, u8 opcode, u8 dev, u8 lun,
  110. u8 tag, dma_addr_t data, int timeout)
  111. {
  112. int ret = 0;
  113. /* clear interrupt status register (allow command register to clear) */
  114. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  115. /* Wait for the Command register to become free */
  116. if (wd719x_wait_ready(wd))
  117. return -ETIMEDOUT;
  118. /* disable interrupts except for RESET/ABORT (it breaks them) */
  119. if (opcode != WD719X_CMD_BUSRESET && opcode != WD719X_CMD_ABORT &&
  120. opcode != WD719X_CMD_ABORT_TAG && opcode != WD719X_CMD_RESET)
  121. dev |= WD719X_DISABLE_INT;
  122. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, dev);
  123. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_2, lun);
  124. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_3, tag);
  125. if (data)
  126. wd719x_writel(wd, WD719X_AMR_SCB_IN, data);
  127. /* clear interrupt status register again */
  128. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  129. /* Now, write the command */
  130. wd719x_writeb(wd, WD719X_AMR_COMMAND, opcode);
  131. if (timeout) /* wait for the command to complete */
  132. ret = wd719x_wait_done(wd, timeout);
  133. /* clear interrupt status register (clean up) */
  134. if (opcode != WD719X_CMD_READ_FIRMVER)
  135. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  136. return ret;
  137. }
  138. static void wd719x_destroy(struct wd719x *wd)
  139. {
  140. /* stop the RISC */
  141. if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0,
  142. WD719X_WAIT_FOR_RISC))
  143. dev_warn(&wd->pdev->dev, "RISC sleep command failed\n");
  144. /* disable RISC */
  145. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
  146. WARN_ON_ONCE(!list_empty(&wd->active_scbs));
  147. /* free internal buffers */
  148. dma_free_coherent(&wd->pdev->dev, wd->fw_size, wd->fw_virt,
  149. wd->fw_phys);
  150. wd->fw_virt = NULL;
  151. dma_free_coherent(&wd->pdev->dev, WD719X_HASH_TABLE_SIZE, wd->hash_virt,
  152. wd->hash_phys);
  153. wd->hash_virt = NULL;
  154. dma_free_coherent(&wd->pdev->dev, sizeof(struct wd719x_host_param),
  155. wd->params, wd->params_phys);
  156. wd->params = NULL;
  157. free_irq(wd->pdev->irq, wd);
  158. }
  159. /* finish a SCSI command, unmap buffers */
  160. static void wd719x_finish_cmd(struct wd719x_scb *scb, int result)
  161. {
  162. struct scsi_cmnd *cmd = scb->cmd;
  163. struct wd719x *wd = shost_priv(cmd->device->host);
  164. list_del(&scb->list);
  165. dma_unmap_single(&wd->pdev->dev, scb->phys,
  166. sizeof(struct wd719x_scb), DMA_BIDIRECTIONAL);
  167. scsi_dma_unmap(cmd);
  168. dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle,
  169. SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
  170. cmd->result = result << 16;
  171. cmd->scsi_done(cmd);
  172. }
  173. /* Build a SCB and send it to the card */
  174. static int wd719x_queuecommand(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
  175. {
  176. int i, count_sg;
  177. unsigned long flags;
  178. struct wd719x_scb *scb = scsi_cmd_priv(cmd);
  179. struct wd719x *wd = shost_priv(sh);
  180. scb->cmd = cmd;
  181. scb->CDB_tag = 0; /* Tagged queueing not supported yet */
  182. scb->devid = cmd->device->id;
  183. scb->lun = cmd->device->lun;
  184. /* copy the command */
  185. memcpy(scb->CDB, cmd->cmnd, cmd->cmd_len);
  186. /* map SCB */
  187. scb->phys = dma_map_single(&wd->pdev->dev, scb, sizeof(*scb),
  188. DMA_BIDIRECTIONAL);
  189. if (dma_mapping_error(&wd->pdev->dev, scb->phys))
  190. goto out_error;
  191. /* map sense buffer */
  192. scb->sense_buf_length = SCSI_SENSE_BUFFERSIZE;
  193. cmd->SCp.dma_handle = dma_map_single(&wd->pdev->dev, cmd->sense_buffer,
  194. SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
  195. if (dma_mapping_error(&wd->pdev->dev, cmd->SCp.dma_handle))
  196. goto out_unmap_scb;
  197. scb->sense_buf = cpu_to_le32(cmd->SCp.dma_handle);
  198. /* request autosense */
  199. scb->SCB_options |= WD719X_SCB_FLAGS_AUTO_REQUEST_SENSE;
  200. /* check direction */
  201. if (cmd->sc_data_direction == DMA_TO_DEVICE)
  202. scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION
  203. | WD719X_SCB_FLAGS_PCI_TO_SCSI;
  204. else if (cmd->sc_data_direction == DMA_FROM_DEVICE)
  205. scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION;
  206. /* Scather/gather */
  207. count_sg = scsi_dma_map(cmd);
  208. if (count_sg < 0)
  209. goto out_unmap_sense;
  210. BUG_ON(count_sg > WD719X_SG);
  211. if (count_sg) {
  212. struct scatterlist *sg;
  213. scb->data_length = cpu_to_le32(count_sg *
  214. sizeof(struct wd719x_sglist));
  215. scb->data_p = cpu_to_le32(scb->phys +
  216. offsetof(struct wd719x_scb, sg_list));
  217. scsi_for_each_sg(cmd, sg, count_sg, i) {
  218. scb->sg_list[i].ptr = cpu_to_le32(sg_dma_address(sg));
  219. scb->sg_list[i].length = cpu_to_le32(sg_dma_len(sg));
  220. }
  221. scb->SCB_options |= WD719X_SCB_FLAGS_DO_SCATTER_GATHER;
  222. } else { /* zero length */
  223. scb->data_length = 0;
  224. scb->data_p = 0;
  225. }
  226. spin_lock_irqsave(wd->sh->host_lock, flags);
  227. /* check if the Command register is free */
  228. if (wd719x_readb(wd, WD719X_AMR_COMMAND) != WD719X_CMD_READY) {
  229. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  230. return SCSI_MLQUEUE_HOST_BUSY;
  231. }
  232. list_add(&scb->list, &wd->active_scbs);
  233. /* write pointer to the AMR */
  234. wd719x_writel(wd, WD719X_AMR_SCB_IN, scb->phys);
  235. /* send SCB opcode */
  236. wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_PROCESS_SCB);
  237. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  238. return 0;
  239. out_unmap_sense:
  240. dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle,
  241. SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
  242. out_unmap_scb:
  243. dma_unmap_single(&wd->pdev->dev, scb->phys, sizeof(*scb),
  244. DMA_BIDIRECTIONAL);
  245. out_error:
  246. cmd->result = DID_ERROR << 16;
  247. cmd->scsi_done(cmd);
  248. return 0;
  249. }
  250. static int wd719x_chip_init(struct wd719x *wd)
  251. {
  252. int i, ret;
  253. u32 risc_init[3];
  254. const struct firmware *fw_wcs, *fw_risc;
  255. const char fwname_wcs[] = "wd719x-wcs.bin";
  256. const char fwname_risc[] = "wd719x-risc.bin";
  257. memset(wd->hash_virt, 0, WD719X_HASH_TABLE_SIZE);
  258. /* WCS (sequencer) firmware */
  259. ret = request_firmware(&fw_wcs, fwname_wcs, &wd->pdev->dev);
  260. if (ret) {
  261. dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n",
  262. fwname_wcs, ret);
  263. return ret;
  264. }
  265. /* RISC firmware */
  266. ret = request_firmware(&fw_risc, fwname_risc, &wd->pdev->dev);
  267. if (ret) {
  268. dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n",
  269. fwname_risc, ret);
  270. release_firmware(fw_wcs);
  271. return ret;
  272. }
  273. wd->fw_size = ALIGN(fw_wcs->size, 4) + fw_risc->size;
  274. if (!wd->fw_virt)
  275. wd->fw_virt = dma_alloc_coherent(&wd->pdev->dev, wd->fw_size,
  276. &wd->fw_phys, GFP_KERNEL);
  277. if (!wd->fw_virt) {
  278. ret = -ENOMEM;
  279. goto wd719x_init_end;
  280. }
  281. /* make a fresh copy of WCS and RISC code */
  282. memcpy(wd->fw_virt, fw_wcs->data, fw_wcs->size);
  283. memcpy(wd->fw_virt + ALIGN(fw_wcs->size, 4), fw_risc->data,
  284. fw_risc->size);
  285. /* Reset the Spider Chip and adapter itself */
  286. wd719x_writeb(wd, WD719X_PCI_PORT_RESET, WD719X_PCI_RESET);
  287. udelay(WD719X_WAIT_FOR_RISC);
  288. /* Clear PIO mode bits set by BIOS */
  289. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, 0);
  290. /* ensure RISC is not running */
  291. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
  292. /* ensure command port is ready */
  293. wd719x_writeb(wd, WD719X_AMR_COMMAND, 0);
  294. if (wd719x_wait_ready(wd)) {
  295. ret = -ETIMEDOUT;
  296. goto wd719x_init_end;
  297. }
  298. /* Transfer the first 2K words of RISC code to kick start the uP */
  299. risc_init[0] = wd->fw_phys; /* WCS FW */
  300. risc_init[1] = wd->fw_phys + ALIGN(fw_wcs->size, 4); /* RISC FW */
  301. risc_init[2] = wd->hash_phys; /* hash table */
  302. /* clear DMA status */
  303. wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3STATUS, 0);
  304. /* address to read firmware from */
  305. wd719x_writel(wd, WD719X_PCI_EXTERNAL_ADDR, risc_init[1]);
  306. /* base address to write firmware to (on card) */
  307. wd719x_writew(wd, WD719X_PCI_INTERNAL_ADDR, WD719X_PRAM_BASE_ADDR);
  308. /* size: first 2K words */
  309. wd719x_writew(wd, WD719X_PCI_DMA_TRANSFER_SIZE, 2048 * 2);
  310. /* start DMA */
  311. wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3CMD, WD719X_START_CHANNEL2_3DMA);
  312. /* wait for DMA to complete */
  313. i = WD719X_WAIT_FOR_RISC;
  314. while (i-- > 0) {
  315. u8 status = wd719x_readb(wd, WD719X_PCI_CHANNEL2_3STATUS);
  316. if (status == WD719X_START_CHANNEL2_3DONE)
  317. break;
  318. if (status == WD719X_START_CHANNEL2_3ABORT) {
  319. dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA aborted\n");
  320. ret = -EIO;
  321. goto wd719x_init_end;
  322. }
  323. udelay(1);
  324. }
  325. if (i < 1) {
  326. dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA timeout\n");
  327. ret = -ETIMEDOUT;
  328. goto wd719x_init_end;
  329. }
  330. /* firmware is loaded, now initialize and wake up the RISC */
  331. /* write RISC initialization long words to Spider */
  332. wd719x_writel(wd, WD719X_AMR_SCB_IN, risc_init[0]);
  333. wd719x_writel(wd, WD719X_AMR_SCB_IN + 4, risc_init[1]);
  334. wd719x_writel(wd, WD719X_AMR_SCB_IN + 8, risc_init[2]);
  335. /* disable interrupts during initialization of RISC */
  336. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, WD719X_DISABLE_INT);
  337. /* issue INITIALIZE RISC comand */
  338. wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_INIT_RISC);
  339. /* enable advanced mode (wake up RISC) */
  340. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, WD719X_ENABLE_ADVANCE_MODE);
  341. udelay(WD719X_WAIT_FOR_RISC);
  342. ret = wd719x_wait_done(wd, WD719X_WAIT_FOR_RISC);
  343. /* clear interrupt status register */
  344. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  345. if (ret) {
  346. dev_warn(&wd->pdev->dev, "Unable to initialize RISC\n");
  347. goto wd719x_init_end;
  348. }
  349. /* RISC is up and running */
  350. /* Read FW version from RISC */
  351. ret = wd719x_direct_cmd(wd, WD719X_CMD_READ_FIRMVER, 0, 0, 0, 0,
  352. WD719X_WAIT_FOR_RISC);
  353. if (ret) {
  354. dev_warn(&wd->pdev->dev, "Unable to read firmware version\n");
  355. goto wd719x_init_end;
  356. }
  357. dev_info(&wd->pdev->dev, "RISC initialized with firmware version %.2x.%.2x\n",
  358. wd719x_readb(wd, WD719X_AMR_SCB_OUT + 1),
  359. wd719x_readb(wd, WD719X_AMR_SCB_OUT));
  360. /* RESET SCSI bus */
  361. ret = wd719x_direct_cmd(wd, WD719X_CMD_BUSRESET, 0, 0, 0, 0,
  362. WD719X_WAIT_FOR_SCSI_RESET);
  363. if (ret) {
  364. dev_warn(&wd->pdev->dev, "SCSI bus reset failed\n");
  365. goto wd719x_init_end;
  366. }
  367. /* use HostParameter structure to set Spider's Host Parameter Block */
  368. ret = wd719x_direct_cmd(wd, WD719X_CMD_SET_PARAM, 0,
  369. sizeof(struct wd719x_host_param), 0,
  370. wd->params_phys, WD719X_WAIT_FOR_RISC);
  371. if (ret) {
  372. dev_warn(&wd->pdev->dev, "Failed to set HOST PARAMETERS\n");
  373. goto wd719x_init_end;
  374. }
  375. /* initiate SCAM (does nothing if disabled in BIOS) */
  376. /* bug?: we should pass a mask of static IDs which we don't have */
  377. ret = wd719x_direct_cmd(wd, WD719X_CMD_INIT_SCAM, 0, 0, 0, 0,
  378. WD719X_WAIT_FOR_SCSI_RESET);
  379. if (ret) {
  380. dev_warn(&wd->pdev->dev, "SCAM initialization failed\n");
  381. goto wd719x_init_end;
  382. }
  383. /* clear AMR_BIOS_SHARE_INT register */
  384. wd719x_writeb(wd, WD719X_AMR_BIOS_SHARE_INT, 0);
  385. wd719x_init_end:
  386. release_firmware(fw_wcs);
  387. release_firmware(fw_risc);
  388. return ret;
  389. }
  390. static int wd719x_abort(struct scsi_cmnd *cmd)
  391. {
  392. int action, result;
  393. unsigned long flags;
  394. struct wd719x_scb *scb = scsi_cmd_priv(cmd);
  395. struct wd719x *wd = shost_priv(cmd->device->host);
  396. dev_info(&wd->pdev->dev, "abort command, tag: %x\n", cmd->tag);
  397. action = /*cmd->tag ? WD719X_CMD_ABORT_TAG : */WD719X_CMD_ABORT;
  398. spin_lock_irqsave(wd->sh->host_lock, flags);
  399. result = wd719x_direct_cmd(wd, action, cmd->device->id,
  400. cmd->device->lun, cmd->tag, scb->phys, 0);
  401. wd719x_finish_cmd(scb, DID_ABORT);
  402. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  403. if (result)
  404. return FAILED;
  405. return SUCCESS;
  406. }
  407. static int wd719x_reset(struct scsi_cmnd *cmd, u8 opcode, u8 device)
  408. {
  409. int result;
  410. unsigned long flags;
  411. struct wd719x *wd = shost_priv(cmd->device->host);
  412. struct wd719x_scb *scb, *tmp;
  413. dev_info(&wd->pdev->dev, "%s reset requested\n",
  414. (opcode == WD719X_CMD_BUSRESET) ? "bus" : "device");
  415. spin_lock_irqsave(wd->sh->host_lock, flags);
  416. result = wd719x_direct_cmd(wd, opcode, device, 0, 0, 0,
  417. WD719X_WAIT_FOR_SCSI_RESET);
  418. /* flush all SCBs (or all for a device if dev_reset) */
  419. list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list) {
  420. if (opcode == WD719X_CMD_BUSRESET ||
  421. scb->cmd->device->id == device)
  422. wd719x_finish_cmd(scb, DID_RESET);
  423. }
  424. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  425. if (result)
  426. return FAILED;
  427. return SUCCESS;
  428. }
  429. static int wd719x_dev_reset(struct scsi_cmnd *cmd)
  430. {
  431. return wd719x_reset(cmd, WD719X_CMD_RESET, cmd->device->id);
  432. }
  433. static int wd719x_bus_reset(struct scsi_cmnd *cmd)
  434. {
  435. return wd719x_reset(cmd, WD719X_CMD_BUSRESET, 0);
  436. }
  437. static int wd719x_host_reset(struct scsi_cmnd *cmd)
  438. {
  439. struct wd719x *wd = shost_priv(cmd->device->host);
  440. struct wd719x_scb *scb, *tmp;
  441. unsigned long flags;
  442. dev_info(&wd->pdev->dev, "host reset requested\n");
  443. spin_lock_irqsave(wd->sh->host_lock, flags);
  444. /* stop the RISC */
  445. if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0,
  446. WD719X_WAIT_FOR_RISC))
  447. dev_warn(&wd->pdev->dev, "RISC sleep command failed\n");
  448. /* disable RISC */
  449. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
  450. /* flush all SCBs */
  451. list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list)
  452. wd719x_finish_cmd(scb, DID_RESET);
  453. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  454. /* Try to reinit the RISC */
  455. return wd719x_chip_init(wd) == 0 ? SUCCESS : FAILED;
  456. }
  457. static int wd719x_biosparam(struct scsi_device *sdev, struct block_device *bdev,
  458. sector_t capacity, int geom[])
  459. {
  460. if (capacity >= 0x200000) {
  461. geom[0] = 255; /* heads */
  462. geom[1] = 63; /* sectors */
  463. } else {
  464. geom[0] = 64; /* heads */
  465. geom[1] = 32; /* sectors */
  466. }
  467. geom[2] = sector_div(capacity, geom[0] * geom[1]); /* cylinders */
  468. return 0;
  469. }
  470. /* process a SCB-completion interrupt */
  471. static inline void wd719x_interrupt_SCB(struct wd719x *wd,
  472. union wd719x_regs regs,
  473. struct wd719x_scb *scb)
  474. {
  475. int result;
  476. /* now have to find result from card */
  477. switch (regs.bytes.SUE) {
  478. case WD719X_SUE_NOERRORS:
  479. result = DID_OK;
  480. break;
  481. case WD719X_SUE_REJECTED:
  482. dev_err(&wd->pdev->dev, "command rejected\n");
  483. result = DID_ERROR;
  484. break;
  485. case WD719X_SUE_SCBQFULL:
  486. dev_err(&wd->pdev->dev, "SCB queue is full\n");
  487. result = DID_ERROR;
  488. break;
  489. case WD719X_SUE_TERM:
  490. dev_dbg(&wd->pdev->dev, "SCB terminated by direct command\n");
  491. result = DID_ABORT; /* or DID_RESET? */
  492. break;
  493. case WD719X_SUE_CHAN1ABORT:
  494. case WD719X_SUE_CHAN23ABORT:
  495. result = DID_ABORT;
  496. dev_err(&wd->pdev->dev, "DMA abort\n");
  497. break;
  498. case WD719X_SUE_CHAN1PAR:
  499. case WD719X_SUE_CHAN23PAR:
  500. result = DID_PARITY;
  501. dev_err(&wd->pdev->dev, "DMA parity error\n");
  502. break;
  503. case WD719X_SUE_TIMEOUT:
  504. result = DID_TIME_OUT;
  505. dev_dbg(&wd->pdev->dev, "selection timeout\n");
  506. break;
  507. case WD719X_SUE_RESET:
  508. dev_dbg(&wd->pdev->dev, "bus reset occurred\n");
  509. result = DID_RESET;
  510. break;
  511. case WD719X_SUE_BUSERROR:
  512. dev_dbg(&wd->pdev->dev, "SCSI bus error\n");
  513. result = DID_ERROR;
  514. break;
  515. case WD719X_SUE_WRONGWAY:
  516. dev_err(&wd->pdev->dev, "wrong data transfer direction\n");
  517. result = DID_ERROR;
  518. break;
  519. case WD719X_SUE_BADPHASE:
  520. dev_err(&wd->pdev->dev, "invalid SCSI phase\n");
  521. result = DID_ERROR;
  522. break;
  523. case WD719X_SUE_TOOLONG:
  524. dev_err(&wd->pdev->dev, "record too long\n");
  525. result = DID_ERROR;
  526. break;
  527. case WD719X_SUE_BUSFREE:
  528. dev_err(&wd->pdev->dev, "unexpected bus free\n");
  529. result = DID_NO_CONNECT; /* or DID_ERROR ???*/
  530. break;
  531. case WD719X_SUE_ARSDONE:
  532. dev_dbg(&wd->pdev->dev, "auto request sense\n");
  533. if (regs.bytes.SCSI == 0)
  534. result = DID_OK;
  535. else
  536. result = DID_PARITY;
  537. break;
  538. case WD719X_SUE_IGNORED:
  539. dev_err(&wd->pdev->dev, "target id %d ignored command\n",
  540. scb->cmd->device->id);
  541. result = DID_NO_CONNECT;
  542. break;
  543. case WD719X_SUE_WRONGTAGS:
  544. dev_err(&wd->pdev->dev, "reversed tags\n");
  545. result = DID_ERROR;
  546. break;
  547. case WD719X_SUE_BADTAGS:
  548. dev_err(&wd->pdev->dev, "tag type not supported by target\n");
  549. result = DID_ERROR;
  550. break;
  551. case WD719X_SUE_NOSCAMID:
  552. dev_err(&wd->pdev->dev, "no SCAM soft ID available\n");
  553. result = DID_ERROR;
  554. break;
  555. default:
  556. dev_warn(&wd->pdev->dev, "unknown SUE error code: 0x%x\n",
  557. regs.bytes.SUE);
  558. result = DID_ERROR;
  559. break;
  560. }
  561. wd719x_finish_cmd(scb, result);
  562. }
  563. static irqreturn_t wd719x_interrupt(int irq, void *dev_id)
  564. {
  565. struct wd719x *wd = dev_id;
  566. union wd719x_regs regs;
  567. unsigned long flags;
  568. u32 SCB_out;
  569. spin_lock_irqsave(wd->sh->host_lock, flags);
  570. /* read SCB pointer back from card */
  571. SCB_out = wd719x_readl(wd, WD719X_AMR_SCB_OUT);
  572. /* read all status info at once */
  573. regs.all = cpu_to_le32(wd719x_readl(wd, WD719X_AMR_OP_CODE));
  574. switch (regs.bytes.INT) {
  575. case WD719X_INT_NONE:
  576. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  577. return IRQ_NONE;
  578. case WD719X_INT_LINKNOSTATUS:
  579. dev_err(&wd->pdev->dev, "linked command completed with no status\n");
  580. break;
  581. case WD719X_INT_BADINT:
  582. dev_err(&wd->pdev->dev, "unsolicited interrupt\n");
  583. break;
  584. case WD719X_INT_NOERRORS:
  585. case WD719X_INT_LINKNOERRORS:
  586. case WD719X_INT_ERRORSLOGGED:
  587. case WD719X_INT_SPIDERFAILED:
  588. /* was the cmd completed a direct or SCB command? */
  589. if (regs.bytes.OPC == WD719X_CMD_PROCESS_SCB) {
  590. struct wd719x_scb *scb;
  591. list_for_each_entry(scb, &wd->active_scbs, list)
  592. if (SCB_out == scb->phys)
  593. break;
  594. if (SCB_out == scb->phys)
  595. wd719x_interrupt_SCB(wd, regs, scb);
  596. else
  597. dev_err(&wd->pdev->dev, "card returned invalid SCB pointer\n");
  598. } else
  599. dev_dbg(&wd->pdev->dev, "direct command 0x%x completed\n",
  600. regs.bytes.OPC);
  601. break;
  602. case WD719X_INT_PIOREADY:
  603. dev_err(&wd->pdev->dev, "card indicates PIO data ready but we never use PIO\n");
  604. /* interrupt will not be cleared until all data is read */
  605. break;
  606. default:
  607. dev_err(&wd->pdev->dev, "unknown interrupt reason: %d\n",
  608. regs.bytes.INT);
  609. }
  610. /* clear interrupt so another can happen */
  611. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  612. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  613. return IRQ_HANDLED;
  614. }
  615. static void wd719x_eeprom_reg_read(struct eeprom_93cx6 *eeprom)
  616. {
  617. struct wd719x *wd = eeprom->data;
  618. u8 reg = wd719x_readb(wd, WD719X_PCI_GPIO_DATA);
  619. eeprom->reg_data_out = reg & WD719X_EE_DO;
  620. }
  621. static void wd719x_eeprom_reg_write(struct eeprom_93cx6 *eeprom)
  622. {
  623. struct wd719x *wd = eeprom->data;
  624. u8 reg = 0;
  625. if (eeprom->reg_data_in)
  626. reg |= WD719X_EE_DI;
  627. if (eeprom->reg_data_clock)
  628. reg |= WD719X_EE_CLK;
  629. if (eeprom->reg_chip_select)
  630. reg |= WD719X_EE_CS;
  631. wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, reg);
  632. }
  633. /* read config from EEPROM so it can be downloaded by the RISC on (re-)init */
  634. static void wd719x_read_eeprom(struct wd719x *wd)
  635. {
  636. struct eeprom_93cx6 eeprom;
  637. u8 gpio;
  638. struct wd719x_eeprom_header header;
  639. eeprom.data = wd;
  640. eeprom.register_read = wd719x_eeprom_reg_read;
  641. eeprom.register_write = wd719x_eeprom_reg_write;
  642. eeprom.width = PCI_EEPROM_WIDTH_93C46;
  643. /* set all outputs to low */
  644. wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, 0);
  645. /* configure GPIO pins */
  646. gpio = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL);
  647. /* GPIO outputs */
  648. gpio &= (~(WD719X_EE_CLK | WD719X_EE_DI | WD719X_EE_CS));
  649. /* GPIO input */
  650. gpio |= WD719X_EE_DO;
  651. wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, gpio);
  652. /* read EEPROM header */
  653. eeprom_93cx6_multireadb(&eeprom, 0, (u8 *)&header, sizeof(header));
  654. if (header.sig1 == 'W' && header.sig2 == 'D')
  655. eeprom_93cx6_multireadb(&eeprom, header.cfg_offset,
  656. (u8 *)wd->params,
  657. sizeof(struct wd719x_host_param));
  658. else { /* default EEPROM values */
  659. dev_warn(&wd->pdev->dev, "EEPROM signature is invalid (0x%02x 0x%02x), using default values\n",
  660. header.sig1, header.sig2);
  661. wd->params->ch_1_th = 0x10; /* 16 DWs = 64 B */
  662. wd->params->scsi_conf = 0x4c; /* 48ma, spue, parity check */
  663. wd->params->own_scsi_id = 0x07; /* ID 7, SCAM disabled */
  664. wd->params->sel_timeout = 0x4d; /* 250 ms */
  665. wd->params->sleep_timer = 0x01;
  666. wd->params->cdb_size = cpu_to_le16(0x5555); /* all 6 B */
  667. wd->params->scsi_pad = 0x1b;
  668. if (wd->type == WD719X_TYPE_7193) /* narrow card - disable */
  669. wd->params->wide = cpu_to_le32(0x00000000);
  670. else /* initiate & respond to WIDE messages */
  671. wd->params->wide = cpu_to_le32(0xffffffff);
  672. wd->params->sync = cpu_to_le32(0xffffffff);
  673. wd->params->soft_mask = 0x00; /* all disabled */
  674. wd->params->unsol_mask = 0x00; /* all disabled */
  675. }
  676. /* disable TAGGED messages */
  677. wd->params->tag_en = cpu_to_le16(0x0000);
  678. }
  679. /* Read card type from GPIO bits 1 and 3 */
  680. static enum wd719x_card_type wd719x_detect_type(struct wd719x *wd)
  681. {
  682. u8 card = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL);
  683. card |= WD719X_GPIO_ID_BITS;
  684. wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, card);
  685. card = wd719x_readb(wd, WD719X_PCI_GPIO_DATA) & WD719X_GPIO_ID_BITS;
  686. switch (card) {
  687. case 0x08:
  688. return WD719X_TYPE_7193;
  689. case 0x02:
  690. return WD719X_TYPE_7197;
  691. case 0x00:
  692. return WD719X_TYPE_7296;
  693. default:
  694. dev_warn(&wd->pdev->dev, "unknown card type 0x%x\n", card);
  695. return WD719X_TYPE_UNKNOWN;
  696. }
  697. }
  698. static int wd719x_board_found(struct Scsi_Host *sh)
  699. {
  700. struct wd719x *wd = shost_priv(sh);
  701. static const char * const card_types[] = {
  702. "Unknown card", "WD7193", "WD7197", "WD7296"
  703. };
  704. int ret;
  705. INIT_LIST_HEAD(&wd->active_scbs);
  706. sh->base = pci_resource_start(wd->pdev, 0);
  707. wd->type = wd719x_detect_type(wd);
  708. wd->sh = sh;
  709. sh->irq = wd->pdev->irq;
  710. wd->fw_virt = NULL;
  711. /* memory area for host (EEPROM) parameters */
  712. wd->params = dma_alloc_coherent(&wd->pdev->dev,
  713. sizeof(struct wd719x_host_param),
  714. &wd->params_phys, GFP_KERNEL);
  715. if (!wd->params) {
  716. dev_warn(&wd->pdev->dev, "unable to allocate parameter buffer\n");
  717. return -ENOMEM;
  718. }
  719. /* memory area for the RISC for hash table of outstanding requests */
  720. wd->hash_virt = dma_alloc_coherent(&wd->pdev->dev,
  721. WD719X_HASH_TABLE_SIZE,
  722. &wd->hash_phys, GFP_KERNEL);
  723. if (!wd->hash_virt) {
  724. dev_warn(&wd->pdev->dev, "unable to allocate hash buffer\n");
  725. ret = -ENOMEM;
  726. goto fail_free_params;
  727. }
  728. ret = request_irq(wd->pdev->irq, wd719x_interrupt, IRQF_SHARED,
  729. "wd719x", wd);
  730. if (ret) {
  731. dev_warn(&wd->pdev->dev, "unable to assign IRQ %d\n",
  732. wd->pdev->irq);
  733. goto fail_free_hash;
  734. }
  735. /* read parameters from EEPROM */
  736. wd719x_read_eeprom(wd);
  737. ret = wd719x_chip_init(wd);
  738. if (ret)
  739. goto fail_free_irq;
  740. sh->this_id = wd->params->own_scsi_id & WD719X_EE_SCSI_ID_MASK;
  741. dev_info(&wd->pdev->dev, "%s at I/O 0x%lx, IRQ %u, SCSI ID %d\n",
  742. card_types[wd->type], sh->base, sh->irq, sh->this_id);
  743. return 0;
  744. fail_free_irq:
  745. free_irq(wd->pdev->irq, wd);
  746. fail_free_hash:
  747. dma_free_coherent(&wd->pdev->dev, WD719X_HASH_TABLE_SIZE, wd->hash_virt,
  748. wd->hash_phys);
  749. fail_free_params:
  750. dma_free_coherent(&wd->pdev->dev, sizeof(struct wd719x_host_param),
  751. wd->params, wd->params_phys);
  752. return ret;
  753. }
  754. static struct scsi_host_template wd719x_template = {
  755. .module = THIS_MODULE,
  756. .name = "Western Digital 719x",
  757. .cmd_size = sizeof(struct wd719x_scb),
  758. .queuecommand = wd719x_queuecommand,
  759. .eh_abort_handler = wd719x_abort,
  760. .eh_device_reset_handler = wd719x_dev_reset,
  761. .eh_bus_reset_handler = wd719x_bus_reset,
  762. .eh_host_reset_handler = wd719x_host_reset,
  763. .bios_param = wd719x_biosparam,
  764. .proc_name = "wd719x",
  765. .can_queue = 255,
  766. .this_id = 7,
  767. .sg_tablesize = WD719X_SG,
  768. };
  769. static int wd719x_pci_probe(struct pci_dev *pdev, const struct pci_device_id *d)
  770. {
  771. int err;
  772. struct Scsi_Host *sh;
  773. struct wd719x *wd;
  774. err = pci_enable_device(pdev);
  775. if (err)
  776. goto fail;
  777. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
  778. dev_warn(&pdev->dev, "Unable to set 32-bit DMA mask\n");
  779. goto disable_device;
  780. }
  781. err = pci_request_regions(pdev, "wd719x");
  782. if (err)
  783. goto disable_device;
  784. pci_set_master(pdev);
  785. err = -ENODEV;
  786. if (pci_resource_len(pdev, 0) == 0)
  787. goto release_region;
  788. err = -ENOMEM;
  789. sh = scsi_host_alloc(&wd719x_template, sizeof(struct wd719x));
  790. if (!sh)
  791. goto release_region;
  792. wd = shost_priv(sh);
  793. wd->base = pci_iomap(pdev, 0, 0);
  794. if (!wd->base)
  795. goto free_host;
  796. wd->pdev = pdev;
  797. err = wd719x_board_found(sh);
  798. if (err)
  799. goto unmap;
  800. err = scsi_add_host(sh, &wd->pdev->dev);
  801. if (err)
  802. goto destroy;
  803. scsi_scan_host(sh);
  804. pci_set_drvdata(pdev, sh);
  805. return 0;
  806. destroy:
  807. wd719x_destroy(wd);
  808. unmap:
  809. pci_iounmap(pdev, wd->base);
  810. free_host:
  811. scsi_host_put(sh);
  812. release_region:
  813. pci_release_regions(pdev);
  814. disable_device:
  815. pci_disable_device(pdev);
  816. fail:
  817. return err;
  818. }
  819. static void wd719x_pci_remove(struct pci_dev *pdev)
  820. {
  821. struct Scsi_Host *sh = pci_get_drvdata(pdev);
  822. struct wd719x *wd = shost_priv(sh);
  823. scsi_remove_host(sh);
  824. wd719x_destroy(wd);
  825. pci_iounmap(pdev, wd->base);
  826. pci_release_regions(pdev);
  827. pci_disable_device(pdev);
  828. scsi_host_put(sh);
  829. }
  830. static const struct pci_device_id wd719x_pci_table[] = {
  831. { PCI_DEVICE(PCI_VENDOR_ID_WD, 0x3296) },
  832. {}
  833. };
  834. MODULE_DEVICE_TABLE(pci, wd719x_pci_table);
  835. static struct pci_driver wd719x_pci_driver = {
  836. .name = "wd719x",
  837. .id_table = wd719x_pci_table,
  838. .probe = wd719x_pci_probe,
  839. .remove = wd719x_pci_remove,
  840. };
  841. module_pci_driver(wd719x_pci_driver);
  842. MODULE_DESCRIPTION("Western Digital WD7193/7197/7296 SCSI driver");
  843. MODULE_AUTHOR("Ondrej Zary, Aaron Dewell, Juergen Gaertner");
  844. MODULE_LICENSE("GPL");
  845. MODULE_FIRMWARE("wd719x-wcs.bin");
  846. MODULE_FIRMWARE("wd719x-risc.bin");