wd33c93.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * wd33c93.h - Linux device driver definitions for the
  4. * Commodore Amiga A2091/590 SCSI controller card
  5. *
  6. * IMPORTANT: This file is for version 1.25 - 09/Jul/1997
  7. *
  8. * Copyright (c) 1996 John Shifflett, GeoLog Consulting
  9. * john@geolog.com
  10. * jshiffle@netcom.com
  11. */
  12. #ifndef WD33C93_H
  13. #define WD33C93_H
  14. #define PROC_INTERFACE /* add code for /proc/scsi/wd33c93/xxx interface */
  15. #ifdef PROC_INTERFACE
  16. #define PROC_STATISTICS /* add code for keeping various real time stats */
  17. #endif
  18. #define SYNC_DEBUG /* extra info on sync negotiation printed */
  19. #define DEBUGGING_ON /* enable command-line debugging bitmask */
  20. #define DEBUG_DEFAULTS 0 /* default debugging bitmask */
  21. #ifdef DEBUGGING_ON
  22. #define DB(f,a) if (hostdata->args & (f)) a;
  23. #else
  24. #define DB(f,a)
  25. #endif
  26. #define uchar unsigned char
  27. /* wd register names */
  28. #define WD_OWN_ID 0x00
  29. #define WD_CONTROL 0x01
  30. #define WD_TIMEOUT_PERIOD 0x02
  31. #define WD_CDB_1 0x03
  32. #define WD_CDB_2 0x04
  33. #define WD_CDB_3 0x05
  34. #define WD_CDB_4 0x06
  35. #define WD_CDB_5 0x07
  36. #define WD_CDB_6 0x08
  37. #define WD_CDB_7 0x09
  38. #define WD_CDB_8 0x0a
  39. #define WD_CDB_9 0x0b
  40. #define WD_CDB_10 0x0c
  41. #define WD_CDB_11 0x0d
  42. #define WD_CDB_12 0x0e
  43. #define WD_TARGET_LUN 0x0f
  44. #define WD_COMMAND_PHASE 0x10
  45. #define WD_SYNCHRONOUS_TRANSFER 0x11
  46. #define WD_TRANSFER_COUNT_MSB 0x12
  47. #define WD_TRANSFER_COUNT 0x13
  48. #define WD_TRANSFER_COUNT_LSB 0x14
  49. #define WD_DESTINATION_ID 0x15
  50. #define WD_SOURCE_ID 0x16
  51. #define WD_SCSI_STATUS 0x17
  52. #define WD_COMMAND 0x18
  53. #define WD_DATA 0x19
  54. #define WD_QUEUE_TAG 0x1a
  55. #define WD_AUXILIARY_STATUS 0x1f
  56. /* WD commands */
  57. #define WD_CMD_RESET 0x00
  58. #define WD_CMD_ABORT 0x01
  59. #define WD_CMD_ASSERT_ATN 0x02
  60. #define WD_CMD_NEGATE_ACK 0x03
  61. #define WD_CMD_DISCONNECT 0x04
  62. #define WD_CMD_RESELECT 0x05
  63. #define WD_CMD_SEL_ATN 0x06
  64. #define WD_CMD_SEL 0x07
  65. #define WD_CMD_SEL_ATN_XFER 0x08
  66. #define WD_CMD_SEL_XFER 0x09
  67. #define WD_CMD_RESEL_RECEIVE 0x0a
  68. #define WD_CMD_RESEL_SEND 0x0b
  69. #define WD_CMD_WAIT_SEL_RECEIVE 0x0c
  70. #define WD_CMD_TRANS_ADDR 0x18
  71. #define WD_CMD_TRANS_INFO 0x20
  72. #define WD_CMD_TRANSFER_PAD 0x21
  73. #define WD_CMD_SBT_MODE 0x80
  74. /* ASR register */
  75. #define ASR_INT (0x80)
  76. #define ASR_LCI (0x40)
  77. #define ASR_BSY (0x20)
  78. #define ASR_CIP (0x10)
  79. #define ASR_PE (0x02)
  80. #define ASR_DBR (0x01)
  81. /* SCSI Bus Phases */
  82. #define PHS_DATA_OUT 0x00
  83. #define PHS_DATA_IN 0x01
  84. #define PHS_COMMAND 0x02
  85. #define PHS_STATUS 0x03
  86. #define PHS_MESS_OUT 0x06
  87. #define PHS_MESS_IN 0x07
  88. /* Command Status Register definitions */
  89. /* reset state interrupts */
  90. #define CSR_RESET 0x00
  91. #define CSR_RESET_AF 0x01
  92. /* successful completion interrupts */
  93. #define CSR_RESELECT 0x10
  94. #define CSR_SELECT 0x11
  95. #define CSR_SEL_XFER_DONE 0x16
  96. #define CSR_XFER_DONE 0x18
  97. /* paused or aborted interrupts */
  98. #define CSR_MSGIN 0x20
  99. #define CSR_SDP 0x21
  100. #define CSR_SEL_ABORT 0x22
  101. #define CSR_RESEL_ABORT 0x25
  102. #define CSR_RESEL_ABORT_AM 0x27
  103. #define CSR_ABORT 0x28
  104. /* terminated interrupts */
  105. #define CSR_INVALID 0x40
  106. #define CSR_UNEXP_DISC 0x41
  107. #define CSR_TIMEOUT 0x42
  108. #define CSR_PARITY 0x43
  109. #define CSR_PARITY_ATN 0x44
  110. #define CSR_BAD_STATUS 0x45
  111. #define CSR_UNEXP 0x48
  112. /* service required interrupts */
  113. #define CSR_RESEL 0x80
  114. #define CSR_RESEL_AM 0x81
  115. #define CSR_DISC 0x85
  116. #define CSR_SRV_REQ 0x88
  117. /* Own ID/CDB Size register */
  118. #define OWNID_EAF 0x08
  119. #define OWNID_EHP 0x10
  120. #define OWNID_RAF 0x20
  121. #define OWNID_FS_8 0x00
  122. #define OWNID_FS_12 0x40
  123. #define OWNID_FS_16 0x80
  124. /* define these so we don't have to change a2091.c, etc. */
  125. #define WD33C93_FS_8_10 OWNID_FS_8
  126. #define WD33C93_FS_12_15 OWNID_FS_12
  127. #define WD33C93_FS_16_20 OWNID_FS_16
  128. /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
  129. #define WD33C93_FS_MHZ(mhz) (mhz)
  130. /* Control register */
  131. #define CTRL_HSP 0x01
  132. #define CTRL_HA 0x02
  133. #define CTRL_IDI 0x04
  134. #define CTRL_EDI 0x08
  135. #define CTRL_HHP 0x10
  136. #define CTRL_POLLED 0x00
  137. #define CTRL_BURST 0x20
  138. #define CTRL_BUS 0x40
  139. #define CTRL_DMA 0x80
  140. /* Timeout Period register */
  141. #define TIMEOUT_PERIOD_VALUE 20 /* 20 = 200 ms */
  142. /* Synchronous Transfer Register */
  143. #define STR_FSS 0x80
  144. /* Destination ID register */
  145. #define DSTID_DPD 0x40
  146. #define DATA_OUT_DIR 0
  147. #define DATA_IN_DIR 1
  148. #define DSTID_SCC 0x80
  149. /* Source ID register */
  150. #define SRCID_MASK 0x07
  151. #define SRCID_SIV 0x08
  152. #define SRCID_DSP 0x20
  153. #define SRCID_ES 0x40
  154. #define SRCID_ER 0x80
  155. /* This is what the 3393 chip looks like to us */
  156. typedef struct {
  157. #ifdef CONFIG_WD33C93_PIO
  158. unsigned int SASR;
  159. unsigned int SCMD;
  160. #else
  161. volatile unsigned char *SASR;
  162. volatile unsigned char *SCMD;
  163. #endif
  164. } wd33c93_regs;
  165. typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
  166. typedef void (*dma_stop_t) (struct Scsi_Host *instance,
  167. struct scsi_cmnd *SCpnt, int status);
  168. #define ILLEGAL_STATUS_BYTE 0xff
  169. #define DEFAULT_SX_PER 376 /* (ns) fairly safe */
  170. #define DEFAULT_SX_OFF 0 /* aka async */
  171. #define OPTIMUM_SX_PER 252 /* (ns) best we can do (mult-of-4) */
  172. #define OPTIMUM_SX_OFF 12 /* size of wd3393 fifo */
  173. struct sx_period {
  174. unsigned int period_ns;
  175. uchar reg_value;
  176. };
  177. /* FEF: defines for hostdata->dma_buffer_pool */
  178. #define BUF_CHIP_ALLOCED 0
  179. #define BUF_SCSI_ALLOCED 1
  180. struct WD33C93_hostdata {
  181. struct Scsi_Host *next;
  182. wd33c93_regs regs;
  183. spinlock_t lock;
  184. uchar clock_freq;
  185. uchar chip; /* what kind of wd33c93? */
  186. uchar microcode; /* microcode rev */
  187. uchar dma_buffer_pool; /* FEF: buffer from chip_ram? */
  188. int dma_dir; /* data transfer dir. */
  189. dma_setup_t dma_setup;
  190. dma_stop_t dma_stop;
  191. unsigned int dma_xfer_mask;
  192. uchar *dma_bounce_buffer;
  193. unsigned int dma_bounce_len;
  194. volatile uchar busy[8]; /* index = target, bit = lun */
  195. volatile struct scsi_cmnd *input_Q; /* commands waiting to be started */
  196. volatile struct scsi_cmnd *selecting; /* trying to select this command */
  197. volatile struct scsi_cmnd *connected; /* currently connected command */
  198. volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
  199. uchar state; /* what we are currently doing */
  200. uchar dma; /* current state of DMA (on/off) */
  201. uchar level2; /* extent to which Level-2 commands are used */
  202. uchar disconnect; /* disconnect/reselect policy */
  203. unsigned int args; /* set from command-line argument */
  204. uchar incoming_msg[8]; /* filled during message_in phase */
  205. int incoming_ptr; /* mainly used with EXTENDED messages */
  206. uchar outgoing_msg[8]; /* send this during next message_out */
  207. int outgoing_len; /* length of outgoing message */
  208. unsigned int default_sx_per; /* default transfer period for SCSI bus */
  209. uchar sync_xfer[8]; /* sync_xfer reg settings per target */
  210. uchar sync_stat[8]; /* status of sync negotiation per target */
  211. uchar no_sync; /* bitmask: don't do sync on these targets */
  212. uchar no_dma; /* set this flag to disable DMA */
  213. uchar dma_mode; /* DMA Burst Mode or Single Byte DMA */
  214. uchar fast; /* set this flag to enable Fast SCSI */
  215. struct sx_period sx_table[9]; /* transfer periods for actual DTC-setting */
  216. #ifdef PROC_INTERFACE
  217. uchar proc; /* bitmask: what's in proc output */
  218. #ifdef PROC_STATISTICS
  219. unsigned long cmd_cnt[8]; /* # of commands issued per target */
  220. unsigned long int_cnt; /* # of interrupts serviced */
  221. unsigned long pio_cnt; /* # of pio data transfers */
  222. unsigned long dma_cnt; /* # of DMA data transfers */
  223. unsigned long disc_allowed_cnt[8]; /* # of disconnects allowed per target */
  224. unsigned long disc_done_cnt[8]; /* # of disconnects done per target*/
  225. #endif
  226. #endif
  227. };
  228. /* defines for hostdata->chip */
  229. #define C_WD33C93 0
  230. #define C_WD33C93A 1
  231. #define C_WD33C93B 2
  232. #define C_UNKNOWN_CHIP 100
  233. /* defines for hostdata->state */
  234. #define S_UNCONNECTED 0
  235. #define S_SELECTING 1
  236. #define S_RUNNING_LEVEL2 2
  237. #define S_CONNECTED 3
  238. #define S_PRE_TMP_DISC 4
  239. #define S_PRE_CMP_DISC 5
  240. /* defines for hostdata->dma */
  241. #define D_DMA_OFF 0
  242. #define D_DMA_RUNNING 1
  243. /* defines for hostdata->level2 */
  244. /* NOTE: only the first 3 are implemented so far */
  245. #define L2_NONE 1 /* no combination commands - we get lots of ints */
  246. #define L2_SELECT 2 /* start with SEL_ATN_XFER, but never resume it */
  247. #define L2_BASIC 3 /* resume after STATUS ints & RDP messages */
  248. #define L2_DATA 4 /* resume after DATA_IN/OUT ints */
  249. #define L2_MOST 5 /* resume after anything except a RESELECT int */
  250. #define L2_RESELECT 6 /* resume after everything, including RESELECT ints */
  251. #define L2_ALL 7 /* always resume */
  252. /* defines for hostdata->disconnect */
  253. #define DIS_NEVER 0
  254. #define DIS_ADAPTIVE 1
  255. #define DIS_ALWAYS 2
  256. /* defines for hostdata->args */
  257. #define DB_TEST1 1<<0
  258. #define DB_TEST2 1<<1
  259. #define DB_QUEUE_COMMAND 1<<2
  260. #define DB_EXECUTE 1<<3
  261. #define DB_INTR 1<<4
  262. #define DB_TRANSFER 1<<5
  263. #define DB_MASK 0x3f
  264. /* defines for hostdata->sync_stat[] */
  265. #define SS_UNSET 0
  266. #define SS_FIRST 1
  267. #define SS_WAITING 2
  268. #define SS_SET 3
  269. /* defines for hostdata->proc */
  270. #define PR_VERSION 1<<0
  271. #define PR_INFO 1<<1
  272. #define PR_STATISTICS 1<<2
  273. #define PR_CONNECTED 1<<3
  274. #define PR_INPUTQ 1<<4
  275. #define PR_DISCQ 1<<5
  276. #define PR_TEST 1<<6
  277. #define PR_STOP 1<<7
  278. void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
  279. dma_setup_t setup, dma_stop_t stop, int clock_freq);
  280. int wd33c93_abort (struct scsi_cmnd *cmd);
  281. int wd33c93_queuecommand (struct Scsi_Host *h, struct scsi_cmnd *cmd);
  282. void wd33c93_intr (struct Scsi_Host *instance);
  283. int wd33c93_show_info(struct seq_file *, struct Scsi_Host *);
  284. int wd33c93_write_info(struct Scsi_Host *, char *, int);
  285. int wd33c93_host_reset (struct scsi_cmnd *);
  286. #endif /* WD33C93_H */