sym_fw2.h 47 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
  4. * of PCI-SCSI IO processors.
  5. *
  6. * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
  7. *
  8. * This driver is derived from the Linux sym53c8xx driver.
  9. * Copyright (C) 1998-2000 Gerard Roudier
  10. *
  11. * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
  12. * a port of the FreeBSD ncr driver to Linux-1.2.13.
  13. *
  14. * The original ncr driver has been written for 386bsd and FreeBSD by
  15. * Wolfgang Stanglmeier <wolf@cologne.de>
  16. * Stefan Esser <se@mi.Uni-Koeln.de>
  17. * Copyright (C) 1994 Wolfgang Stanglmeier
  18. *
  19. * Other major contributions:
  20. *
  21. * NVRAM detection and reading.
  22. * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
  23. *
  24. *-----------------------------------------------------------------------------
  25. */
  26. /*
  27. * Scripts for SYMBIOS-Processor
  28. *
  29. * We have to know the offsets of all labels before we reach
  30. * them (for forward jumps). Therefore we declare a struct
  31. * here. If you make changes inside the script,
  32. *
  33. * DONT FORGET TO CHANGE THE LENGTHS HERE!
  34. */
  35. /*
  36. * Script fragments which are loaded into the on-chip RAM
  37. * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
  38. * Must not exceed 4K bytes.
  39. */
  40. struct SYM_FWA_SCR {
  41. u32 start [ 14];
  42. u32 getjob_begin [ 4];
  43. u32 getjob_end [ 4];
  44. #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  45. u32 select [ 6];
  46. #else
  47. u32 select [ 4];
  48. #endif
  49. #if SYM_CONF_DMA_ADDRESSING_MODE == 2
  50. u32 is_dmap_dirty [ 4];
  51. #endif
  52. u32 wf_sel_done [ 2];
  53. u32 sel_done [ 2];
  54. u32 send_ident [ 2];
  55. #ifdef SYM_CONF_IARB_SUPPORT
  56. u32 select2 [ 8];
  57. #else
  58. u32 select2 [ 2];
  59. #endif
  60. u32 command [ 2];
  61. u32 dispatch [ 28];
  62. u32 sel_no_cmd [ 10];
  63. u32 init [ 6];
  64. u32 clrack [ 4];
  65. u32 datai_done [ 10];
  66. u32 datai_done_wsr [ 20];
  67. u32 datao_done [ 10];
  68. u32 datao_done_wss [ 6];
  69. u32 datai_phase [ 4];
  70. u32 datao_phase [ 6];
  71. u32 msg_in [ 2];
  72. u32 msg_in2 [ 10];
  73. #ifdef SYM_CONF_IARB_SUPPORT
  74. u32 status [ 14];
  75. #else
  76. u32 status [ 10];
  77. #endif
  78. u32 complete [ 6];
  79. u32 complete2 [ 12];
  80. u32 done [ 14];
  81. u32 done_end [ 2];
  82. u32 complete_error [ 4];
  83. u32 save_dp [ 12];
  84. u32 restore_dp [ 8];
  85. u32 disconnect [ 12];
  86. #ifdef SYM_CONF_IARB_SUPPORT
  87. u32 idle [ 4];
  88. #else
  89. u32 idle [ 2];
  90. #endif
  91. #ifdef SYM_CONF_IARB_SUPPORT
  92. u32 ungetjob [ 6];
  93. #else
  94. u32 ungetjob [ 4];
  95. #endif
  96. #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  97. u32 reselect [ 4];
  98. #else
  99. u32 reselect [ 2];
  100. #endif
  101. u32 reselected [ 22];
  102. u32 resel_scntl4 [ 20];
  103. u32 resel_lun0 [ 6];
  104. #if SYM_CONF_MAX_TASK*4 > 512
  105. u32 resel_tag [ 26];
  106. #elif SYM_CONF_MAX_TASK*4 > 256
  107. u32 resel_tag [ 20];
  108. #else
  109. u32 resel_tag [ 16];
  110. #endif
  111. u32 resel_dsa [ 2];
  112. u32 resel_dsa1 [ 4];
  113. u32 resel_no_tag [ 6];
  114. u32 data_in [SYM_CONF_MAX_SG * 2];
  115. u32 data_in2 [ 4];
  116. u32 data_out [SYM_CONF_MAX_SG * 2];
  117. u32 data_out2 [ 4];
  118. u32 pm0_data [ 12];
  119. u32 pm0_data_out [ 6];
  120. u32 pm0_data_end [ 6];
  121. u32 pm1_data [ 12];
  122. u32 pm1_data_out [ 6];
  123. u32 pm1_data_end [ 6];
  124. };
  125. /*
  126. * Script fragments which stay in main memory for all chips
  127. * except for chips that support 8K on-chip RAM.
  128. */
  129. struct SYM_FWB_SCR {
  130. u32 start64 [ 2];
  131. u32 no_data [ 2];
  132. #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  133. u32 sel_for_abort [ 18];
  134. #else
  135. u32 sel_for_abort [ 16];
  136. #endif
  137. u32 sel_for_abort_1 [ 2];
  138. u32 msg_in_etc [ 12];
  139. u32 msg_received [ 4];
  140. u32 msg_weird_seen [ 4];
  141. u32 msg_extended [ 20];
  142. u32 msg_bad [ 6];
  143. u32 msg_weird [ 4];
  144. u32 msg_weird1 [ 8];
  145. u32 wdtr_resp [ 6];
  146. u32 send_wdtr [ 4];
  147. u32 sdtr_resp [ 6];
  148. u32 send_sdtr [ 4];
  149. u32 ppr_resp [ 6];
  150. u32 send_ppr [ 4];
  151. u32 nego_bad_phase [ 4];
  152. u32 msg_out [ 4];
  153. u32 msg_out_done [ 4];
  154. u32 data_ovrun [ 2];
  155. u32 data_ovrun1 [ 22];
  156. u32 data_ovrun2 [ 8];
  157. u32 abort_resel [ 16];
  158. u32 resend_ident [ 4];
  159. u32 ident_break [ 4];
  160. u32 ident_break_atn [ 4];
  161. u32 sdata_in [ 6];
  162. u32 resel_bad_lun [ 4];
  163. u32 bad_i_t_l [ 4];
  164. u32 bad_i_t_l_q [ 4];
  165. u32 bad_status [ 6];
  166. u32 pm_handle [ 20];
  167. u32 pm_handle1 [ 4];
  168. u32 pm_save [ 4];
  169. u32 pm0_save [ 12];
  170. u32 pm_save_end [ 4];
  171. u32 pm1_save [ 14];
  172. /* WSR handling */
  173. u32 pm_wsr_handle [ 38];
  174. u32 wsr_ma_helper [ 4];
  175. /* Data area */
  176. u32 zero [ 1];
  177. u32 scratch [ 1];
  178. u32 pm0_data_addr [ 1];
  179. u32 pm1_data_addr [ 1];
  180. u32 done_pos [ 1];
  181. u32 startpos [ 1];
  182. u32 targtbl [ 1];
  183. };
  184. /*
  185. * Script fragments used at initialisations.
  186. * Only runs out of main memory.
  187. */
  188. struct SYM_FWZ_SCR {
  189. u32 snooptest [ 6];
  190. u32 snoopend [ 2];
  191. };
  192. static struct SYM_FWA_SCR SYM_FWA_SCR = {
  193. /*--------------------------< START >----------------------------*/ {
  194. /*
  195. * Switch the LED on.
  196. * Will be patched with a NO_OP if LED
  197. * not needed or not desired.
  198. */
  199. SCR_REG_REG (gpreg, SCR_AND, 0xfe),
  200. 0,
  201. /*
  202. * Clear SIGP.
  203. */
  204. SCR_FROM_REG (ctest2),
  205. 0,
  206. /*
  207. * Stop here if the C code wants to perform
  208. * some error recovery procedure manually.
  209. * (Indicate this by setting SEM in ISTAT)
  210. */
  211. SCR_FROM_REG (istat),
  212. 0,
  213. /*
  214. * Report to the C code the next position in
  215. * the start queue the SCRIPTS will schedule.
  216. * The C code must not change SCRATCHA.
  217. */
  218. SCR_LOAD_ABS (scratcha, 4),
  219. PADDR_B (startpos),
  220. SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
  221. SIR_SCRIPT_STOPPED,
  222. /*
  223. * Start the next job.
  224. *
  225. * @DSA = start point for this job.
  226. * SCRATCHA = address of this job in the start queue.
  227. *
  228. * We will restore startpos with SCRATCHA if we fails the
  229. * arbitration or if it is the idle job.
  230. *
  231. * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
  232. * is a critical path. If it is partially executed, it then
  233. * may happen that the job address is not yet in the DSA
  234. * and the next queue position points to the next JOB.
  235. */
  236. SCR_LOAD_ABS (dsa, 4),
  237. PADDR_B (startpos),
  238. SCR_LOAD_REL (temp, 4),
  239. 4,
  240. }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
  241. SCR_STORE_ABS (temp, 4),
  242. PADDR_B (startpos),
  243. SCR_LOAD_REL (dsa, 4),
  244. 0,
  245. }/*-------------------------< GETJOB_END >-----------------------*/,{
  246. SCR_LOAD_REL (temp, 4),
  247. 0,
  248. SCR_RETURN,
  249. 0,
  250. }/*-------------------------< SELECT >---------------------------*/,{
  251. /*
  252. * DSA contains the address of a scheduled
  253. * data structure.
  254. *
  255. * SCRATCHA contains the address of the start queue
  256. * entry which points to the next job.
  257. *
  258. * Set Initiator mode.
  259. *
  260. * (Target mode is left as an exercise for the reader)
  261. */
  262. #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  263. SCR_CLR (SCR_TRG),
  264. 0,
  265. #endif
  266. /*
  267. * And try to select this target.
  268. */
  269. SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
  270. PADDR_A (ungetjob),
  271. /*
  272. * Now there are 4 possibilities:
  273. *
  274. * (1) The chip loses arbitration.
  275. * This is ok, because it will try again,
  276. * when the bus becomes idle.
  277. * (But beware of the timeout function!)
  278. *
  279. * (2) The chip is reselected.
  280. * Then the script processor takes the jump
  281. * to the RESELECT label.
  282. *
  283. * (3) The chip wins arbitration.
  284. * Then it will execute SCRIPTS instruction until
  285. * the next instruction that checks SCSI phase.
  286. * Then will stop and wait for selection to be
  287. * complete or selection time-out to occur.
  288. *
  289. * After having won arbitration, the SCRIPTS
  290. * processor is able to execute instructions while
  291. * the SCSI core is performing SCSI selection.
  292. */
  293. /*
  294. * Initialize the status registers
  295. */
  296. SCR_LOAD_REL (scr0, 4),
  297. offsetof (struct sym_ccb, phys.head.status),
  298. /*
  299. * We may need help from CPU if the DMA segment
  300. * registers aren't up-to-date for this IO.
  301. * Patched with NOOP for chips that donnot
  302. * support DAC addressing.
  303. */
  304. #if SYM_CONF_DMA_ADDRESSING_MODE == 2
  305. }/*-------------------------< IS_DMAP_DIRTY >--------------------*/,{
  306. SCR_FROM_REG (HX_REG),
  307. 0,
  308. SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
  309. SIR_DMAP_DIRTY,
  310. #endif
  311. }/*-------------------------< WF_SEL_DONE >----------------------*/,{
  312. SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
  313. SIR_SEL_ATN_NO_MSG_OUT,
  314. }/*-------------------------< SEL_DONE >-------------------------*/,{
  315. /*
  316. * C1010-33 errata work-around.
  317. * Due to a race, the SCSI core may not have
  318. * loaded SCNTL3 on SEL_TBL instruction.
  319. * We reload it once phase is stable.
  320. * Patched with a NOOP for other chips.
  321. */
  322. SCR_LOAD_REL (scntl3, 1),
  323. offsetof(struct sym_dsb, select.sel_scntl3),
  324. }/*-------------------------< SEND_IDENT >-----------------------*/,{
  325. /*
  326. * Selection complete.
  327. * Send the IDENTIFY and possibly the TAG message
  328. * and negotiation message if present.
  329. */
  330. SCR_MOVE_TBL ^ SCR_MSG_OUT,
  331. offsetof (struct sym_dsb, smsg),
  332. }/*-------------------------< SELECT2 >--------------------------*/,{
  333. #ifdef SYM_CONF_IARB_SUPPORT
  334. /*
  335. * Set IMMEDIATE ARBITRATION if we have been given
  336. * a hint to do so. (Some job to do after this one).
  337. */
  338. SCR_FROM_REG (HF_REG),
  339. 0,
  340. SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
  341. 8,
  342. SCR_REG_REG (scntl1, SCR_OR, IARB),
  343. 0,
  344. #endif
  345. /*
  346. * Anticipate the COMMAND phase.
  347. * This is the PHASE we expect at this point.
  348. */
  349. SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
  350. PADDR_A (sel_no_cmd),
  351. }/*-------------------------< COMMAND >--------------------------*/,{
  352. /*
  353. * ... and send the command
  354. */
  355. SCR_MOVE_TBL ^ SCR_COMMAND,
  356. offsetof (struct sym_dsb, cmd),
  357. }/*-------------------------< DISPATCH >-------------------------*/,{
  358. /*
  359. * MSG_IN is the only phase that shall be
  360. * entered at least once for each (re)selection.
  361. * So we test it first.
  362. */
  363. SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
  364. PADDR_A (msg_in),
  365. SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
  366. PADDR_A (datao_phase),
  367. SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
  368. PADDR_A (datai_phase),
  369. SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
  370. PADDR_A (status),
  371. SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
  372. PADDR_A (command),
  373. SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
  374. PADDR_B (msg_out),
  375. /*
  376. * Discard as many illegal phases as
  377. * required and tell the C code about.
  378. */
  379. SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
  380. 16,
  381. SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
  382. HADDR_1 (scratch),
  383. SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
  384. -16,
  385. SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
  386. 16,
  387. SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
  388. HADDR_1 (scratch),
  389. SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
  390. -16,
  391. SCR_INT,
  392. SIR_BAD_PHASE,
  393. SCR_JUMP,
  394. PADDR_A (dispatch),
  395. }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
  396. /*
  397. * The target does not switch to command
  398. * phase after IDENTIFY has been sent.
  399. *
  400. * If it stays in MSG OUT phase send it
  401. * the IDENTIFY again.
  402. */
  403. SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
  404. PADDR_B (resend_ident),
  405. /*
  406. * If target does not switch to MSG IN phase
  407. * and we sent a negotiation, assert the
  408. * failure immediately.
  409. */
  410. SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
  411. PADDR_A (dispatch),
  412. SCR_FROM_REG (HS_REG),
  413. 0,
  414. SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
  415. SIR_NEGO_FAILED,
  416. /*
  417. * Jump to dispatcher.
  418. */
  419. SCR_JUMP,
  420. PADDR_A (dispatch),
  421. }/*-------------------------< INIT >-----------------------------*/,{
  422. /*
  423. * Wait for the SCSI RESET signal to be
  424. * inactive before restarting operations,
  425. * since the chip may hang on SEL_ATN
  426. * if SCSI RESET is active.
  427. */
  428. SCR_FROM_REG (sstat0),
  429. 0,
  430. SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
  431. -16,
  432. SCR_JUMP,
  433. PADDR_A (start),
  434. }/*-------------------------< CLRACK >---------------------------*/,{
  435. /*
  436. * Terminate possible pending message phase.
  437. */
  438. SCR_CLR (SCR_ACK),
  439. 0,
  440. SCR_JUMP,
  441. PADDR_A (dispatch),
  442. }/*-------------------------< DATAI_DONE >-----------------------*/,{
  443. /*
  444. * Save current pointer to LASTP.
  445. */
  446. SCR_STORE_REL (temp, 4),
  447. offsetof (struct sym_ccb, phys.head.lastp),
  448. /*
  449. * If the SWIDE is not full, jump to dispatcher.
  450. * We anticipate a STATUS phase.
  451. */
  452. SCR_FROM_REG (scntl2),
  453. 0,
  454. SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
  455. PADDR_A (datai_done_wsr),
  456. SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
  457. PADDR_A (status),
  458. SCR_JUMP,
  459. PADDR_A (dispatch),
  460. }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{
  461. /*
  462. * The SWIDE is full.
  463. * Clear this condition.
  464. */
  465. SCR_REG_REG (scntl2, SCR_OR, WSR),
  466. 0,
  467. /*
  468. * We are expecting an IGNORE RESIDUE message
  469. * from the device, otherwise we are in data
  470. * overrun condition. Check against MSG_IN phase.
  471. */
  472. SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
  473. SIR_SWIDE_OVERRUN,
  474. SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
  475. PADDR_A (dispatch),
  476. /*
  477. * We are in MSG_IN phase,
  478. * Read the first byte of the message.
  479. * If it is not an IGNORE RESIDUE message,
  480. * signal overrun and jump to message
  481. * processing.
  482. */
  483. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  484. HADDR_1 (msgin[0]),
  485. SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
  486. SIR_SWIDE_OVERRUN,
  487. SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
  488. PADDR_A (msg_in2),
  489. /*
  490. * We got the message we expected.
  491. * Read the 2nd byte, and jump to dispatcher.
  492. */
  493. SCR_CLR (SCR_ACK),
  494. 0,
  495. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  496. HADDR_1 (msgin[1]),
  497. SCR_CLR (SCR_ACK),
  498. 0,
  499. SCR_JUMP,
  500. PADDR_A (dispatch),
  501. }/*-------------------------< DATAO_DONE >-----------------------*/,{
  502. /*
  503. * Save current pointer to LASTP.
  504. */
  505. SCR_STORE_REL (temp, 4),
  506. offsetof (struct sym_ccb, phys.head.lastp),
  507. /*
  508. * If the SODL is not full jump to dispatcher.
  509. * We anticipate a STATUS phase.
  510. */
  511. SCR_FROM_REG (scntl2),
  512. 0,
  513. SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
  514. PADDR_A (datao_done_wss),
  515. SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
  516. PADDR_A (status),
  517. SCR_JUMP,
  518. PADDR_A (dispatch),
  519. }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{
  520. /*
  521. * The SODL is full, clear this condition.
  522. */
  523. SCR_REG_REG (scntl2, SCR_OR, WSS),
  524. 0,
  525. /*
  526. * And signal a DATA UNDERRUN condition
  527. * to the C code.
  528. */
  529. SCR_INT,
  530. SIR_SODL_UNDERRUN,
  531. SCR_JUMP,
  532. PADDR_A (dispatch),
  533. }/*-------------------------< DATAI_PHASE >----------------------*/,{
  534. /*
  535. * Jump to current pointer.
  536. */
  537. SCR_LOAD_REL (temp, 4),
  538. offsetof (struct sym_ccb, phys.head.lastp),
  539. SCR_RETURN,
  540. 0,
  541. }/*-------------------------< DATAO_PHASE >----------------------*/,{
  542. /*
  543. * C1010-66 errata work-around.
  544. * Extra clocks of data hold must be inserted
  545. * in DATA OUT phase on 33 MHz PCI BUS.
  546. * Patched with a NOOP for other chips.
  547. */
  548. SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)),
  549. 0,
  550. /*
  551. * Jump to current pointer.
  552. */
  553. SCR_LOAD_REL (temp, 4),
  554. offsetof (struct sym_ccb, phys.head.lastp),
  555. SCR_RETURN,
  556. 0,
  557. }/*-------------------------< MSG_IN >---------------------------*/,{
  558. /*
  559. * Get the first byte of the message.
  560. *
  561. * The script processor doesn't negate the
  562. * ACK signal after this transfer.
  563. */
  564. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  565. HADDR_1 (msgin[0]),
  566. }/*-------------------------< MSG_IN2 >--------------------------*/,{
  567. /*
  568. * Check first against 1 byte messages
  569. * that we handle from SCRIPTS.
  570. */
  571. SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
  572. PADDR_A (complete),
  573. SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
  574. PADDR_A (disconnect),
  575. SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
  576. PADDR_A (save_dp),
  577. SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
  578. PADDR_A (restore_dp),
  579. /*
  580. * We handle all other messages from the
  581. * C code, so no need to waste on-chip RAM
  582. * for those ones.
  583. */
  584. SCR_JUMP,
  585. PADDR_B (msg_in_etc),
  586. }/*-------------------------< STATUS >---------------------------*/,{
  587. /*
  588. * get the status
  589. */
  590. SCR_MOVE_ABS (1) ^ SCR_STATUS,
  591. HADDR_1 (scratch),
  592. #ifdef SYM_CONF_IARB_SUPPORT
  593. /*
  594. * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
  595. * since we may have to tamper the start queue from
  596. * the C code.
  597. */
  598. SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
  599. 8,
  600. SCR_REG_REG (scntl1, SCR_AND, ~IARB),
  601. 0,
  602. #endif
  603. /*
  604. * save status to scsi_status.
  605. * mark as complete.
  606. */
  607. SCR_TO_REG (SS_REG),
  608. 0,
  609. SCR_LOAD_REG (HS_REG, HS_COMPLETE),
  610. 0,
  611. /*
  612. * Anticipate the MESSAGE PHASE for
  613. * the TASK COMPLETE message.
  614. */
  615. SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
  616. PADDR_A (msg_in),
  617. SCR_JUMP,
  618. PADDR_A (dispatch),
  619. }/*-------------------------< COMPLETE >-------------------------*/,{
  620. /*
  621. * Complete message.
  622. *
  623. * When we terminate the cycle by clearing ACK,
  624. * the target may disconnect immediately.
  625. *
  626. * We don't want to be told of an "unexpected disconnect",
  627. * so we disable this feature.
  628. */
  629. SCR_REG_REG (scntl2, SCR_AND, 0x7f),
  630. 0,
  631. /*
  632. * Terminate cycle ...
  633. */
  634. SCR_CLR (SCR_ACK|SCR_ATN),
  635. 0,
  636. /*
  637. * ... and wait for the disconnect.
  638. */
  639. SCR_WAIT_DISC,
  640. 0,
  641. }/*-------------------------< COMPLETE2 >------------------------*/,{
  642. /*
  643. * Save host status.
  644. */
  645. SCR_STORE_REL (scr0, 4),
  646. offsetof (struct sym_ccb, phys.head.status),
  647. /*
  648. * Some bridges may reorder DMA writes to memory.
  649. * We donnot want the CPU to deal with completions
  650. * without all the posted write having been flushed
  651. * to memory. This DUMMY READ should flush posted
  652. * buffers prior to the CPU having to deal with
  653. * completions.
  654. */
  655. SCR_LOAD_REL (scr0, 4), /* DUMMY READ */
  656. offsetof (struct sym_ccb, phys.head.status),
  657. /*
  658. * If command resulted in not GOOD status,
  659. * call the C code if needed.
  660. */
  661. SCR_FROM_REG (SS_REG),
  662. 0,
  663. SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
  664. PADDR_B (bad_status),
  665. /*
  666. * If we performed an auto-sense, call
  667. * the C code to synchronyze task aborts
  668. * with UNIT ATTENTION conditions.
  669. */
  670. SCR_FROM_REG (HF_REG),
  671. 0,
  672. SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
  673. PADDR_A (complete_error),
  674. }/*-------------------------< DONE >-----------------------------*/,{
  675. /*
  676. * Copy the DSA to the DONE QUEUE and
  677. * signal completion to the host.
  678. * If we are interrupted between DONE
  679. * and DONE_END, we must reset, otherwise
  680. * the completed CCB may be lost.
  681. */
  682. SCR_STORE_ABS (dsa, 4),
  683. PADDR_B (scratch),
  684. SCR_LOAD_ABS (dsa, 4),
  685. PADDR_B (done_pos),
  686. SCR_LOAD_ABS (scratcha, 4),
  687. PADDR_B (scratch),
  688. SCR_STORE_REL (scratcha, 4),
  689. 0,
  690. /*
  691. * The instruction below reads the DONE QUEUE next
  692. * free position from memory.
  693. * In addition it ensures that all PCI posted writes
  694. * are flushed and so the DSA value of the done
  695. * CCB is visible by the CPU before INTFLY is raised.
  696. */
  697. SCR_LOAD_REL (scratcha, 4),
  698. 4,
  699. SCR_INT_FLY,
  700. 0,
  701. SCR_STORE_ABS (scratcha, 4),
  702. PADDR_B (done_pos),
  703. }/*-------------------------< DONE_END >-------------------------*/,{
  704. SCR_JUMP,
  705. PADDR_A (start),
  706. }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
  707. SCR_LOAD_ABS (scratcha, 4),
  708. PADDR_B (startpos),
  709. SCR_INT,
  710. SIR_COMPLETE_ERROR,
  711. }/*-------------------------< SAVE_DP >--------------------------*/,{
  712. /*
  713. * Clear ACK immediately.
  714. * No need to delay it.
  715. */
  716. SCR_CLR (SCR_ACK),
  717. 0,
  718. /*
  719. * Keep track we received a SAVE DP, so
  720. * we will switch to the other PM context
  721. * on the next PM since the DP may point
  722. * to the current PM context.
  723. */
  724. SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
  725. 0,
  726. /*
  727. * SAVE_DP message:
  728. * Copy LASTP to SAVEP.
  729. */
  730. SCR_LOAD_REL (scratcha, 4),
  731. offsetof (struct sym_ccb, phys.head.lastp),
  732. SCR_STORE_REL (scratcha, 4),
  733. offsetof (struct sym_ccb, phys.head.savep),
  734. /*
  735. * Anticipate the MESSAGE PHASE for
  736. * the DISCONNECT message.
  737. */
  738. SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
  739. PADDR_A (msg_in),
  740. SCR_JUMP,
  741. PADDR_A (dispatch),
  742. }/*-------------------------< RESTORE_DP >-----------------------*/,{
  743. /*
  744. * Clear ACK immediately.
  745. * No need to delay it.
  746. */
  747. SCR_CLR (SCR_ACK),
  748. 0,
  749. /*
  750. * Copy SAVEP to LASTP.
  751. */
  752. SCR_LOAD_REL (scratcha, 4),
  753. offsetof (struct sym_ccb, phys.head.savep),
  754. SCR_STORE_REL (scratcha, 4),
  755. offsetof (struct sym_ccb, phys.head.lastp),
  756. SCR_JUMP,
  757. PADDR_A (dispatch),
  758. }/*-------------------------< DISCONNECT >-----------------------*/,{
  759. /*
  760. * DISCONNECTing ...
  761. *
  762. * disable the "unexpected disconnect" feature,
  763. * and remove the ACK signal.
  764. */
  765. SCR_REG_REG (scntl2, SCR_AND, 0x7f),
  766. 0,
  767. SCR_CLR (SCR_ACK|SCR_ATN),
  768. 0,
  769. /*
  770. * Wait for the disconnect.
  771. */
  772. SCR_WAIT_DISC,
  773. 0,
  774. /*
  775. * Status is: DISCONNECTED.
  776. */
  777. SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
  778. 0,
  779. /*
  780. * Save host status.
  781. */
  782. SCR_STORE_REL (scr0, 4),
  783. offsetof (struct sym_ccb, phys.head.status),
  784. SCR_JUMP,
  785. PADDR_A (start),
  786. }/*-------------------------< IDLE >-----------------------------*/,{
  787. /*
  788. * Nothing to do?
  789. * Switch the LED off and wait for reselect.
  790. * Will be patched with a NO_OP if LED
  791. * not needed or not desired.
  792. */
  793. SCR_REG_REG (gpreg, SCR_OR, 0x01),
  794. 0,
  795. #ifdef SYM_CONF_IARB_SUPPORT
  796. SCR_JUMPR,
  797. 8,
  798. #endif
  799. }/*-------------------------< UNGETJOB >-------------------------*/,{
  800. #ifdef SYM_CONF_IARB_SUPPORT
  801. /*
  802. * Set IMMEDIATE ARBITRATION, for the next time.
  803. * This will give us better chance to win arbitration
  804. * for the job we just wanted to do.
  805. */
  806. SCR_REG_REG (scntl1, SCR_OR, IARB),
  807. 0,
  808. #endif
  809. /*
  810. * We are not able to restart the SCRIPTS if we are
  811. * interrupted and these instruction haven't been
  812. * all executed. BTW, this is very unlikely to
  813. * happen, but we check that from the C code.
  814. */
  815. SCR_LOAD_REG (dsa, 0xff),
  816. 0,
  817. SCR_STORE_ABS (scratcha, 4),
  818. PADDR_B (startpos),
  819. }/*-------------------------< RESELECT >-------------------------*/,{
  820. #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  821. /*
  822. * Make sure we are in initiator mode.
  823. */
  824. SCR_CLR (SCR_TRG),
  825. 0,
  826. #endif
  827. /*
  828. * Sleep waiting for a reselection.
  829. */
  830. SCR_WAIT_RESEL,
  831. PADDR_A(start),
  832. }/*-------------------------< RESELECTED >-----------------------*/,{
  833. /*
  834. * Switch the LED on.
  835. * Will be patched with a NO_OP if LED
  836. * not needed or not desired.
  837. */
  838. SCR_REG_REG (gpreg, SCR_AND, 0xfe),
  839. 0,
  840. /*
  841. * load the target id into the sdid
  842. */
  843. SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
  844. 0,
  845. SCR_TO_REG (sdid),
  846. 0,
  847. /*
  848. * Load the target control block address
  849. */
  850. SCR_LOAD_ABS (dsa, 4),
  851. PADDR_B (targtbl),
  852. SCR_SFBR_REG (dsa, SCR_SHL, 0),
  853. 0,
  854. SCR_REG_REG (dsa, SCR_SHL, 0),
  855. 0,
  856. SCR_REG_REG (dsa, SCR_AND, 0x3c),
  857. 0,
  858. SCR_LOAD_REL (dsa, 4),
  859. 0,
  860. /*
  861. * We expect MESSAGE IN phase.
  862. * If not, get help from the C code.
  863. */
  864. SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
  865. SIR_RESEL_NO_MSG_IN,
  866. /*
  867. * Load the legacy synchronous transfer registers.
  868. */
  869. SCR_LOAD_REL (scntl3, 1),
  870. offsetof(struct sym_tcb, head.wval),
  871. SCR_LOAD_REL (sxfer, 1),
  872. offsetof(struct sym_tcb, head.sval),
  873. }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{
  874. /*
  875. * The C1010 uses a new synchronous timing scheme.
  876. * Will be patched with a NO_OP if not a C1010.
  877. */
  878. SCR_LOAD_REL (scntl4, 1),
  879. offsetof(struct sym_tcb, head.uval),
  880. /*
  881. * Get the IDENTIFY message.
  882. */
  883. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  884. HADDR_1 (msgin),
  885. /*
  886. * If IDENTIFY LUN #0, use a faster path
  887. * to find the LCB structure.
  888. */
  889. SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
  890. PADDR_A (resel_lun0),
  891. /*
  892. * If message isn't an IDENTIFY,
  893. * tell the C code about.
  894. */
  895. SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
  896. SIR_RESEL_NO_IDENTIFY,
  897. /*
  898. * It is an IDENTIFY message,
  899. * Load the LUN control block address.
  900. */
  901. SCR_LOAD_REL (dsa, 4),
  902. offsetof(struct sym_tcb, head.luntbl_sa),
  903. SCR_SFBR_REG (dsa, SCR_SHL, 0),
  904. 0,
  905. SCR_REG_REG (dsa, SCR_SHL, 0),
  906. 0,
  907. SCR_REG_REG (dsa, SCR_AND, 0xfc),
  908. 0,
  909. SCR_LOAD_REL (dsa, 4),
  910. 0,
  911. SCR_JUMPR,
  912. 8,
  913. }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
  914. /*
  915. * LUN 0 special case (but usual one :))
  916. */
  917. SCR_LOAD_REL (dsa, 4),
  918. offsetof(struct sym_tcb, head.lun0_sa),
  919. /*
  920. * Jump indirectly to the reselect action for this LUN.
  921. */
  922. SCR_LOAD_REL (temp, 4),
  923. offsetof(struct sym_lcb, head.resel_sa),
  924. SCR_RETURN,
  925. 0,
  926. /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
  927. }/*-------------------------< RESEL_TAG >------------------------*/,{
  928. /*
  929. * ACK the IDENTIFY previously received.
  930. */
  931. SCR_CLR (SCR_ACK),
  932. 0,
  933. /*
  934. * It shall be a tagged command.
  935. * Read SIMPLE+TAG.
  936. * The C code will deal with errors.
  937. * Aggressive optimization, isn't it? :)
  938. */
  939. SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
  940. HADDR_1 (msgin),
  941. /*
  942. * Load the pointer to the tagged task
  943. * table for this LUN.
  944. */
  945. SCR_LOAD_REL (dsa, 4),
  946. offsetof(struct sym_lcb, head.itlq_tbl_sa),
  947. /*
  948. * The SIDL still contains the TAG value.
  949. * Aggressive optimization, isn't it? :):)
  950. */
  951. SCR_REG_SFBR (sidl, SCR_SHL, 0),
  952. 0,
  953. #if SYM_CONF_MAX_TASK*4 > 512
  954. SCR_JUMPR ^ IFFALSE (CARRYSET),
  955. 8,
  956. SCR_REG_REG (dsa1, SCR_OR, 2),
  957. 0,
  958. SCR_REG_REG (sfbr, SCR_SHL, 0),
  959. 0,
  960. SCR_JUMPR ^ IFFALSE (CARRYSET),
  961. 8,
  962. SCR_REG_REG (dsa1, SCR_OR, 1),
  963. 0,
  964. #elif SYM_CONF_MAX_TASK*4 > 256
  965. SCR_JUMPR ^ IFFALSE (CARRYSET),
  966. 8,
  967. SCR_REG_REG (dsa1, SCR_OR, 1),
  968. 0,
  969. #endif
  970. /*
  971. * Retrieve the DSA of this task.
  972. * JUMP indirectly to the restart point of the CCB.
  973. */
  974. SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
  975. 0,
  976. SCR_LOAD_REL (dsa, 4),
  977. 0,
  978. SCR_LOAD_REL (temp, 4),
  979. offsetof(struct sym_ccb, phys.head.go.restart),
  980. SCR_RETURN,
  981. 0,
  982. /* In normal situations we branch to RESEL_DSA */
  983. }/*-------------------------< RESEL_DSA >------------------------*/,{
  984. /*
  985. * ACK the IDENTIFY or TAG previously received.
  986. */
  987. SCR_CLR (SCR_ACK),
  988. 0,
  989. }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
  990. /*
  991. * Initialize the status registers
  992. */
  993. SCR_LOAD_REL (scr0, 4),
  994. offsetof (struct sym_ccb, phys.head.status),
  995. /*
  996. * Jump to dispatcher.
  997. */
  998. SCR_JUMP,
  999. PADDR_A (dispatch),
  1000. }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
  1001. /*
  1002. * Load the DSA with the unique ITL task.
  1003. */
  1004. SCR_LOAD_REL (dsa, 4),
  1005. offsetof(struct sym_lcb, head.itl_task_sa),
  1006. /*
  1007. * JUMP indirectly to the restart point of the CCB.
  1008. */
  1009. SCR_LOAD_REL (temp, 4),
  1010. offsetof(struct sym_ccb, phys.head.go.restart),
  1011. SCR_RETURN,
  1012. 0,
  1013. /* In normal situations we branch to RESEL_DSA */
  1014. }/*-------------------------< DATA_IN >--------------------------*/,{
  1015. /*
  1016. * Because the size depends on the
  1017. * #define SYM_CONF_MAX_SG parameter,
  1018. * it is filled in at runtime.
  1019. *
  1020. * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
  1021. * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
  1022. * || offsetof (struct sym_dsb, data[ i]),
  1023. * ##==========================================
  1024. */
  1025. 0
  1026. }/*-------------------------< DATA_IN2 >-------------------------*/,{
  1027. SCR_CALL,
  1028. PADDR_A (datai_done),
  1029. SCR_JUMP,
  1030. PADDR_B (data_ovrun),
  1031. }/*-------------------------< DATA_OUT >-------------------------*/,{
  1032. /*
  1033. * Because the size depends on the
  1034. * #define SYM_CONF_MAX_SG parameter,
  1035. * it is filled in at runtime.
  1036. *
  1037. * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
  1038. * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
  1039. * || offsetof (struct sym_dsb, data[ i]),
  1040. * ##==========================================
  1041. */
  1042. 0
  1043. }/*-------------------------< DATA_OUT2 >------------------------*/,{
  1044. SCR_CALL,
  1045. PADDR_A (datao_done),
  1046. SCR_JUMP,
  1047. PADDR_B (data_ovrun),
  1048. }/*-------------------------< PM0_DATA >-------------------------*/,{
  1049. /*
  1050. * Read our host flags to SFBR, so we will be able
  1051. * to check against the data direction we expect.
  1052. */
  1053. SCR_FROM_REG (HF_REG),
  1054. 0,
  1055. /*
  1056. * Check against actual DATA PHASE.
  1057. */
  1058. SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
  1059. PADDR_A (pm0_data_out),
  1060. /*
  1061. * Actual phase is DATA IN.
  1062. * Check against expected direction.
  1063. */
  1064. SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
  1065. PADDR_B (data_ovrun),
  1066. /*
  1067. * Keep track we are moving data from the
  1068. * PM0 DATA mini-script.
  1069. */
  1070. SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
  1071. 0,
  1072. /*
  1073. * Move the data to memory.
  1074. */
  1075. SCR_CHMOV_TBL ^ SCR_DATA_IN,
  1076. offsetof (struct sym_ccb, phys.pm0.sg),
  1077. SCR_JUMP,
  1078. PADDR_A (pm0_data_end),
  1079. }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
  1080. /*
  1081. * Actual phase is DATA OUT.
  1082. * Check against expected direction.
  1083. */
  1084. SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
  1085. PADDR_B (data_ovrun),
  1086. /*
  1087. * Keep track we are moving data from the
  1088. * PM0 DATA mini-script.
  1089. */
  1090. SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
  1091. 0,
  1092. /*
  1093. * Move the data from memory.
  1094. */
  1095. SCR_CHMOV_TBL ^ SCR_DATA_OUT,
  1096. offsetof (struct sym_ccb, phys.pm0.sg),
  1097. }/*-------------------------< PM0_DATA_END >---------------------*/,{
  1098. /*
  1099. * Clear the flag that told we were moving
  1100. * data from the PM0 DATA mini-script.
  1101. */
  1102. SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
  1103. 0,
  1104. /*
  1105. * Return to the previous DATA script which
  1106. * is guaranteed by design (if no bug) to be
  1107. * the main DATA script for this transfer.
  1108. */
  1109. SCR_LOAD_REL (temp, 4),
  1110. offsetof (struct sym_ccb, phys.pm0.ret),
  1111. SCR_RETURN,
  1112. 0,
  1113. }/*-------------------------< PM1_DATA >-------------------------*/,{
  1114. /*
  1115. * Read our host flags to SFBR, so we will be able
  1116. * to check against the data direction we expect.
  1117. */
  1118. SCR_FROM_REG (HF_REG),
  1119. 0,
  1120. /*
  1121. * Check against actual DATA PHASE.
  1122. */
  1123. SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
  1124. PADDR_A (pm1_data_out),
  1125. /*
  1126. * Actual phase is DATA IN.
  1127. * Check against expected direction.
  1128. */
  1129. SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
  1130. PADDR_B (data_ovrun),
  1131. /*
  1132. * Keep track we are moving data from the
  1133. * PM1 DATA mini-script.
  1134. */
  1135. SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
  1136. 0,
  1137. /*
  1138. * Move the data to memory.
  1139. */
  1140. SCR_CHMOV_TBL ^ SCR_DATA_IN,
  1141. offsetof (struct sym_ccb, phys.pm1.sg),
  1142. SCR_JUMP,
  1143. PADDR_A (pm1_data_end),
  1144. }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
  1145. /*
  1146. * Actual phase is DATA OUT.
  1147. * Check against expected direction.
  1148. */
  1149. SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
  1150. PADDR_B (data_ovrun),
  1151. /*
  1152. * Keep track we are moving data from the
  1153. * PM1 DATA mini-script.
  1154. */
  1155. SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
  1156. 0,
  1157. /*
  1158. * Move the data from memory.
  1159. */
  1160. SCR_CHMOV_TBL ^ SCR_DATA_OUT,
  1161. offsetof (struct sym_ccb, phys.pm1.sg),
  1162. }/*-------------------------< PM1_DATA_END >---------------------*/,{
  1163. /*
  1164. * Clear the flag that told we were moving
  1165. * data from the PM1 DATA mini-script.
  1166. */
  1167. SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
  1168. 0,
  1169. /*
  1170. * Return to the previous DATA script which
  1171. * is guaranteed by design (if no bug) to be
  1172. * the main DATA script for this transfer.
  1173. */
  1174. SCR_LOAD_REL (temp, 4),
  1175. offsetof (struct sym_ccb, phys.pm1.ret),
  1176. SCR_RETURN,
  1177. 0,
  1178. }/*-------------------------<>-----------------------------------*/
  1179. };
  1180. static struct SYM_FWB_SCR SYM_FWB_SCR = {
  1181. /*--------------------------< START64 >--------------------------*/ {
  1182. /*
  1183. * SCRIPT entry point for the 895A, 896 and 1010.
  1184. * For now, there is no specific stuff for those
  1185. * chips at this point, but this may come.
  1186. */
  1187. SCR_JUMP,
  1188. PADDR_A (init),
  1189. }/*-------------------------< NO_DATA >--------------------------*/,{
  1190. SCR_JUMP,
  1191. PADDR_B (data_ovrun),
  1192. }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
  1193. /*
  1194. * We are jumped here by the C code, if we have
  1195. * some target to reset or some disconnected
  1196. * job to abort. Since error recovery is a serious
  1197. * busyness, we will really reset the SCSI BUS, if
  1198. * case of a SCSI interrupt occurring in this path.
  1199. */
  1200. #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  1201. /*
  1202. * Set initiator mode.
  1203. */
  1204. SCR_CLR (SCR_TRG),
  1205. 0,
  1206. #endif
  1207. /*
  1208. * And try to select this target.
  1209. */
  1210. SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
  1211. PADDR_A (reselect),
  1212. /*
  1213. * Wait for the selection to complete or
  1214. * the selection to time out.
  1215. */
  1216. SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
  1217. -8,
  1218. /*
  1219. * Call the C code.
  1220. */
  1221. SCR_INT,
  1222. SIR_TARGET_SELECTED,
  1223. /*
  1224. * The C code should let us continue here.
  1225. * Send the 'kiss of death' message.
  1226. * We expect an immediate disconnect once
  1227. * the target has eaten the message.
  1228. */
  1229. SCR_REG_REG (scntl2, SCR_AND, 0x7f),
  1230. 0,
  1231. SCR_MOVE_TBL ^ SCR_MSG_OUT,
  1232. offsetof (struct sym_hcb, abrt_tbl),
  1233. SCR_CLR (SCR_ACK|SCR_ATN),
  1234. 0,
  1235. SCR_WAIT_DISC,
  1236. 0,
  1237. /*
  1238. * Tell the C code that we are done.
  1239. */
  1240. SCR_INT,
  1241. SIR_ABORT_SENT,
  1242. }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
  1243. /*
  1244. * Jump at scheduler.
  1245. */
  1246. SCR_JUMP,
  1247. PADDR_A (start),
  1248. }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
  1249. /*
  1250. * If it is an EXTENDED (variable size message)
  1251. * Handle it.
  1252. */
  1253. SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
  1254. PADDR_B (msg_extended),
  1255. /*
  1256. * Let the C code handle any other
  1257. * 1 byte message.
  1258. */
  1259. SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
  1260. PADDR_B (msg_received),
  1261. SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
  1262. PADDR_B (msg_received),
  1263. /*
  1264. * We donnot handle 2 bytes messages from SCRIPTS.
  1265. * So, let the C code deal with these ones too.
  1266. */
  1267. SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
  1268. PADDR_B (msg_weird_seen),
  1269. SCR_CLR (SCR_ACK),
  1270. 0,
  1271. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  1272. HADDR_1 (msgin[1]),
  1273. }/*-------------------------< MSG_RECEIVED >---------------------*/,{
  1274. SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
  1275. 0,
  1276. SCR_INT,
  1277. SIR_MSG_RECEIVED,
  1278. }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
  1279. SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */
  1280. 0,
  1281. SCR_INT,
  1282. SIR_MSG_WEIRD,
  1283. }/*-------------------------< MSG_EXTENDED >---------------------*/,{
  1284. /*
  1285. * Clear ACK and get the next byte
  1286. * assumed to be the message length.
  1287. */
  1288. SCR_CLR (SCR_ACK),
  1289. 0,
  1290. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  1291. HADDR_1 (msgin[1]),
  1292. /*
  1293. * Try to catch some unlikely situations as 0 length
  1294. * or too large the length.
  1295. */
  1296. SCR_JUMP ^ IFTRUE (DATA (0)),
  1297. PADDR_B (msg_weird_seen),
  1298. SCR_TO_REG (scratcha),
  1299. 0,
  1300. SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
  1301. 0,
  1302. SCR_JUMP ^ IFTRUE (CARRYSET),
  1303. PADDR_B (msg_weird_seen),
  1304. /*
  1305. * We donnot handle extended messages from SCRIPTS.
  1306. * Read the amount of data corresponding to the
  1307. * message length and call the C code.
  1308. */
  1309. SCR_STORE_REL (scratcha, 1),
  1310. offsetof (struct sym_dsb, smsg_ext.size),
  1311. SCR_CLR (SCR_ACK),
  1312. 0,
  1313. SCR_MOVE_TBL ^ SCR_MSG_IN,
  1314. offsetof (struct sym_dsb, smsg_ext),
  1315. SCR_JUMP,
  1316. PADDR_B (msg_received),
  1317. }/*-------------------------< MSG_BAD >--------------------------*/,{
  1318. /*
  1319. * unimplemented message - reject it.
  1320. */
  1321. SCR_INT,
  1322. SIR_REJECT_TO_SEND,
  1323. SCR_SET (SCR_ATN),
  1324. 0,
  1325. SCR_JUMP,
  1326. PADDR_A (clrack),
  1327. }/*-------------------------< MSG_WEIRD >------------------------*/,{
  1328. /*
  1329. * weird message received
  1330. * ignore all MSG IN phases and reject it.
  1331. */
  1332. SCR_INT,
  1333. SIR_REJECT_TO_SEND,
  1334. SCR_SET (SCR_ATN),
  1335. 0,
  1336. }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
  1337. SCR_CLR (SCR_ACK),
  1338. 0,
  1339. SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
  1340. PADDR_A (dispatch),
  1341. SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
  1342. HADDR_1 (scratch),
  1343. SCR_JUMP,
  1344. PADDR_B (msg_weird1),
  1345. }/*-------------------------< WDTR_RESP >------------------------*/,{
  1346. /*
  1347. * let the target fetch our answer.
  1348. */
  1349. SCR_SET (SCR_ATN),
  1350. 0,
  1351. SCR_CLR (SCR_ACK),
  1352. 0,
  1353. SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
  1354. PADDR_B (nego_bad_phase),
  1355. }/*-------------------------< SEND_WDTR >------------------------*/,{
  1356. /*
  1357. * Send the M_X_WIDE_REQ
  1358. */
  1359. SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
  1360. HADDR_1 (msgout),
  1361. SCR_JUMP,
  1362. PADDR_B (msg_out_done),
  1363. }/*-------------------------< SDTR_RESP >------------------------*/,{
  1364. /*
  1365. * let the target fetch our answer.
  1366. */
  1367. SCR_SET (SCR_ATN),
  1368. 0,
  1369. SCR_CLR (SCR_ACK),
  1370. 0,
  1371. SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
  1372. PADDR_B (nego_bad_phase),
  1373. }/*-------------------------< SEND_SDTR >------------------------*/,{
  1374. /*
  1375. * Send the M_X_SYNC_REQ
  1376. */
  1377. SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
  1378. HADDR_1 (msgout),
  1379. SCR_JUMP,
  1380. PADDR_B (msg_out_done),
  1381. }/*-------------------------< PPR_RESP >-------------------------*/,{
  1382. /*
  1383. * let the target fetch our answer.
  1384. */
  1385. SCR_SET (SCR_ATN),
  1386. 0,
  1387. SCR_CLR (SCR_ACK),
  1388. 0,
  1389. SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
  1390. PADDR_B (nego_bad_phase),
  1391. }/*-------------------------< SEND_PPR >-------------------------*/,{
  1392. /*
  1393. * Send the M_X_PPR_REQ
  1394. */
  1395. SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
  1396. HADDR_1 (msgout),
  1397. SCR_JUMP,
  1398. PADDR_B (msg_out_done),
  1399. }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
  1400. SCR_INT,
  1401. SIR_NEGO_PROTO,
  1402. SCR_JUMP,
  1403. PADDR_A (dispatch),
  1404. }/*-------------------------< MSG_OUT >--------------------------*/,{
  1405. /*
  1406. * The target requests a message.
  1407. * We donnot send messages that may
  1408. * require the device to go to bus free.
  1409. */
  1410. SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
  1411. HADDR_1 (msgout),
  1412. /*
  1413. * ... wait for the next phase
  1414. * if it's a message out, send it again, ...
  1415. */
  1416. SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
  1417. PADDR_B (msg_out),
  1418. }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
  1419. /*
  1420. * Let the C code be aware of the
  1421. * sent message and clear the message.
  1422. */
  1423. SCR_INT,
  1424. SIR_MSG_OUT_DONE,
  1425. /*
  1426. * ... and process the next phase
  1427. */
  1428. SCR_JUMP,
  1429. PADDR_A (dispatch),
  1430. }/*-------------------------< DATA_OVRUN >-----------------------*/,{
  1431. /*
  1432. * Use scratcha to count the extra bytes.
  1433. */
  1434. SCR_LOAD_ABS (scratcha, 4),
  1435. PADDR_B (zero),
  1436. }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
  1437. /*
  1438. * The target may want to transfer too much data.
  1439. *
  1440. * If phase is DATA OUT write 1 byte and count it.
  1441. */
  1442. SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
  1443. 16,
  1444. SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
  1445. HADDR_1 (scratch),
  1446. SCR_JUMP,
  1447. PADDR_B (data_ovrun2),
  1448. /*
  1449. * If WSR is set, clear this condition, and
  1450. * count this byte.
  1451. */
  1452. SCR_FROM_REG (scntl2),
  1453. 0,
  1454. SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
  1455. 16,
  1456. SCR_REG_REG (scntl2, SCR_OR, WSR),
  1457. 0,
  1458. SCR_JUMP,
  1459. PADDR_B (data_ovrun2),
  1460. /*
  1461. * Finally check against DATA IN phase.
  1462. * Signal data overrun to the C code
  1463. * and jump to dispatcher if not so.
  1464. * Read 1 byte otherwise and count it.
  1465. */
  1466. SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
  1467. 16,
  1468. SCR_INT,
  1469. SIR_DATA_OVERRUN,
  1470. SCR_JUMP,
  1471. PADDR_A (dispatch),
  1472. SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
  1473. HADDR_1 (scratch),
  1474. }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
  1475. /*
  1476. * Count this byte.
  1477. * This will allow to return a negative
  1478. * residual to user.
  1479. */
  1480. SCR_REG_REG (scratcha, SCR_ADD, 0x01),
  1481. 0,
  1482. SCR_REG_REG (scratcha1, SCR_ADDC, 0),
  1483. 0,
  1484. SCR_REG_REG (scratcha2, SCR_ADDC, 0),
  1485. 0,
  1486. /*
  1487. * .. and repeat as required.
  1488. */
  1489. SCR_JUMP,
  1490. PADDR_B (data_ovrun1),
  1491. }/*-------------------------< ABORT_RESEL >----------------------*/,{
  1492. SCR_SET (SCR_ATN),
  1493. 0,
  1494. SCR_CLR (SCR_ACK),
  1495. 0,
  1496. /*
  1497. * send the abort/abortag/reset message
  1498. * we expect an immediate disconnect
  1499. */
  1500. SCR_REG_REG (scntl2, SCR_AND, 0x7f),
  1501. 0,
  1502. SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
  1503. HADDR_1 (msgout),
  1504. SCR_CLR (SCR_ACK|SCR_ATN),
  1505. 0,
  1506. SCR_WAIT_DISC,
  1507. 0,
  1508. SCR_INT,
  1509. SIR_RESEL_ABORTED,
  1510. SCR_JUMP,
  1511. PADDR_A (start),
  1512. }/*-------------------------< RESEND_IDENT >---------------------*/,{
  1513. /*
  1514. * The target stays in MSG OUT phase after having acked
  1515. * Identify [+ Tag [+ Extended message ]]. Targets shall
  1516. * behave this way on parity error.
  1517. * We must send it again all the messages.
  1518. */
  1519. SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
  1520. 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
  1521. SCR_JUMP,
  1522. PADDR_A (send_ident),
  1523. }/*-------------------------< IDENT_BREAK >----------------------*/,{
  1524. SCR_CLR (SCR_ATN),
  1525. 0,
  1526. SCR_JUMP,
  1527. PADDR_A (select2),
  1528. }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
  1529. SCR_SET (SCR_ATN),
  1530. 0,
  1531. SCR_JUMP,
  1532. PADDR_A (select2),
  1533. }/*-------------------------< SDATA_IN >-------------------------*/,{
  1534. SCR_CHMOV_TBL ^ SCR_DATA_IN,
  1535. offsetof (struct sym_dsb, sense),
  1536. SCR_CALL,
  1537. PADDR_A (datai_done),
  1538. SCR_JUMP,
  1539. PADDR_B (data_ovrun),
  1540. }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
  1541. /*
  1542. * Message is an IDENTIFY, but lun is unknown.
  1543. * Signal problem to C code for logging the event.
  1544. * Send a M_ABORT to clear all pending tasks.
  1545. */
  1546. SCR_INT,
  1547. SIR_RESEL_BAD_LUN,
  1548. SCR_JUMP,
  1549. PADDR_B (abort_resel),
  1550. }/*-------------------------< BAD_I_T_L >------------------------*/,{
  1551. /*
  1552. * We donnot have a task for that I_T_L.
  1553. * Signal problem to C code for logging the event.
  1554. * Send a M_ABORT message.
  1555. */
  1556. SCR_INT,
  1557. SIR_RESEL_BAD_I_T_L,
  1558. SCR_JUMP,
  1559. PADDR_B (abort_resel),
  1560. }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
  1561. /*
  1562. * We donnot have a task that matches the tag.
  1563. * Signal problem to C code for logging the event.
  1564. * Send a M_ABORTTAG message.
  1565. */
  1566. SCR_INT,
  1567. SIR_RESEL_BAD_I_T_L_Q,
  1568. SCR_JUMP,
  1569. PADDR_B (abort_resel),
  1570. }/*-------------------------< BAD_STATUS >-----------------------*/,{
  1571. /*
  1572. * Anything different from INTERMEDIATE
  1573. * CONDITION MET should be a bad SCSI status,
  1574. * given that GOOD status has already been tested.
  1575. * Call the C code.
  1576. */
  1577. SCR_LOAD_ABS (scratcha, 4),
  1578. PADDR_B (startpos),
  1579. SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
  1580. SIR_BAD_SCSI_STATUS,
  1581. SCR_RETURN,
  1582. 0,
  1583. }/*-------------------------< PM_HANDLE >------------------------*/,{
  1584. /*
  1585. * Phase mismatch handling.
  1586. *
  1587. * Since we have to deal with 2 SCSI data pointers
  1588. * (current and saved), we need at least 2 contexts.
  1589. * Each context (pm0 and pm1) has a saved area, a
  1590. * SAVE mini-script and a DATA phase mini-script.
  1591. */
  1592. /*
  1593. * Get the PM handling flags.
  1594. */
  1595. SCR_FROM_REG (HF_REG),
  1596. 0,
  1597. /*
  1598. * If no flags (1rst PM for example), avoid
  1599. * all the below heavy flags testing.
  1600. * This makes the normal case a bit faster.
  1601. */
  1602. SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))),
  1603. PADDR_B (pm_handle1),
  1604. /*
  1605. * If we received a SAVE DP, switch to the
  1606. * other PM context since the savep may point
  1607. * to the current PM context.
  1608. */
  1609. SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)),
  1610. 8,
  1611. SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM),
  1612. 0,
  1613. /*
  1614. * If we have been interrupt in a PM DATA mini-script,
  1615. * we take the return address from the corresponding
  1616. * saved area.
  1617. * This ensure the return address always points to the
  1618. * main DATA script for this transfer.
  1619. */
  1620. SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))),
  1621. PADDR_B (pm_handle1),
  1622. SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)),
  1623. 16,
  1624. SCR_LOAD_REL (ia, 4),
  1625. offsetof(struct sym_ccb, phys.pm0.ret),
  1626. SCR_JUMP,
  1627. PADDR_B (pm_save),
  1628. SCR_LOAD_REL (ia, 4),
  1629. offsetof(struct sym_ccb, phys.pm1.ret),
  1630. SCR_JUMP,
  1631. PADDR_B (pm_save),
  1632. }/*-------------------------< PM_HANDLE1 >-----------------------*/,{
  1633. /*
  1634. * Normal case.
  1635. * Update the return address so that it
  1636. * will point after the interrupted MOVE.
  1637. */
  1638. SCR_REG_REG (ia, SCR_ADD, 8),
  1639. 0,
  1640. SCR_REG_REG (ia1, SCR_ADDC, 0),
  1641. 0,
  1642. }/*-------------------------< PM_SAVE >--------------------------*/,{
  1643. /*
  1644. * Clear all the flags that told us if we were
  1645. * interrupted in a PM DATA mini-script and/or
  1646. * we received a SAVE DP.
  1647. */
  1648. SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))),
  1649. 0,
  1650. /*
  1651. * Choose the current PM context.
  1652. */
  1653. SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)),
  1654. PADDR_B (pm1_save),
  1655. }/*-------------------------< PM0_SAVE >-------------------------*/,{
  1656. SCR_STORE_REL (ia, 4),
  1657. offsetof(struct sym_ccb, phys.pm0.ret),
  1658. /*
  1659. * If WSR bit is set, either UA and RBC may
  1660. * have to be changed whether the device wants
  1661. * to ignore this residue or not.
  1662. */
  1663. SCR_FROM_REG (scntl2),
  1664. 0,
  1665. SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
  1666. PADDR_B (pm_wsr_handle),
  1667. /*
  1668. * Save the remaining byte count, the updated
  1669. * address and the return address.
  1670. */
  1671. SCR_STORE_REL (rbc, 4),
  1672. offsetof(struct sym_ccb, phys.pm0.sg.size),
  1673. SCR_STORE_REL (ua, 4),
  1674. offsetof(struct sym_ccb, phys.pm0.sg.addr),
  1675. /*
  1676. * Set the current pointer at the PM0 DATA mini-script.
  1677. */
  1678. SCR_LOAD_ABS (ia, 4),
  1679. PADDR_B (pm0_data_addr),
  1680. }/*-------------------------< PM_SAVE_END >----------------------*/,{
  1681. SCR_STORE_REL (ia, 4),
  1682. offsetof(struct sym_ccb, phys.head.lastp),
  1683. SCR_JUMP,
  1684. PADDR_A (dispatch),
  1685. }/*-------------------------< PM1_SAVE >-------------------------*/,{
  1686. SCR_STORE_REL (ia, 4),
  1687. offsetof(struct sym_ccb, phys.pm1.ret),
  1688. /*
  1689. * If WSR bit is set, either UA and RBC may
  1690. * have to be changed whether the device wants
  1691. * to ignore this residue or not.
  1692. */
  1693. SCR_FROM_REG (scntl2),
  1694. 0,
  1695. SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
  1696. PADDR_B (pm_wsr_handle),
  1697. /*
  1698. * Save the remaining byte count, the updated
  1699. * address and the return address.
  1700. */
  1701. SCR_STORE_REL (rbc, 4),
  1702. offsetof(struct sym_ccb, phys.pm1.sg.size),
  1703. SCR_STORE_REL (ua, 4),
  1704. offsetof(struct sym_ccb, phys.pm1.sg.addr),
  1705. /*
  1706. * Set the current pointer at the PM1 DATA mini-script.
  1707. */
  1708. SCR_LOAD_ABS (ia, 4),
  1709. PADDR_B (pm1_data_addr),
  1710. SCR_JUMP,
  1711. PADDR_B (pm_save_end),
  1712. }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{
  1713. /*
  1714. * Phase mismatch handling from SCRIPT with WSR set.
  1715. * Such a condition can occur if the chip wants to
  1716. * execute a CHMOV(size > 1) when the WSR bit is
  1717. * set and the target changes PHASE.
  1718. *
  1719. * We must move the residual byte to memory.
  1720. *
  1721. * UA contains bit 0..31 of the address to
  1722. * move the residual byte.
  1723. * Move it to the table indirect.
  1724. */
  1725. SCR_STORE_REL (ua, 4),
  1726. offsetof (struct sym_ccb, phys.wresid.addr),
  1727. /*
  1728. * Increment UA (move address to next position).
  1729. */
  1730. SCR_REG_REG (ua, SCR_ADD, 1),
  1731. 0,
  1732. SCR_REG_REG (ua1, SCR_ADDC, 0),
  1733. 0,
  1734. SCR_REG_REG (ua2, SCR_ADDC, 0),
  1735. 0,
  1736. SCR_REG_REG (ua3, SCR_ADDC, 0),
  1737. 0,
  1738. /*
  1739. * Compute SCRATCHA as:
  1740. * - size to transfer = 1 byte.
  1741. * - bit 24..31 = high address bit [32...39].
  1742. */
  1743. SCR_LOAD_ABS (scratcha, 4),
  1744. PADDR_B (zero),
  1745. SCR_REG_REG (scratcha, SCR_OR, 1),
  1746. 0,
  1747. SCR_FROM_REG (rbc3),
  1748. 0,
  1749. SCR_TO_REG (scratcha3),
  1750. 0,
  1751. /*
  1752. * Move this value to the table indirect.
  1753. */
  1754. SCR_STORE_REL (scratcha, 4),
  1755. offsetof (struct sym_ccb, phys.wresid.size),
  1756. /*
  1757. * Wait for a valid phase.
  1758. * While testing with bogus QUANTUM drives, the C1010
  1759. * sometimes raised a spurious phase mismatch with
  1760. * WSR and the CHMOV(1) triggered another PM.
  1761. * Waiting explicitly for the PHASE seemed to avoid
  1762. * the nested phase mismatch. Btw, this didn't happen
  1763. * using my IBM drives.
  1764. */
  1765. SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)),
  1766. 0,
  1767. /*
  1768. * Perform the move of the residual byte.
  1769. */
  1770. SCR_CHMOV_TBL ^ SCR_DATA_IN,
  1771. offsetof (struct sym_ccb, phys.wresid),
  1772. /*
  1773. * We can now handle the phase mismatch with UA fixed.
  1774. * RBC[0..23]=0 is a special case that does not require
  1775. * a PM context. The C code also checks against this.
  1776. */
  1777. SCR_FROM_REG (rbc),
  1778. 0,
  1779. SCR_RETURN ^ IFFALSE (DATA (0)),
  1780. 0,
  1781. SCR_FROM_REG (rbc1),
  1782. 0,
  1783. SCR_RETURN ^ IFFALSE (DATA (0)),
  1784. 0,
  1785. SCR_FROM_REG (rbc2),
  1786. 0,
  1787. SCR_RETURN ^ IFFALSE (DATA (0)),
  1788. 0,
  1789. /*
  1790. * RBC[0..23]=0.
  1791. * Not only we donnot need a PM context, but this would
  1792. * lead to a bogus CHMOV(0). This condition means that
  1793. * the residual was the last byte to move from this CHMOV.
  1794. * So, we just have to move the current data script pointer
  1795. * (i.e. TEMP) to the SCRIPTS address following the
  1796. * interrupted CHMOV and jump to dispatcher.
  1797. * IA contains the data pointer to save.
  1798. */
  1799. SCR_JUMP,
  1800. PADDR_B (pm_save_end),
  1801. }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
  1802. /*
  1803. * Helper for the C code when WSR bit is set.
  1804. * Perform the move of the residual byte.
  1805. */
  1806. SCR_CHMOV_TBL ^ SCR_DATA_IN,
  1807. offsetof (struct sym_ccb, phys.wresid),
  1808. SCR_JUMP,
  1809. PADDR_A (dispatch),
  1810. }/*-------------------------< ZERO >-----------------------------*/,{
  1811. SCR_DATA_ZERO,
  1812. }/*-------------------------< SCRATCH >--------------------------*/,{
  1813. SCR_DATA_ZERO,
  1814. }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{
  1815. SCR_DATA_ZERO,
  1816. }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{
  1817. SCR_DATA_ZERO,
  1818. }/*-------------------------< DONE_POS >-------------------------*/,{
  1819. SCR_DATA_ZERO,
  1820. }/*-------------------------< STARTPOS >-------------------------*/,{
  1821. SCR_DATA_ZERO,
  1822. }/*-------------------------< TARGTBL >--------------------------*/,{
  1823. SCR_DATA_ZERO,
  1824. }/*-------------------------<>-----------------------------------*/
  1825. };
  1826. static struct SYM_FWZ_SCR SYM_FWZ_SCR = {
  1827. /*-------------------------< SNOOPTEST >------------------------*/{
  1828. /*
  1829. * Read the variable from memory.
  1830. */
  1831. SCR_LOAD_REL (scratcha, 4),
  1832. offsetof(struct sym_hcb, scratch),
  1833. /*
  1834. * Write the variable to memory.
  1835. */
  1836. SCR_STORE_REL (temp, 4),
  1837. offsetof(struct sym_hcb, scratch),
  1838. /*
  1839. * Read back the variable from memory.
  1840. */
  1841. SCR_LOAD_REL (temp, 4),
  1842. offsetof(struct sym_hcb, scratch),
  1843. }/*-------------------------< SNOOPEND >-------------------------*/,{
  1844. /*
  1845. * And stop.
  1846. */
  1847. SCR_INT,
  1848. 99,
  1849. }/*-------------------------<>-----------------------------------*/
  1850. };