sun3_scsi.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
  4. *
  5. * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
  6. *
  7. * VME support added by Sam Creasey
  8. *
  9. * TODO: modify this driver to support multiple Sun3 SCSI VME boards
  10. *
  11. * Adapted from mac_scsinew.c:
  12. */
  13. /*
  14. * Generic Macintosh NCR5380 driver
  15. *
  16. * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
  17. *
  18. * derived in part from:
  19. */
  20. /*
  21. * Generic Generic NCR5380 driver
  22. *
  23. * Copyright 1995, Russell King
  24. */
  25. #include <linux/types.h>
  26. #include <linux/delay.h>
  27. #include <linux/module.h>
  28. #include <linux/ioport.h>
  29. #include <linux/init.h>
  30. #include <linux/blkdev.h>
  31. #include <linux/platform_device.h>
  32. #include <asm/io.h>
  33. #include <asm/dvma.h>
  34. #include <scsi/scsi_host.h>
  35. /* minimum number of bytes to do dma on */
  36. #define DMA_MIN_SIZE 129
  37. /* Definitions for the core NCR5380 driver. */
  38. #define NCR5380_implementation_fields /* none */
  39. #define NCR5380_read(reg) in_8(hostdata->io + (reg))
  40. #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
  41. #define NCR5380_queue_command sun3scsi_queue_command
  42. #define NCR5380_host_reset sun3scsi_host_reset
  43. #define NCR5380_abort sun3scsi_abort
  44. #define NCR5380_info sun3scsi_info
  45. #define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
  46. #define NCR5380_dma_recv_setup sun3scsi_dma_count
  47. #define NCR5380_dma_send_setup sun3scsi_dma_count
  48. #define NCR5380_dma_residual sun3scsi_dma_residual
  49. #include "NCR5380.h"
  50. /* dma regs start at regbase + 8, directly after the NCR regs */
  51. struct sun3_dma_regs {
  52. unsigned short dma_addr_hi; /* vme only */
  53. unsigned short dma_addr_lo; /* vme only */
  54. unsigned short dma_count_hi; /* vme only */
  55. unsigned short dma_count_lo; /* vme only */
  56. unsigned short udc_data; /* udc dma data reg (obio only) */
  57. unsigned short udc_addr; /* uda dma addr reg (obio only) */
  58. unsigned short fifo_data; /* fifo data reg,
  59. * holds extra byte on odd dma reads
  60. */
  61. unsigned short fifo_count;
  62. unsigned short csr; /* control/status reg */
  63. unsigned short bpack_hi; /* vme only */
  64. unsigned short bpack_lo; /* vme only */
  65. unsigned short ivect; /* vme only */
  66. unsigned short fifo_count_hi; /* vme only */
  67. };
  68. /* ucd chip specific regs - live in dvma space */
  69. struct sun3_udc_regs {
  70. unsigned short rsel; /* select regs to load */
  71. unsigned short addr_hi; /* high word of addr */
  72. unsigned short addr_lo; /* low word */
  73. unsigned short count; /* words to be xfer'd */
  74. unsigned short mode_hi; /* high word of channel mode */
  75. unsigned short mode_lo; /* low word of channel mode */
  76. };
  77. /* addresses of the udc registers */
  78. #define UDC_MODE 0x38
  79. #define UDC_CSR 0x2e /* command/status */
  80. #define UDC_CHN_HI 0x26 /* chain high word */
  81. #define UDC_CHN_LO 0x22 /* chain lo word */
  82. #define UDC_CURA_HI 0x1a /* cur reg A high */
  83. #define UDC_CURA_LO 0x0a /* cur reg A low */
  84. #define UDC_CURB_HI 0x12 /* cur reg B high */
  85. #define UDC_CURB_LO 0x02 /* cur reg B low */
  86. #define UDC_MODE_HI 0x56 /* mode reg high */
  87. #define UDC_MODE_LO 0x52 /* mode reg low */
  88. #define UDC_COUNT 0x32 /* words to xfer */
  89. /* some udc commands */
  90. #define UDC_RESET 0
  91. #define UDC_CHN_START 0xa0 /* start chain */
  92. #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
  93. /* udc mode words */
  94. #define UDC_MODE_HIWORD 0x40
  95. #define UDC_MODE_LSEND 0xc2
  96. #define UDC_MODE_LRECV 0xd2
  97. /* udc reg selections */
  98. #define UDC_RSEL_SEND 0x282
  99. #define UDC_RSEL_RECV 0x182
  100. /* bits in csr reg */
  101. #define CSR_DMA_ACTIVE 0x8000
  102. #define CSR_DMA_CONFLICT 0x4000
  103. #define CSR_DMA_BUSERR 0x2000
  104. #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
  105. #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
  106. #define CSR_DMA_INT 0x100 /* dma interrupt pending */
  107. #define CSR_LEFT 0xc0
  108. #define CSR_LEFT_3 0xc0
  109. #define CSR_LEFT_2 0x80
  110. #define CSR_LEFT_1 0x40
  111. #define CSR_PACK_ENABLE 0x20
  112. #define CSR_DMA_ENABLE 0x10
  113. #define CSR_SEND 0x8 /* 1 = send 0 = recv */
  114. #define CSR_FIFO 0x2 /* reset fifo */
  115. #define CSR_INTR 0x4 /* interrupt enable */
  116. #define CSR_SCSI 0x1
  117. #define VME_DATA24 0x3d00
  118. extern int sun3_map_test(unsigned long, char *);
  119. static int setup_can_queue = -1;
  120. module_param(setup_can_queue, int, 0);
  121. static int setup_cmd_per_lun = -1;
  122. module_param(setup_cmd_per_lun, int, 0);
  123. static int setup_sg_tablesize = -1;
  124. module_param(setup_sg_tablesize, int, 0);
  125. static int setup_hostid = -1;
  126. module_param(setup_hostid, int, 0);
  127. /* ms to wait after hitting dma regs */
  128. #define SUN3_DMA_DELAY 10
  129. /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
  130. #define SUN3_DVMA_BUFSIZE 0xe000
  131. static struct scsi_cmnd *sun3_dma_setup_done;
  132. static volatile struct sun3_dma_regs *dregs;
  133. static struct sun3_udc_regs *udc_regs;
  134. static unsigned char *sun3_dma_orig_addr;
  135. static unsigned long sun3_dma_orig_count;
  136. static int sun3_dma_active;
  137. static unsigned long last_residual;
  138. #ifndef SUN3_SCSI_VME
  139. /* dma controller register access functions */
  140. static inline unsigned short sun3_udc_read(unsigned char reg)
  141. {
  142. unsigned short ret;
  143. dregs->udc_addr = UDC_CSR;
  144. udelay(SUN3_DMA_DELAY);
  145. ret = dregs->udc_data;
  146. udelay(SUN3_DMA_DELAY);
  147. return ret;
  148. }
  149. static inline void sun3_udc_write(unsigned short val, unsigned char reg)
  150. {
  151. dregs->udc_addr = reg;
  152. udelay(SUN3_DMA_DELAY);
  153. dregs->udc_data = val;
  154. udelay(SUN3_DMA_DELAY);
  155. }
  156. #endif
  157. // safe bits for the CSR
  158. #define CSR_GOOD 0x060f
  159. static irqreturn_t scsi_sun3_intr(int irq, void *dev)
  160. {
  161. struct Scsi_Host *instance = dev;
  162. unsigned short csr = dregs->csr;
  163. int handled = 0;
  164. #ifdef SUN3_SCSI_VME
  165. dregs->csr &= ~CSR_DMA_ENABLE;
  166. #endif
  167. if(csr & ~CSR_GOOD) {
  168. if (csr & CSR_DMA_BUSERR)
  169. shost_printk(KERN_ERR, instance, "bus error in DMA\n");
  170. if (csr & CSR_DMA_CONFLICT)
  171. shost_printk(KERN_ERR, instance, "DMA conflict\n");
  172. handled = 1;
  173. }
  174. if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
  175. NCR5380_intr(irq, dev);
  176. handled = 1;
  177. }
  178. return IRQ_RETVAL(handled);
  179. }
  180. /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
  181. static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
  182. unsigned char *data, int count, int write_flag)
  183. {
  184. void *addr;
  185. if(sun3_dma_orig_addr != NULL)
  186. dvma_unmap(sun3_dma_orig_addr);
  187. #ifdef SUN3_SCSI_VME
  188. addr = (void *)dvma_map_vme((unsigned long) data, count);
  189. #else
  190. addr = (void *)dvma_map((unsigned long) data, count);
  191. #endif
  192. sun3_dma_orig_addr = addr;
  193. sun3_dma_orig_count = count;
  194. #ifndef SUN3_SCSI_VME
  195. dregs->fifo_count = 0;
  196. sun3_udc_write(UDC_RESET, UDC_CSR);
  197. /* reset fifo */
  198. dregs->csr &= ~CSR_FIFO;
  199. dregs->csr |= CSR_FIFO;
  200. #endif
  201. /* set direction */
  202. if(write_flag)
  203. dregs->csr |= CSR_SEND;
  204. else
  205. dregs->csr &= ~CSR_SEND;
  206. #ifdef SUN3_SCSI_VME
  207. dregs->csr |= CSR_PACK_ENABLE;
  208. dregs->dma_addr_hi = ((unsigned long)addr >> 16);
  209. dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
  210. dregs->dma_count_hi = 0;
  211. dregs->dma_count_lo = 0;
  212. dregs->fifo_count_hi = 0;
  213. dregs->fifo_count = 0;
  214. #else
  215. /* byte count for fifo */
  216. dregs->fifo_count = count;
  217. sun3_udc_write(UDC_RESET, UDC_CSR);
  218. /* reset fifo */
  219. dregs->csr &= ~CSR_FIFO;
  220. dregs->csr |= CSR_FIFO;
  221. if(dregs->fifo_count != count) {
  222. shost_printk(KERN_ERR, hostdata->host,
  223. "FIFO mismatch %04x not %04x\n",
  224. dregs->fifo_count, (unsigned int) count);
  225. NCR5380_dprint(NDEBUG_DMA, hostdata->host);
  226. }
  227. /* setup udc */
  228. udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
  229. udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
  230. udc_regs->count = count/2; /* count in words */
  231. udc_regs->mode_hi = UDC_MODE_HIWORD;
  232. if(write_flag) {
  233. if(count & 1)
  234. udc_regs->count++;
  235. udc_regs->mode_lo = UDC_MODE_LSEND;
  236. udc_regs->rsel = UDC_RSEL_SEND;
  237. } else {
  238. udc_regs->mode_lo = UDC_MODE_LRECV;
  239. udc_regs->rsel = UDC_RSEL_RECV;
  240. }
  241. /* announce location of regs block */
  242. sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
  243. UDC_CHN_HI);
  244. sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
  245. /* set dma master on */
  246. sun3_udc_write(0xd, UDC_MODE);
  247. /* interrupt enable */
  248. sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
  249. #endif
  250. return count;
  251. }
  252. static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
  253. unsigned char *data, int count)
  254. {
  255. return count;
  256. }
  257. static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
  258. unsigned char *data, int count)
  259. {
  260. return sun3scsi_dma_setup(hostdata, data, count, 0);
  261. }
  262. static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
  263. unsigned char *data, int count)
  264. {
  265. return sun3scsi_dma_setup(hostdata, data, count, 1);
  266. }
  267. static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
  268. {
  269. return last_residual;
  270. }
  271. static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
  272. struct scsi_cmnd *cmd)
  273. {
  274. int wanted_len = cmd->SCp.this_residual;
  275. if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
  276. return 0;
  277. return wanted_len;
  278. }
  279. static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
  280. {
  281. #ifdef SUN3_SCSI_VME
  282. unsigned short csr;
  283. csr = dregs->csr;
  284. dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
  285. dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
  286. dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
  287. dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
  288. /* if(!(csr & CSR_DMA_ENABLE))
  289. * dregs->csr |= CSR_DMA_ENABLE;
  290. */
  291. #else
  292. sun3_udc_write(UDC_CHN_START, UDC_CSR);
  293. #endif
  294. return 0;
  295. }
  296. /* clean up after our dma is done */
  297. static int sun3scsi_dma_finish(int write_flag)
  298. {
  299. unsigned short __maybe_unused count;
  300. unsigned short fifo;
  301. int ret = 0;
  302. sun3_dma_active = 0;
  303. #ifdef SUN3_SCSI_VME
  304. dregs->csr &= ~CSR_DMA_ENABLE;
  305. fifo = dregs->fifo_count;
  306. if (write_flag) {
  307. if ((fifo > 0) && (fifo < sun3_dma_orig_count))
  308. fifo++;
  309. }
  310. last_residual = fifo;
  311. /* empty bytes from the fifo which didn't make it */
  312. if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
  313. unsigned char *vaddr;
  314. vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
  315. vaddr += (sun3_dma_orig_count - fifo);
  316. vaddr--;
  317. switch (dregs->csr & CSR_LEFT) {
  318. case CSR_LEFT_3:
  319. *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
  320. vaddr--;
  321. fallthrough;
  322. case CSR_LEFT_2:
  323. *vaddr = (dregs->bpack_hi & 0x00ff);
  324. vaddr--;
  325. fallthrough;
  326. case CSR_LEFT_1:
  327. *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
  328. break;
  329. }
  330. }
  331. #else
  332. // check to empty the fifo on a read
  333. if(!write_flag) {
  334. int tmo = 20000; /* .2 sec */
  335. while(1) {
  336. if(dregs->csr & CSR_FIFO_EMPTY)
  337. break;
  338. if(--tmo <= 0) {
  339. printk("sun3scsi: fifo failed to empty!\n");
  340. return 1;
  341. }
  342. udelay(10);
  343. }
  344. }
  345. dregs->udc_addr = 0x32;
  346. udelay(SUN3_DMA_DELAY);
  347. count = 2 * dregs->udc_data;
  348. udelay(SUN3_DMA_DELAY);
  349. fifo = dregs->fifo_count;
  350. last_residual = fifo;
  351. /* empty bytes from the fifo which didn't make it */
  352. if((!write_flag) && (count - fifo) == 2) {
  353. unsigned short data;
  354. unsigned char *vaddr;
  355. data = dregs->fifo_data;
  356. vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
  357. vaddr += (sun3_dma_orig_count - fifo);
  358. vaddr[-2] = (data & 0xff00) >> 8;
  359. vaddr[-1] = (data & 0xff);
  360. }
  361. #endif
  362. dvma_unmap(sun3_dma_orig_addr);
  363. sun3_dma_orig_addr = NULL;
  364. #ifdef SUN3_SCSI_VME
  365. dregs->dma_addr_hi = 0;
  366. dregs->dma_addr_lo = 0;
  367. dregs->dma_count_hi = 0;
  368. dregs->dma_count_lo = 0;
  369. dregs->fifo_count = 0;
  370. dregs->fifo_count_hi = 0;
  371. dregs->csr &= ~CSR_SEND;
  372. /* dregs->csr |= CSR_DMA_ENABLE; */
  373. #else
  374. sun3_udc_write(UDC_RESET, UDC_CSR);
  375. dregs->fifo_count = 0;
  376. dregs->csr &= ~CSR_SEND;
  377. /* reset fifo */
  378. dregs->csr &= ~CSR_FIFO;
  379. dregs->csr |= CSR_FIFO;
  380. #endif
  381. sun3_dma_setup_done = NULL;
  382. return ret;
  383. }
  384. #include "NCR5380.c"
  385. #ifdef SUN3_SCSI_VME
  386. #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
  387. #define DRV_MODULE_NAME "sun3_scsi_vme"
  388. #else
  389. #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
  390. #define DRV_MODULE_NAME "sun3_scsi"
  391. #endif
  392. #define PFX DRV_MODULE_NAME ": "
  393. static struct scsi_host_template sun3_scsi_template = {
  394. .module = THIS_MODULE,
  395. .proc_name = DRV_MODULE_NAME,
  396. .name = SUN3_SCSI_NAME,
  397. .info = sun3scsi_info,
  398. .queuecommand = sun3scsi_queue_command,
  399. .eh_abort_handler = sun3scsi_abort,
  400. .eh_host_reset_handler = sun3scsi_host_reset,
  401. .can_queue = 16,
  402. .this_id = 7,
  403. .sg_tablesize = 1,
  404. .cmd_per_lun = 2,
  405. .dma_boundary = PAGE_SIZE - 1,
  406. .cmd_size = NCR5380_CMD_SIZE,
  407. };
  408. static int __init sun3_scsi_probe(struct platform_device *pdev)
  409. {
  410. struct Scsi_Host *instance;
  411. struct NCR5380_hostdata *hostdata;
  412. int error;
  413. struct resource *irq, *mem;
  414. void __iomem *ioaddr;
  415. int host_flags = 0;
  416. #ifdef SUN3_SCSI_VME
  417. int i;
  418. #endif
  419. if (setup_can_queue > 0)
  420. sun3_scsi_template.can_queue = setup_can_queue;
  421. if (setup_cmd_per_lun > 0)
  422. sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
  423. if (setup_sg_tablesize > 0)
  424. sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
  425. if (setup_hostid >= 0)
  426. sun3_scsi_template.this_id = setup_hostid & 7;
  427. #ifdef SUN3_SCSI_VME
  428. ioaddr = NULL;
  429. for (i = 0; i < 2; i++) {
  430. unsigned char x;
  431. irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
  432. mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
  433. if (!irq || !mem)
  434. break;
  435. ioaddr = sun3_ioremap(mem->start, resource_size(mem),
  436. SUN3_PAGE_TYPE_VME16);
  437. dregs = (struct sun3_dma_regs *)(ioaddr + 8);
  438. if (sun3_map_test((unsigned long)dregs, &x)) {
  439. unsigned short oldcsr;
  440. oldcsr = dregs->csr;
  441. dregs->csr = 0;
  442. udelay(SUN3_DMA_DELAY);
  443. if (dregs->csr == 0x1400)
  444. break;
  445. dregs->csr = oldcsr;
  446. }
  447. iounmap(ioaddr);
  448. ioaddr = NULL;
  449. }
  450. if (!ioaddr)
  451. return -ENODEV;
  452. #else
  453. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  454. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  455. if (!irq || !mem)
  456. return -ENODEV;
  457. ioaddr = ioremap(mem->start, resource_size(mem));
  458. dregs = (struct sun3_dma_regs *)(ioaddr + 8);
  459. udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
  460. if (!udc_regs) {
  461. pr_err(PFX "couldn't allocate DVMA memory!\n");
  462. iounmap(ioaddr);
  463. return -ENOMEM;
  464. }
  465. #endif
  466. instance = scsi_host_alloc(&sun3_scsi_template,
  467. sizeof(struct NCR5380_hostdata));
  468. if (!instance) {
  469. error = -ENOMEM;
  470. goto fail_alloc;
  471. }
  472. instance->irq = irq->start;
  473. hostdata = shost_priv(instance);
  474. hostdata->base = mem->start;
  475. hostdata->io = ioaddr;
  476. error = NCR5380_init(instance, host_flags);
  477. if (error)
  478. goto fail_init;
  479. error = request_irq(instance->irq, scsi_sun3_intr, 0,
  480. "NCR5380", instance);
  481. if (error) {
  482. pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
  483. instance->host_no, instance->irq);
  484. goto fail_irq;
  485. }
  486. dregs->csr = 0;
  487. udelay(SUN3_DMA_DELAY);
  488. dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
  489. udelay(SUN3_DMA_DELAY);
  490. dregs->fifo_count = 0;
  491. #ifdef SUN3_SCSI_VME
  492. dregs->fifo_count_hi = 0;
  493. dregs->dma_addr_hi = 0;
  494. dregs->dma_addr_lo = 0;
  495. dregs->dma_count_hi = 0;
  496. dregs->dma_count_lo = 0;
  497. dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
  498. #endif
  499. NCR5380_maybe_reset_bus(instance);
  500. error = scsi_add_host(instance, NULL);
  501. if (error)
  502. goto fail_host;
  503. platform_set_drvdata(pdev, instance);
  504. scsi_scan_host(instance);
  505. return 0;
  506. fail_host:
  507. free_irq(instance->irq, instance);
  508. fail_irq:
  509. NCR5380_exit(instance);
  510. fail_init:
  511. scsi_host_put(instance);
  512. fail_alloc:
  513. if (udc_regs)
  514. dvma_free(udc_regs);
  515. iounmap(ioaddr);
  516. return error;
  517. }
  518. static int __exit sun3_scsi_remove(struct platform_device *pdev)
  519. {
  520. struct Scsi_Host *instance = platform_get_drvdata(pdev);
  521. struct NCR5380_hostdata *hostdata = shost_priv(instance);
  522. void __iomem *ioaddr = hostdata->io;
  523. scsi_remove_host(instance);
  524. free_irq(instance->irq, instance);
  525. NCR5380_exit(instance);
  526. scsi_host_put(instance);
  527. if (udc_regs)
  528. dvma_free(udc_regs);
  529. iounmap(ioaddr);
  530. return 0;
  531. }
  532. static struct platform_driver sun3_scsi_driver = {
  533. .remove = __exit_p(sun3_scsi_remove),
  534. .driver = {
  535. .name = DRV_MODULE_NAME,
  536. },
  537. };
  538. module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
  539. MODULE_ALIAS("platform:" DRV_MODULE_NAME);
  540. MODULE_LICENSE("GPL");