stex.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * SuperTrak EX Series Storage Controller driver for Linux
  4. *
  5. * Copyright (C) 2005-2015 Promise Technology Inc.
  6. *
  7. * Written By:
  8. * Ed Lin <promise_linux@promise.com>
  9. */
  10. #include <linux/init.h>
  11. #include <linux/errno.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/time.h>
  16. #include <linux/pci.h>
  17. #include <linux/blkdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/types.h>
  20. #include <linux/module.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/ktime.h>
  23. #include <linux/reboot.h>
  24. #include <asm/io.h>
  25. #include <asm/irq.h>
  26. #include <asm/byteorder.h>
  27. #include <scsi/scsi.h>
  28. #include <scsi/scsi_device.h>
  29. #include <scsi/scsi_cmnd.h>
  30. #include <scsi/scsi_host.h>
  31. #include <scsi/scsi_tcq.h>
  32. #include <scsi/scsi_dbg.h>
  33. #include <scsi/scsi_eh.h>
  34. #define DRV_NAME "stex"
  35. #define ST_DRIVER_VERSION "6.02.0000.01"
  36. #define ST_VER_MAJOR 6
  37. #define ST_VER_MINOR 02
  38. #define ST_OEM 0000
  39. #define ST_BUILD_VER 01
  40. enum {
  41. /* MU register offset */
  42. IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  43. IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  44. OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  45. OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  46. IDBL = 0x20, /* MU_INBOUND_DOORBELL */
  47. IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  48. IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  49. ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
  50. OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  51. OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  52. YIOA_STATUS = 0x00,
  53. YH2I_INT = 0x20,
  54. YINT_EN = 0x34,
  55. YI2H_INT = 0x9c,
  56. YI2H_INT_C = 0xa0,
  57. YH2I_REQ = 0xc0,
  58. YH2I_REQ_HI = 0xc4,
  59. PSCRATCH0 = 0xb0,
  60. PSCRATCH1 = 0xb4,
  61. PSCRATCH2 = 0xb8,
  62. PSCRATCH3 = 0xbc,
  63. PSCRATCH4 = 0xc8,
  64. MAILBOX_BASE = 0x1000,
  65. MAILBOX_HNDSHK_STS = 0x0,
  66. /* MU register value */
  67. MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
  68. MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
  69. MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
  70. MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
  71. MU_INBOUND_DOORBELL_RESET = (1 << 4),
  72. MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
  73. MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  74. MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
  75. MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
  76. MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
  77. MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
  78. /* MU status code */
  79. MU_STATE_STARTING = 1,
  80. MU_STATE_STARTED = 2,
  81. MU_STATE_RESETTING = 3,
  82. MU_STATE_FAILED = 4,
  83. MU_STATE_STOP = 5,
  84. MU_STATE_NOCONNECT = 6,
  85. MU_MAX_DELAY = 50,
  86. MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
  87. MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
  88. MU_HARD_RESET_WAIT = 30000,
  89. HMU_PARTNER_TYPE = 2,
  90. /* firmware returned values */
  91. SRB_STATUS_SUCCESS = 0x01,
  92. SRB_STATUS_ERROR = 0x04,
  93. SRB_STATUS_BUSY = 0x05,
  94. SRB_STATUS_INVALID_REQUEST = 0x06,
  95. SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
  96. SRB_SEE_SENSE = 0x80,
  97. /* task attribute */
  98. TASK_ATTRIBUTE_SIMPLE = 0x0,
  99. TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
  100. TASK_ATTRIBUTE_ORDERED = 0x2,
  101. TASK_ATTRIBUTE_ACA = 0x4,
  102. SS_STS_NORMAL = 0x80000000,
  103. SS_STS_DONE = 0x40000000,
  104. SS_STS_HANDSHAKE = 0x20000000,
  105. SS_HEAD_HANDSHAKE = 0x80,
  106. SS_H2I_INT_RESET = 0x100,
  107. SS_I2H_REQUEST_RESET = 0x2000,
  108. SS_MU_OPERATIONAL = 0x80000000,
  109. STEX_CDB_LENGTH = 16,
  110. STATUS_VAR_LEN = 128,
  111. /* sg flags */
  112. SG_CF_EOT = 0x80, /* end of table */
  113. SG_CF_64B = 0x40, /* 64 bit item */
  114. SG_CF_HOST = 0x20, /* sg in host memory */
  115. MSG_DATA_DIR_ND = 0,
  116. MSG_DATA_DIR_IN = 1,
  117. MSG_DATA_DIR_OUT = 2,
  118. st_shasta = 0,
  119. st_vsc = 1,
  120. st_yosemite = 2,
  121. st_seq = 3,
  122. st_yel = 4,
  123. st_P3 = 5,
  124. PASSTHRU_REQ_TYPE = 0x00000001,
  125. PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
  126. ST_INTERNAL_TIMEOUT = 180,
  127. ST_TO_CMD = 0,
  128. ST_FROM_CMD = 1,
  129. /* vendor specific commands of Promise */
  130. MGT_CMD = 0xd8,
  131. SINBAND_MGT_CMD = 0xd9,
  132. ARRAY_CMD = 0xe0,
  133. CONTROLLER_CMD = 0xe1,
  134. DEBUGGING_CMD = 0xe2,
  135. PASSTHRU_CMD = 0xe3,
  136. PASSTHRU_GET_ADAPTER = 0x05,
  137. PASSTHRU_GET_DRVVER = 0x10,
  138. CTLR_CONFIG_CMD = 0x03,
  139. CTLR_SHUTDOWN = 0x0d,
  140. CTLR_POWER_STATE_CHANGE = 0x0e,
  141. CTLR_POWER_SAVING = 0x01,
  142. PASSTHRU_SIGNATURE = 0x4e415041,
  143. MGT_CMD_SIGNATURE = 0xba,
  144. INQUIRY_EVPD = 0x01,
  145. ST_ADDITIONAL_MEM = 0x200000,
  146. ST_ADDITIONAL_MEM_MIN = 0x80000,
  147. PMIC_SHUTDOWN = 0x0D,
  148. PMIC_REUMSE = 0x10,
  149. ST_IGNORED = -1,
  150. ST_NOTHANDLED = 7,
  151. ST_S3 = 3,
  152. ST_S4 = 4,
  153. ST_S5 = 5,
  154. ST_S6 = 6,
  155. };
  156. struct st_sgitem {
  157. u8 ctrl; /* SG_CF_xxx */
  158. u8 reserved[3];
  159. __le32 count;
  160. __le64 addr;
  161. };
  162. struct st_ss_sgitem {
  163. __le32 addr;
  164. __le32 addr_hi;
  165. __le32 count;
  166. };
  167. struct st_sgtable {
  168. __le16 sg_count;
  169. __le16 max_sg_count;
  170. __le32 sz_in_byte;
  171. };
  172. struct st_msg_header {
  173. __le64 handle;
  174. u8 flag;
  175. u8 channel;
  176. __le16 timeout;
  177. u32 reserved;
  178. };
  179. struct handshake_frame {
  180. __le64 rb_phy; /* request payload queue physical address */
  181. __le16 req_sz; /* size of each request payload */
  182. __le16 req_cnt; /* count of reqs the buffer can hold */
  183. __le16 status_sz; /* size of each status payload */
  184. __le16 status_cnt; /* count of status the buffer can hold */
  185. __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
  186. u8 partner_type; /* who sends this frame */
  187. u8 reserved0[7];
  188. __le32 partner_ver_major;
  189. __le32 partner_ver_minor;
  190. __le32 partner_ver_oem;
  191. __le32 partner_ver_build;
  192. __le32 extra_offset; /* NEW */
  193. __le32 extra_size; /* NEW */
  194. __le32 scratch_size;
  195. u32 reserved1;
  196. };
  197. struct req_msg {
  198. __le16 tag;
  199. u8 lun;
  200. u8 target;
  201. u8 task_attr;
  202. u8 task_manage;
  203. u8 data_dir;
  204. u8 payload_sz; /* payload size in 4-byte, not used */
  205. u8 cdb[STEX_CDB_LENGTH];
  206. u32 variable[];
  207. };
  208. struct status_msg {
  209. __le16 tag;
  210. u8 lun;
  211. u8 target;
  212. u8 srb_status;
  213. u8 scsi_status;
  214. u8 reserved;
  215. u8 payload_sz; /* payload size in 4-byte */
  216. u8 variable[STATUS_VAR_LEN];
  217. };
  218. struct ver_info {
  219. u32 major;
  220. u32 minor;
  221. u32 oem;
  222. u32 build;
  223. u32 reserved[2];
  224. };
  225. struct st_frame {
  226. u32 base[6];
  227. u32 rom_addr;
  228. struct ver_info drv_ver;
  229. struct ver_info bios_ver;
  230. u32 bus;
  231. u32 slot;
  232. u32 irq_level;
  233. u32 irq_vec;
  234. u32 id;
  235. u32 subid;
  236. u32 dimm_size;
  237. u8 dimm_type;
  238. u8 reserved[3];
  239. u32 channel;
  240. u32 reserved1;
  241. };
  242. struct st_drvver {
  243. u32 major;
  244. u32 minor;
  245. u32 oem;
  246. u32 build;
  247. u32 signature[2];
  248. u8 console_id;
  249. u8 host_no;
  250. u8 reserved0[2];
  251. u32 reserved[3];
  252. };
  253. struct st_ccb {
  254. struct req_msg *req;
  255. struct scsi_cmnd *cmd;
  256. void *sense_buffer;
  257. unsigned int sense_bufflen;
  258. int sg_count;
  259. u32 req_type;
  260. u8 srb_status;
  261. u8 scsi_status;
  262. u8 reserved[2];
  263. };
  264. struct st_hba {
  265. void __iomem *mmio_base; /* iomapped PCI memory space */
  266. void *dma_mem;
  267. dma_addr_t dma_handle;
  268. size_t dma_size;
  269. struct Scsi_Host *host;
  270. struct pci_dev *pdev;
  271. struct req_msg * (*alloc_rq) (struct st_hba *);
  272. int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
  273. void (*send) (struct st_hba *, struct req_msg *, u16);
  274. u32 req_head;
  275. u32 req_tail;
  276. u32 status_head;
  277. u32 status_tail;
  278. struct status_msg *status_buffer;
  279. void *copy_buffer; /* temp buffer for driver-handled commands */
  280. struct st_ccb *ccb;
  281. struct st_ccb *wait_ccb;
  282. __le32 *scratch;
  283. char work_q_name[20];
  284. struct workqueue_struct *work_q;
  285. struct work_struct reset_work;
  286. wait_queue_head_t reset_waitq;
  287. unsigned int mu_status;
  288. unsigned int cardtype;
  289. int msi_enabled;
  290. int out_req_cnt;
  291. u32 extra_offset;
  292. u16 rq_count;
  293. u16 rq_size;
  294. u16 sts_count;
  295. u8 supports_pm;
  296. int msi_lock;
  297. };
  298. struct st_card_info {
  299. struct req_msg * (*alloc_rq) (struct st_hba *);
  300. int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
  301. void (*send) (struct st_hba *, struct req_msg *, u16);
  302. unsigned int max_id;
  303. unsigned int max_lun;
  304. unsigned int max_channel;
  305. u16 rq_count;
  306. u16 rq_size;
  307. u16 sts_count;
  308. };
  309. static int S6flag;
  310. static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
  311. static struct notifier_block stex_notifier = {
  312. stex_halt, NULL, 0
  313. };
  314. static int msi;
  315. module_param(msi, int, 0);
  316. MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
  317. static const char console_inq_page[] =
  318. {
  319. 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
  320. 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
  321. 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
  322. 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
  323. 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
  324. 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
  325. 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
  326. 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  327. };
  328. MODULE_AUTHOR("Ed Lin");
  329. MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
  330. MODULE_LICENSE("GPL");
  331. MODULE_VERSION(ST_DRIVER_VERSION);
  332. static struct status_msg *stex_get_status(struct st_hba *hba)
  333. {
  334. struct status_msg *status = hba->status_buffer + hba->status_tail;
  335. ++hba->status_tail;
  336. hba->status_tail %= hba->sts_count+1;
  337. return status;
  338. }
  339. static void stex_invalid_field(struct scsi_cmnd *cmd,
  340. void (*done)(struct scsi_cmnd *))
  341. {
  342. cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
  343. /* "Invalid field in cdb" */
  344. scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
  345. 0x0);
  346. done(cmd);
  347. }
  348. static struct req_msg *stex_alloc_req(struct st_hba *hba)
  349. {
  350. struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
  351. ++hba->req_head;
  352. hba->req_head %= hba->rq_count+1;
  353. return req;
  354. }
  355. static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
  356. {
  357. return (struct req_msg *)(hba->dma_mem +
  358. hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
  359. }
  360. static int stex_map_sg(struct st_hba *hba,
  361. struct req_msg *req, struct st_ccb *ccb)
  362. {
  363. struct scsi_cmnd *cmd;
  364. struct scatterlist *sg;
  365. struct st_sgtable *dst;
  366. struct st_sgitem *table;
  367. int i, nseg;
  368. cmd = ccb->cmd;
  369. nseg = scsi_dma_map(cmd);
  370. BUG_ON(nseg < 0);
  371. if (nseg) {
  372. dst = (struct st_sgtable *)req->variable;
  373. ccb->sg_count = nseg;
  374. dst->sg_count = cpu_to_le16((u16)nseg);
  375. dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
  376. dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
  377. table = (struct st_sgitem *)(dst + 1);
  378. scsi_for_each_sg(cmd, sg, nseg, i) {
  379. table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
  380. table[i].addr = cpu_to_le64(sg_dma_address(sg));
  381. table[i].ctrl = SG_CF_64B | SG_CF_HOST;
  382. }
  383. table[--i].ctrl |= SG_CF_EOT;
  384. }
  385. return nseg;
  386. }
  387. static int stex_ss_map_sg(struct st_hba *hba,
  388. struct req_msg *req, struct st_ccb *ccb)
  389. {
  390. struct scsi_cmnd *cmd;
  391. struct scatterlist *sg;
  392. struct st_sgtable *dst;
  393. struct st_ss_sgitem *table;
  394. int i, nseg;
  395. cmd = ccb->cmd;
  396. nseg = scsi_dma_map(cmd);
  397. BUG_ON(nseg < 0);
  398. if (nseg) {
  399. dst = (struct st_sgtable *)req->variable;
  400. ccb->sg_count = nseg;
  401. dst->sg_count = cpu_to_le16((u16)nseg);
  402. dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
  403. dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
  404. table = (struct st_ss_sgitem *)(dst + 1);
  405. scsi_for_each_sg(cmd, sg, nseg, i) {
  406. table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
  407. table[i].addr =
  408. cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
  409. table[i].addr_hi =
  410. cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
  411. }
  412. }
  413. return nseg;
  414. }
  415. static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
  416. {
  417. struct st_frame *p;
  418. size_t count = sizeof(struct st_frame);
  419. p = hba->copy_buffer;
  420. scsi_sg_copy_to_buffer(ccb->cmd, p, count);
  421. memset(p->base, 0, sizeof(u32)*6);
  422. *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
  423. p->rom_addr = 0;
  424. p->drv_ver.major = ST_VER_MAJOR;
  425. p->drv_ver.minor = ST_VER_MINOR;
  426. p->drv_ver.oem = ST_OEM;
  427. p->drv_ver.build = ST_BUILD_VER;
  428. p->bus = hba->pdev->bus->number;
  429. p->slot = hba->pdev->devfn;
  430. p->irq_level = 0;
  431. p->irq_vec = hba->pdev->irq;
  432. p->id = hba->pdev->vendor << 16 | hba->pdev->device;
  433. p->subid =
  434. hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
  435. scsi_sg_copy_from_buffer(ccb->cmd, p, count);
  436. }
  437. static void
  438. stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  439. {
  440. req->tag = cpu_to_le16(tag);
  441. hba->ccb[tag].req = req;
  442. hba->out_req_cnt++;
  443. writel(hba->req_head, hba->mmio_base + IMR0);
  444. writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
  445. readl(hba->mmio_base + IDBL); /* flush */
  446. }
  447. static void
  448. stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  449. {
  450. struct scsi_cmnd *cmd;
  451. struct st_msg_header *msg_h;
  452. dma_addr_t addr;
  453. req->tag = cpu_to_le16(tag);
  454. hba->ccb[tag].req = req;
  455. hba->out_req_cnt++;
  456. cmd = hba->ccb[tag].cmd;
  457. msg_h = (struct st_msg_header *)req - 1;
  458. if (likely(cmd)) {
  459. msg_h->channel = (u8)cmd->device->channel;
  460. msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
  461. }
  462. addr = hba->dma_handle + hba->req_head * hba->rq_size;
  463. addr += (hba->ccb[tag].sg_count+4)/11;
  464. msg_h->handle = cpu_to_le64(addr);
  465. ++hba->req_head;
  466. hba->req_head %= hba->rq_count+1;
  467. if (hba->cardtype == st_P3) {
  468. writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
  469. writel(addr, hba->mmio_base + YH2I_REQ);
  470. } else {
  471. writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
  472. readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
  473. writel(addr, hba->mmio_base + YH2I_REQ);
  474. readl(hba->mmio_base + YH2I_REQ); /* flush */
  475. }
  476. }
  477. static void return_abnormal_state(struct st_hba *hba, int status)
  478. {
  479. struct st_ccb *ccb;
  480. unsigned long flags;
  481. u16 tag;
  482. spin_lock_irqsave(hba->host->host_lock, flags);
  483. for (tag = 0; tag < hba->host->can_queue; tag++) {
  484. ccb = &hba->ccb[tag];
  485. if (ccb->req == NULL)
  486. continue;
  487. ccb->req = NULL;
  488. if (ccb->cmd) {
  489. scsi_dma_unmap(ccb->cmd);
  490. ccb->cmd->result = status << 16;
  491. ccb->cmd->scsi_done(ccb->cmd);
  492. ccb->cmd = NULL;
  493. }
  494. }
  495. spin_unlock_irqrestore(hba->host->host_lock, flags);
  496. }
  497. static int
  498. stex_slave_config(struct scsi_device *sdev)
  499. {
  500. sdev->use_10_for_rw = 1;
  501. sdev->use_10_for_ms = 1;
  502. blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
  503. return 0;
  504. }
  505. static int
  506. stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  507. {
  508. struct st_hba *hba;
  509. struct Scsi_Host *host;
  510. unsigned int id, lun;
  511. struct req_msg *req;
  512. u16 tag;
  513. host = cmd->device->host;
  514. id = cmd->device->id;
  515. lun = cmd->device->lun;
  516. hba = (struct st_hba *) &host->hostdata[0];
  517. if (hba->mu_status == MU_STATE_NOCONNECT) {
  518. cmd->result = DID_NO_CONNECT;
  519. done(cmd);
  520. return 0;
  521. }
  522. if (unlikely(hba->mu_status != MU_STATE_STARTED))
  523. return SCSI_MLQUEUE_HOST_BUSY;
  524. switch (cmd->cmnd[0]) {
  525. case MODE_SENSE_10:
  526. {
  527. static char ms10_caching_page[12] =
  528. { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
  529. unsigned char page;
  530. page = cmd->cmnd[2] & 0x3f;
  531. if (page == 0x8 || page == 0x3f) {
  532. scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
  533. sizeof(ms10_caching_page));
  534. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  535. done(cmd);
  536. } else
  537. stex_invalid_field(cmd, done);
  538. return 0;
  539. }
  540. case REPORT_LUNS:
  541. /*
  542. * The shasta firmware does not report actual luns in the
  543. * target, so fail the command to force sequential lun scan.
  544. * Also, the console device does not support this command.
  545. */
  546. if (hba->cardtype == st_shasta || id == host->max_id - 1) {
  547. stex_invalid_field(cmd, done);
  548. return 0;
  549. }
  550. break;
  551. case TEST_UNIT_READY:
  552. if (id == host->max_id - 1) {
  553. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  554. done(cmd);
  555. return 0;
  556. }
  557. break;
  558. case INQUIRY:
  559. if (lun >= host->max_lun) {
  560. cmd->result = DID_NO_CONNECT << 16;
  561. done(cmd);
  562. return 0;
  563. }
  564. if (id != host->max_id - 1)
  565. break;
  566. if (!lun && !cmd->device->channel &&
  567. (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
  568. scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
  569. sizeof(console_inq_page));
  570. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  571. done(cmd);
  572. } else
  573. stex_invalid_field(cmd, done);
  574. return 0;
  575. case PASSTHRU_CMD:
  576. if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
  577. struct st_drvver ver;
  578. size_t cp_len = sizeof(ver);
  579. ver.major = ST_VER_MAJOR;
  580. ver.minor = ST_VER_MINOR;
  581. ver.oem = ST_OEM;
  582. ver.build = ST_BUILD_VER;
  583. ver.signature[0] = PASSTHRU_SIGNATURE;
  584. ver.console_id = host->max_id - 1;
  585. ver.host_no = hba->host->host_no;
  586. cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
  587. cmd->result = sizeof(ver) == cp_len ?
  588. DID_OK << 16 | COMMAND_COMPLETE << 8 :
  589. DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  590. done(cmd);
  591. return 0;
  592. }
  593. default:
  594. break;
  595. }
  596. cmd->scsi_done = done;
  597. tag = cmd->request->tag;
  598. if (unlikely(tag >= host->can_queue))
  599. return SCSI_MLQUEUE_HOST_BUSY;
  600. req = hba->alloc_rq(hba);
  601. req->lun = lun;
  602. req->target = id;
  603. /* cdb */
  604. memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
  605. if (cmd->sc_data_direction == DMA_FROM_DEVICE)
  606. req->data_dir = MSG_DATA_DIR_IN;
  607. else if (cmd->sc_data_direction == DMA_TO_DEVICE)
  608. req->data_dir = MSG_DATA_DIR_OUT;
  609. else
  610. req->data_dir = MSG_DATA_DIR_ND;
  611. hba->ccb[tag].cmd = cmd;
  612. hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  613. hba->ccb[tag].sense_buffer = cmd->sense_buffer;
  614. if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
  615. hba->ccb[tag].sg_count = 0;
  616. memset(&req->variable[0], 0, 8);
  617. }
  618. hba->send(hba, req, tag);
  619. return 0;
  620. }
  621. static DEF_SCSI_QCMD(stex_queuecommand)
  622. static void stex_scsi_done(struct st_ccb *ccb)
  623. {
  624. struct scsi_cmnd *cmd = ccb->cmd;
  625. int result;
  626. if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
  627. result = ccb->scsi_status;
  628. switch (ccb->scsi_status) {
  629. case SAM_STAT_GOOD:
  630. result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
  631. break;
  632. case SAM_STAT_CHECK_CONDITION:
  633. result |= DRIVER_SENSE << 24;
  634. break;
  635. case SAM_STAT_BUSY:
  636. result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  637. break;
  638. default:
  639. result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  640. break;
  641. }
  642. }
  643. else if (ccb->srb_status & SRB_SEE_SENSE)
  644. result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
  645. else switch (ccb->srb_status) {
  646. case SRB_STATUS_SELECTION_TIMEOUT:
  647. result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
  648. break;
  649. case SRB_STATUS_BUSY:
  650. result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  651. break;
  652. case SRB_STATUS_INVALID_REQUEST:
  653. case SRB_STATUS_ERROR:
  654. default:
  655. result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  656. break;
  657. }
  658. cmd->result = result;
  659. cmd->scsi_done(cmd);
  660. }
  661. static void stex_copy_data(struct st_ccb *ccb,
  662. struct status_msg *resp, unsigned int variable)
  663. {
  664. if (resp->scsi_status != SAM_STAT_GOOD) {
  665. if (ccb->sense_buffer != NULL)
  666. memcpy(ccb->sense_buffer, resp->variable,
  667. min(variable, ccb->sense_bufflen));
  668. return;
  669. }
  670. if (ccb->cmd == NULL)
  671. return;
  672. scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
  673. }
  674. static void stex_check_cmd(struct st_hba *hba,
  675. struct st_ccb *ccb, struct status_msg *resp)
  676. {
  677. if (ccb->cmd->cmnd[0] == MGT_CMD &&
  678. resp->scsi_status != SAM_STAT_CHECK_CONDITION)
  679. scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
  680. le32_to_cpu(*(__le32 *)&resp->variable[0]));
  681. }
  682. static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
  683. {
  684. void __iomem *base = hba->mmio_base;
  685. struct status_msg *resp;
  686. struct st_ccb *ccb;
  687. unsigned int size;
  688. u16 tag;
  689. if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
  690. return;
  691. /* status payloads */
  692. hba->status_head = readl(base + OMR1);
  693. if (unlikely(hba->status_head > hba->sts_count)) {
  694. printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
  695. pci_name(hba->pdev));
  696. return;
  697. }
  698. /*
  699. * it's not a valid status payload if:
  700. * 1. there are no pending requests(e.g. during init stage)
  701. * 2. there are some pending requests, but the controller is in
  702. * reset status, and its type is not st_yosemite
  703. * firmware of st_yosemite in reset status will return pending requests
  704. * to driver, so we allow it to pass
  705. */
  706. if (unlikely(hba->out_req_cnt <= 0 ||
  707. (hba->mu_status == MU_STATE_RESETTING &&
  708. hba->cardtype != st_yosemite))) {
  709. hba->status_tail = hba->status_head;
  710. goto update_status;
  711. }
  712. while (hba->status_tail != hba->status_head) {
  713. resp = stex_get_status(hba);
  714. tag = le16_to_cpu(resp->tag);
  715. if (unlikely(tag >= hba->host->can_queue)) {
  716. printk(KERN_WARNING DRV_NAME
  717. "(%s): invalid tag\n", pci_name(hba->pdev));
  718. continue;
  719. }
  720. hba->out_req_cnt--;
  721. ccb = &hba->ccb[tag];
  722. if (unlikely(hba->wait_ccb == ccb))
  723. hba->wait_ccb = NULL;
  724. if (unlikely(ccb->req == NULL)) {
  725. printk(KERN_WARNING DRV_NAME
  726. "(%s): lagging req\n", pci_name(hba->pdev));
  727. continue;
  728. }
  729. size = resp->payload_sz * sizeof(u32); /* payload size */
  730. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  731. size > sizeof(*resp))) {
  732. printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
  733. pci_name(hba->pdev));
  734. } else {
  735. size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
  736. if (size)
  737. stex_copy_data(ccb, resp, size);
  738. }
  739. ccb->req = NULL;
  740. ccb->srb_status = resp->srb_status;
  741. ccb->scsi_status = resp->scsi_status;
  742. if (likely(ccb->cmd != NULL)) {
  743. if (hba->cardtype == st_yosemite)
  744. stex_check_cmd(hba, ccb, resp);
  745. if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
  746. ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
  747. stex_controller_info(hba, ccb);
  748. scsi_dma_unmap(ccb->cmd);
  749. stex_scsi_done(ccb);
  750. } else
  751. ccb->req_type = 0;
  752. }
  753. update_status:
  754. writel(hba->status_head, base + IMR1);
  755. readl(base + IMR1); /* flush */
  756. }
  757. static irqreturn_t stex_intr(int irq, void *__hba)
  758. {
  759. struct st_hba *hba = __hba;
  760. void __iomem *base = hba->mmio_base;
  761. u32 data;
  762. unsigned long flags;
  763. spin_lock_irqsave(hba->host->host_lock, flags);
  764. data = readl(base + ODBL);
  765. if (data && data != 0xffffffff) {
  766. /* clear the interrupt */
  767. writel(data, base + ODBL);
  768. readl(base + ODBL); /* flush */
  769. stex_mu_intr(hba, data);
  770. spin_unlock_irqrestore(hba->host->host_lock, flags);
  771. if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
  772. hba->cardtype == st_shasta))
  773. queue_work(hba->work_q, &hba->reset_work);
  774. return IRQ_HANDLED;
  775. }
  776. spin_unlock_irqrestore(hba->host->host_lock, flags);
  777. return IRQ_NONE;
  778. }
  779. static void stex_ss_mu_intr(struct st_hba *hba)
  780. {
  781. struct status_msg *resp;
  782. struct st_ccb *ccb;
  783. __le32 *scratch;
  784. unsigned int size;
  785. int count = 0;
  786. u32 value;
  787. u16 tag;
  788. if (unlikely(hba->out_req_cnt <= 0 ||
  789. hba->mu_status == MU_STATE_RESETTING))
  790. return;
  791. while (count < hba->sts_count) {
  792. scratch = hba->scratch + hba->status_tail;
  793. value = le32_to_cpu(*scratch);
  794. if (unlikely(!(value & SS_STS_NORMAL)))
  795. return;
  796. resp = hba->status_buffer + hba->status_tail;
  797. *scratch = 0;
  798. ++count;
  799. ++hba->status_tail;
  800. hba->status_tail %= hba->sts_count+1;
  801. tag = (u16)value;
  802. if (unlikely(tag >= hba->host->can_queue)) {
  803. printk(KERN_WARNING DRV_NAME
  804. "(%s): invalid tag\n", pci_name(hba->pdev));
  805. continue;
  806. }
  807. hba->out_req_cnt--;
  808. ccb = &hba->ccb[tag];
  809. if (unlikely(hba->wait_ccb == ccb))
  810. hba->wait_ccb = NULL;
  811. if (unlikely(ccb->req == NULL)) {
  812. printk(KERN_WARNING DRV_NAME
  813. "(%s): lagging req\n", pci_name(hba->pdev));
  814. continue;
  815. }
  816. ccb->req = NULL;
  817. if (likely(value & SS_STS_DONE)) { /* normal case */
  818. ccb->srb_status = SRB_STATUS_SUCCESS;
  819. ccb->scsi_status = SAM_STAT_GOOD;
  820. } else {
  821. ccb->srb_status = resp->srb_status;
  822. ccb->scsi_status = resp->scsi_status;
  823. size = resp->payload_sz * sizeof(u32);
  824. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  825. size > sizeof(*resp))) {
  826. printk(KERN_WARNING DRV_NAME
  827. "(%s): bad status size\n",
  828. pci_name(hba->pdev));
  829. } else {
  830. size -= sizeof(*resp) - STATUS_VAR_LEN;
  831. if (size)
  832. stex_copy_data(ccb, resp, size);
  833. }
  834. if (likely(ccb->cmd != NULL))
  835. stex_check_cmd(hba, ccb, resp);
  836. }
  837. if (likely(ccb->cmd != NULL)) {
  838. scsi_dma_unmap(ccb->cmd);
  839. stex_scsi_done(ccb);
  840. } else
  841. ccb->req_type = 0;
  842. }
  843. }
  844. static irqreturn_t stex_ss_intr(int irq, void *__hba)
  845. {
  846. struct st_hba *hba = __hba;
  847. void __iomem *base = hba->mmio_base;
  848. u32 data;
  849. unsigned long flags;
  850. spin_lock_irqsave(hba->host->host_lock, flags);
  851. if (hba->cardtype == st_yel) {
  852. data = readl(base + YI2H_INT);
  853. if (data && data != 0xffffffff) {
  854. /* clear the interrupt */
  855. writel(data, base + YI2H_INT_C);
  856. stex_ss_mu_intr(hba);
  857. spin_unlock_irqrestore(hba->host->host_lock, flags);
  858. if (unlikely(data & SS_I2H_REQUEST_RESET))
  859. queue_work(hba->work_q, &hba->reset_work);
  860. return IRQ_HANDLED;
  861. }
  862. } else {
  863. data = readl(base + PSCRATCH4);
  864. if (data != 0xffffffff) {
  865. if (data != 0) {
  866. /* clear the interrupt */
  867. writel(data, base + PSCRATCH1);
  868. writel((1 << 22), base + YH2I_INT);
  869. }
  870. stex_ss_mu_intr(hba);
  871. spin_unlock_irqrestore(hba->host->host_lock, flags);
  872. if (unlikely(data & SS_I2H_REQUEST_RESET))
  873. queue_work(hba->work_q, &hba->reset_work);
  874. return IRQ_HANDLED;
  875. }
  876. }
  877. spin_unlock_irqrestore(hba->host->host_lock, flags);
  878. return IRQ_NONE;
  879. }
  880. static int stex_common_handshake(struct st_hba *hba)
  881. {
  882. void __iomem *base = hba->mmio_base;
  883. struct handshake_frame *h;
  884. dma_addr_t status_phys;
  885. u32 data;
  886. unsigned long before;
  887. if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  888. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  889. readl(base + IDBL);
  890. before = jiffies;
  891. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  892. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  893. printk(KERN_ERR DRV_NAME
  894. "(%s): no handshake signature\n",
  895. pci_name(hba->pdev));
  896. return -1;
  897. }
  898. rmb();
  899. msleep(1);
  900. }
  901. }
  902. udelay(10);
  903. data = readl(base + OMR1);
  904. if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
  905. data &= 0x0000ffff;
  906. if (hba->host->can_queue > data) {
  907. hba->host->can_queue = data;
  908. hba->host->cmd_per_lun = data;
  909. }
  910. }
  911. h = (struct handshake_frame *)hba->status_buffer;
  912. h->rb_phy = cpu_to_le64(hba->dma_handle);
  913. h->req_sz = cpu_to_le16(hba->rq_size);
  914. h->req_cnt = cpu_to_le16(hba->rq_count+1);
  915. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  916. h->status_cnt = cpu_to_le16(hba->sts_count+1);
  917. h->hosttime = cpu_to_le64(ktime_get_real_seconds());
  918. h->partner_type = HMU_PARTNER_TYPE;
  919. if (hba->extra_offset) {
  920. h->extra_offset = cpu_to_le32(hba->extra_offset);
  921. h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
  922. } else
  923. h->extra_offset = h->extra_size = 0;
  924. status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
  925. writel(status_phys, base + IMR0);
  926. readl(base + IMR0);
  927. writel((status_phys >> 16) >> 16, base + IMR1);
  928. readl(base + IMR1);
  929. writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
  930. readl(base + OMR0);
  931. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  932. readl(base + IDBL); /* flush */
  933. udelay(10);
  934. before = jiffies;
  935. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  936. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  937. printk(KERN_ERR DRV_NAME
  938. "(%s): no signature after handshake frame\n",
  939. pci_name(hba->pdev));
  940. return -1;
  941. }
  942. rmb();
  943. msleep(1);
  944. }
  945. writel(0, base + IMR0);
  946. readl(base + IMR0);
  947. writel(0, base + OMR0);
  948. readl(base + OMR0);
  949. writel(0, base + IMR1);
  950. readl(base + IMR1);
  951. writel(0, base + OMR1);
  952. readl(base + OMR1); /* flush */
  953. return 0;
  954. }
  955. static int stex_ss_handshake(struct st_hba *hba)
  956. {
  957. void __iomem *base = hba->mmio_base;
  958. struct st_msg_header *msg_h;
  959. struct handshake_frame *h;
  960. __le32 *scratch;
  961. u32 data, scratch_size, mailboxdata, operationaldata;
  962. unsigned long before;
  963. int ret = 0;
  964. before = jiffies;
  965. if (hba->cardtype == st_yel) {
  966. operationaldata = readl(base + YIOA_STATUS);
  967. while (operationaldata != SS_MU_OPERATIONAL) {
  968. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  969. printk(KERN_ERR DRV_NAME
  970. "(%s): firmware not operational\n",
  971. pci_name(hba->pdev));
  972. return -1;
  973. }
  974. msleep(1);
  975. operationaldata = readl(base + YIOA_STATUS);
  976. }
  977. } else {
  978. operationaldata = readl(base + PSCRATCH3);
  979. while (operationaldata != SS_MU_OPERATIONAL) {
  980. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  981. printk(KERN_ERR DRV_NAME
  982. "(%s): firmware not operational\n",
  983. pci_name(hba->pdev));
  984. return -1;
  985. }
  986. msleep(1);
  987. operationaldata = readl(base + PSCRATCH3);
  988. }
  989. }
  990. msg_h = (struct st_msg_header *)hba->dma_mem;
  991. msg_h->handle = cpu_to_le64(hba->dma_handle);
  992. msg_h->flag = SS_HEAD_HANDSHAKE;
  993. h = (struct handshake_frame *)(msg_h + 1);
  994. h->rb_phy = cpu_to_le64(hba->dma_handle);
  995. h->req_sz = cpu_to_le16(hba->rq_size);
  996. h->req_cnt = cpu_to_le16(hba->rq_count+1);
  997. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  998. h->status_cnt = cpu_to_le16(hba->sts_count+1);
  999. h->hosttime = cpu_to_le64(ktime_get_real_seconds());
  1000. h->partner_type = HMU_PARTNER_TYPE;
  1001. h->extra_offset = h->extra_size = 0;
  1002. scratch_size = (hba->sts_count+1)*sizeof(u32);
  1003. h->scratch_size = cpu_to_le32(scratch_size);
  1004. if (hba->cardtype == st_yel) {
  1005. data = readl(base + YINT_EN);
  1006. data &= ~4;
  1007. writel(data, base + YINT_EN);
  1008. writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
  1009. readl(base + YH2I_REQ_HI);
  1010. writel(hba->dma_handle, base + YH2I_REQ);
  1011. readl(base + YH2I_REQ); /* flush */
  1012. } else {
  1013. data = readl(base + YINT_EN);
  1014. data &= ~(1 << 0);
  1015. data &= ~(1 << 2);
  1016. writel(data, base + YINT_EN);
  1017. if (hba->msi_lock == 0) {
  1018. /* P3 MSI Register cannot access twice */
  1019. writel((1 << 6), base + YH2I_INT);
  1020. hba->msi_lock = 1;
  1021. }
  1022. writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
  1023. writel(hba->dma_handle, base + YH2I_REQ);
  1024. }
  1025. before = jiffies;
  1026. scratch = hba->scratch;
  1027. if (hba->cardtype == st_yel) {
  1028. while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
  1029. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  1030. printk(KERN_ERR DRV_NAME
  1031. "(%s): no signature after handshake frame\n",
  1032. pci_name(hba->pdev));
  1033. ret = -1;
  1034. break;
  1035. }
  1036. rmb();
  1037. msleep(1);
  1038. }
  1039. } else {
  1040. mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
  1041. while (mailboxdata != SS_STS_HANDSHAKE) {
  1042. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  1043. printk(KERN_ERR DRV_NAME
  1044. "(%s): no signature after handshake frame\n",
  1045. pci_name(hba->pdev));
  1046. ret = -1;
  1047. break;
  1048. }
  1049. rmb();
  1050. msleep(1);
  1051. mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
  1052. }
  1053. }
  1054. memset(scratch, 0, scratch_size);
  1055. msg_h->flag = 0;
  1056. return ret;
  1057. }
  1058. static int stex_handshake(struct st_hba *hba)
  1059. {
  1060. int err;
  1061. unsigned long flags;
  1062. unsigned int mu_status;
  1063. if (hba->cardtype == st_yel || hba->cardtype == st_P3)
  1064. err = stex_ss_handshake(hba);
  1065. else
  1066. err = stex_common_handshake(hba);
  1067. spin_lock_irqsave(hba->host->host_lock, flags);
  1068. mu_status = hba->mu_status;
  1069. if (err == 0) {
  1070. hba->req_head = 0;
  1071. hba->req_tail = 0;
  1072. hba->status_head = 0;
  1073. hba->status_tail = 0;
  1074. hba->out_req_cnt = 0;
  1075. hba->mu_status = MU_STATE_STARTED;
  1076. } else
  1077. hba->mu_status = MU_STATE_FAILED;
  1078. if (mu_status == MU_STATE_RESETTING)
  1079. wake_up_all(&hba->reset_waitq);
  1080. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1081. return err;
  1082. }
  1083. static int stex_abort(struct scsi_cmnd *cmd)
  1084. {
  1085. struct Scsi_Host *host = cmd->device->host;
  1086. struct st_hba *hba = (struct st_hba *)host->hostdata;
  1087. u16 tag = cmd->request->tag;
  1088. void __iomem *base;
  1089. u32 data;
  1090. int result = SUCCESS;
  1091. unsigned long flags;
  1092. scmd_printk(KERN_INFO, cmd, "aborting command\n");
  1093. base = hba->mmio_base;
  1094. spin_lock_irqsave(host->host_lock, flags);
  1095. if (tag < host->can_queue &&
  1096. hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
  1097. hba->wait_ccb = &hba->ccb[tag];
  1098. else
  1099. goto out;
  1100. if (hba->cardtype == st_yel) {
  1101. data = readl(base + YI2H_INT);
  1102. if (data == 0 || data == 0xffffffff)
  1103. goto fail_out;
  1104. writel(data, base + YI2H_INT_C);
  1105. stex_ss_mu_intr(hba);
  1106. } else if (hba->cardtype == st_P3) {
  1107. data = readl(base + PSCRATCH4);
  1108. if (data == 0xffffffff)
  1109. goto fail_out;
  1110. if (data != 0) {
  1111. writel(data, base + PSCRATCH1);
  1112. writel((1 << 22), base + YH2I_INT);
  1113. }
  1114. stex_ss_mu_intr(hba);
  1115. } else {
  1116. data = readl(base + ODBL);
  1117. if (data == 0 || data == 0xffffffff)
  1118. goto fail_out;
  1119. writel(data, base + ODBL);
  1120. readl(base + ODBL); /* flush */
  1121. stex_mu_intr(hba, data);
  1122. }
  1123. if (hba->wait_ccb == NULL) {
  1124. printk(KERN_WARNING DRV_NAME
  1125. "(%s): lost interrupt\n", pci_name(hba->pdev));
  1126. goto out;
  1127. }
  1128. fail_out:
  1129. scsi_dma_unmap(cmd);
  1130. hba->wait_ccb->req = NULL; /* nullify the req's future return */
  1131. hba->wait_ccb = NULL;
  1132. result = FAILED;
  1133. out:
  1134. spin_unlock_irqrestore(host->host_lock, flags);
  1135. return result;
  1136. }
  1137. static void stex_hard_reset(struct st_hba *hba)
  1138. {
  1139. struct pci_bus *bus;
  1140. int i;
  1141. u16 pci_cmd;
  1142. u8 pci_bctl;
  1143. for (i = 0; i < 16; i++)
  1144. pci_read_config_dword(hba->pdev, i * 4,
  1145. &hba->pdev->saved_config_space[i]);
  1146. /* Reset secondary bus. Our controller(MU/ATU) is the only device on
  1147. secondary bus. Consult Intel 80331/3 developer's manual for detail */
  1148. bus = hba->pdev->bus;
  1149. pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
  1150. pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
  1151. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  1152. /*
  1153. * 1 ms may be enough for 8-port controllers. But 16-port controllers
  1154. * require more time to finish bus reset. Use 100 ms here for safety
  1155. */
  1156. msleep(100);
  1157. pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  1158. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  1159. for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
  1160. pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
  1161. if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
  1162. break;
  1163. msleep(1);
  1164. }
  1165. ssleep(5);
  1166. for (i = 0; i < 16; i++)
  1167. pci_write_config_dword(hba->pdev, i * 4,
  1168. hba->pdev->saved_config_space[i]);
  1169. }
  1170. static int stex_yos_reset(struct st_hba *hba)
  1171. {
  1172. void __iomem *base;
  1173. unsigned long flags, before;
  1174. int ret = 0;
  1175. base = hba->mmio_base;
  1176. writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
  1177. readl(base + IDBL); /* flush */
  1178. before = jiffies;
  1179. while (hba->out_req_cnt > 0) {
  1180. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  1181. printk(KERN_WARNING DRV_NAME
  1182. "(%s): reset timeout\n", pci_name(hba->pdev));
  1183. ret = -1;
  1184. break;
  1185. }
  1186. msleep(1);
  1187. }
  1188. spin_lock_irqsave(hba->host->host_lock, flags);
  1189. if (ret == -1)
  1190. hba->mu_status = MU_STATE_FAILED;
  1191. else
  1192. hba->mu_status = MU_STATE_STARTED;
  1193. wake_up_all(&hba->reset_waitq);
  1194. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1195. return ret;
  1196. }
  1197. static void stex_ss_reset(struct st_hba *hba)
  1198. {
  1199. writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
  1200. readl(hba->mmio_base + YH2I_INT);
  1201. ssleep(5);
  1202. }
  1203. static void stex_p3_reset(struct st_hba *hba)
  1204. {
  1205. writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
  1206. ssleep(5);
  1207. }
  1208. static int stex_do_reset(struct st_hba *hba)
  1209. {
  1210. unsigned long flags;
  1211. unsigned int mu_status = MU_STATE_RESETTING;
  1212. spin_lock_irqsave(hba->host->host_lock, flags);
  1213. if (hba->mu_status == MU_STATE_STARTING) {
  1214. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1215. printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
  1216. pci_name(hba->pdev));
  1217. return 0;
  1218. }
  1219. while (hba->mu_status == MU_STATE_RESETTING) {
  1220. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1221. wait_event_timeout(hba->reset_waitq,
  1222. hba->mu_status != MU_STATE_RESETTING,
  1223. MU_MAX_DELAY * HZ);
  1224. spin_lock_irqsave(hba->host->host_lock, flags);
  1225. mu_status = hba->mu_status;
  1226. }
  1227. if (mu_status != MU_STATE_RESETTING) {
  1228. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1229. return (mu_status == MU_STATE_STARTED) ? 0 : -1;
  1230. }
  1231. hba->mu_status = MU_STATE_RESETTING;
  1232. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1233. if (hba->cardtype == st_yosemite)
  1234. return stex_yos_reset(hba);
  1235. if (hba->cardtype == st_shasta)
  1236. stex_hard_reset(hba);
  1237. else if (hba->cardtype == st_yel)
  1238. stex_ss_reset(hba);
  1239. else if (hba->cardtype == st_P3)
  1240. stex_p3_reset(hba);
  1241. return_abnormal_state(hba, DID_RESET);
  1242. if (stex_handshake(hba) == 0)
  1243. return 0;
  1244. printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
  1245. pci_name(hba->pdev));
  1246. return -1;
  1247. }
  1248. static int stex_reset(struct scsi_cmnd *cmd)
  1249. {
  1250. struct st_hba *hba;
  1251. hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  1252. shost_printk(KERN_INFO, cmd->device->host,
  1253. "resetting host\n");
  1254. return stex_do_reset(hba) ? FAILED : SUCCESS;
  1255. }
  1256. static void stex_reset_work(struct work_struct *work)
  1257. {
  1258. struct st_hba *hba = container_of(work, struct st_hba, reset_work);
  1259. stex_do_reset(hba);
  1260. }
  1261. static int stex_biosparam(struct scsi_device *sdev,
  1262. struct block_device *bdev, sector_t capacity, int geom[])
  1263. {
  1264. int heads = 255, sectors = 63;
  1265. if (capacity < 0x200000) {
  1266. heads = 64;
  1267. sectors = 32;
  1268. }
  1269. sector_div(capacity, heads * sectors);
  1270. geom[0] = heads;
  1271. geom[1] = sectors;
  1272. geom[2] = capacity;
  1273. return 0;
  1274. }
  1275. static struct scsi_host_template driver_template = {
  1276. .module = THIS_MODULE,
  1277. .name = DRV_NAME,
  1278. .proc_name = DRV_NAME,
  1279. .bios_param = stex_biosparam,
  1280. .queuecommand = stex_queuecommand,
  1281. .slave_configure = stex_slave_config,
  1282. .eh_abort_handler = stex_abort,
  1283. .eh_host_reset_handler = stex_reset,
  1284. .this_id = -1,
  1285. .dma_boundary = PAGE_SIZE - 1,
  1286. };
  1287. static struct pci_device_id stex_pci_tbl[] = {
  1288. /* st_shasta */
  1289. { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1290. st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
  1291. { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1292. st_shasta }, /* SuperTrak EX12350 */
  1293. { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1294. st_shasta }, /* SuperTrak EX4350 */
  1295. { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1296. st_shasta }, /* SuperTrak EX24350 */
  1297. /* st_vsc */
  1298. { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
  1299. /* st_yosemite */
  1300. { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
  1301. /* st_seq */
  1302. { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
  1303. /* st_yel */
  1304. { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
  1305. { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
  1306. /* st_P3, pluto */
  1307. { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
  1308. 0x8870, 0, 0, st_P3 },
  1309. /* st_P3, p3 */
  1310. { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
  1311. 0x4300, 0, 0, st_P3 },
  1312. /* st_P3, SymplyStor4E */
  1313. { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
  1314. 0x4311, 0, 0, st_P3 },
  1315. /* st_P3, SymplyStor8E */
  1316. { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
  1317. 0x4312, 0, 0, st_P3 },
  1318. /* st_P3, SymplyStor4 */
  1319. { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
  1320. 0x4321, 0, 0, st_P3 },
  1321. /* st_P3, SymplyStor8 */
  1322. { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
  1323. 0x4322, 0, 0, st_P3 },
  1324. { } /* terminate list */
  1325. };
  1326. static struct st_card_info stex_card_info[] = {
  1327. /* st_shasta */
  1328. {
  1329. .max_id = 17,
  1330. .max_lun = 8,
  1331. .max_channel = 0,
  1332. .rq_count = 32,
  1333. .rq_size = 1048,
  1334. .sts_count = 32,
  1335. .alloc_rq = stex_alloc_req,
  1336. .map_sg = stex_map_sg,
  1337. .send = stex_send_cmd,
  1338. },
  1339. /* st_vsc */
  1340. {
  1341. .max_id = 129,
  1342. .max_lun = 1,
  1343. .max_channel = 0,
  1344. .rq_count = 32,
  1345. .rq_size = 1048,
  1346. .sts_count = 32,
  1347. .alloc_rq = stex_alloc_req,
  1348. .map_sg = stex_map_sg,
  1349. .send = stex_send_cmd,
  1350. },
  1351. /* st_yosemite */
  1352. {
  1353. .max_id = 2,
  1354. .max_lun = 256,
  1355. .max_channel = 0,
  1356. .rq_count = 256,
  1357. .rq_size = 1048,
  1358. .sts_count = 256,
  1359. .alloc_rq = stex_alloc_req,
  1360. .map_sg = stex_map_sg,
  1361. .send = stex_send_cmd,
  1362. },
  1363. /* st_seq */
  1364. {
  1365. .max_id = 129,
  1366. .max_lun = 1,
  1367. .max_channel = 0,
  1368. .rq_count = 32,
  1369. .rq_size = 1048,
  1370. .sts_count = 32,
  1371. .alloc_rq = stex_alloc_req,
  1372. .map_sg = stex_map_sg,
  1373. .send = stex_send_cmd,
  1374. },
  1375. /* st_yel */
  1376. {
  1377. .max_id = 129,
  1378. .max_lun = 256,
  1379. .max_channel = 3,
  1380. .rq_count = 801,
  1381. .rq_size = 512,
  1382. .sts_count = 801,
  1383. .alloc_rq = stex_ss_alloc_req,
  1384. .map_sg = stex_ss_map_sg,
  1385. .send = stex_ss_send_cmd,
  1386. },
  1387. /* st_P3 */
  1388. {
  1389. .max_id = 129,
  1390. .max_lun = 256,
  1391. .max_channel = 0,
  1392. .rq_count = 801,
  1393. .rq_size = 512,
  1394. .sts_count = 801,
  1395. .alloc_rq = stex_ss_alloc_req,
  1396. .map_sg = stex_ss_map_sg,
  1397. .send = stex_ss_send_cmd,
  1398. },
  1399. };
  1400. static int stex_request_irq(struct st_hba *hba)
  1401. {
  1402. struct pci_dev *pdev = hba->pdev;
  1403. int status;
  1404. if (msi || hba->cardtype == st_P3) {
  1405. status = pci_enable_msi(pdev);
  1406. if (status != 0)
  1407. printk(KERN_ERR DRV_NAME
  1408. "(%s): error %d setting up MSI\n",
  1409. pci_name(pdev), status);
  1410. else
  1411. hba->msi_enabled = 1;
  1412. } else
  1413. hba->msi_enabled = 0;
  1414. status = request_irq(pdev->irq,
  1415. (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
  1416. stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
  1417. if (status != 0) {
  1418. if (hba->msi_enabled)
  1419. pci_disable_msi(pdev);
  1420. }
  1421. return status;
  1422. }
  1423. static void stex_free_irq(struct st_hba *hba)
  1424. {
  1425. struct pci_dev *pdev = hba->pdev;
  1426. free_irq(pdev->irq, hba);
  1427. if (hba->msi_enabled)
  1428. pci_disable_msi(pdev);
  1429. }
  1430. static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1431. {
  1432. struct st_hba *hba;
  1433. struct Scsi_Host *host;
  1434. const struct st_card_info *ci = NULL;
  1435. u32 sts_offset, cp_offset, scratch_offset;
  1436. int err;
  1437. err = pci_enable_device(pdev);
  1438. if (err)
  1439. return err;
  1440. pci_set_master(pdev);
  1441. S6flag = 0;
  1442. register_reboot_notifier(&stex_notifier);
  1443. host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
  1444. if (!host) {
  1445. printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
  1446. pci_name(pdev));
  1447. err = -ENOMEM;
  1448. goto out_disable;
  1449. }
  1450. hba = (struct st_hba *)host->hostdata;
  1451. memset(hba, 0, sizeof(struct st_hba));
  1452. err = pci_request_regions(pdev, DRV_NAME);
  1453. if (err < 0) {
  1454. printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
  1455. pci_name(pdev));
  1456. goto out_scsi_host_put;
  1457. }
  1458. hba->mmio_base = pci_ioremap_bar(pdev, 0);
  1459. if ( !hba->mmio_base) {
  1460. printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
  1461. pci_name(pdev));
  1462. err = -ENOMEM;
  1463. goto out_release_regions;
  1464. }
  1465. err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
  1466. if (err)
  1467. err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  1468. if (err) {
  1469. printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
  1470. pci_name(pdev));
  1471. goto out_iounmap;
  1472. }
  1473. hba->cardtype = (unsigned int) id->driver_data;
  1474. ci = &stex_card_info[hba->cardtype];
  1475. switch (id->subdevice) {
  1476. case 0x4221:
  1477. case 0x4222:
  1478. case 0x4223:
  1479. case 0x4224:
  1480. case 0x4225:
  1481. case 0x4226:
  1482. case 0x4227:
  1483. case 0x4261:
  1484. case 0x4262:
  1485. case 0x4263:
  1486. case 0x4264:
  1487. case 0x4265:
  1488. break;
  1489. default:
  1490. if (hba->cardtype == st_yel || hba->cardtype == st_P3)
  1491. hba->supports_pm = 1;
  1492. }
  1493. sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
  1494. if (hba->cardtype == st_yel || hba->cardtype == st_P3)
  1495. sts_offset += (ci->sts_count+1) * sizeof(u32);
  1496. cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
  1497. hba->dma_size = cp_offset + sizeof(struct st_frame);
  1498. if (hba->cardtype == st_seq ||
  1499. (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
  1500. hba->extra_offset = hba->dma_size;
  1501. hba->dma_size += ST_ADDITIONAL_MEM;
  1502. }
  1503. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  1504. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  1505. if (!hba->dma_mem) {
  1506. /* Retry minimum coherent mapping for st_seq and st_vsc */
  1507. if (hba->cardtype == st_seq ||
  1508. (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
  1509. printk(KERN_WARNING DRV_NAME
  1510. "(%s): allocating min buffer for controller\n",
  1511. pci_name(pdev));
  1512. hba->dma_size = hba->extra_offset
  1513. + ST_ADDITIONAL_MEM_MIN;
  1514. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  1515. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  1516. }
  1517. if (!hba->dma_mem) {
  1518. err = -ENOMEM;
  1519. printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
  1520. pci_name(pdev));
  1521. goto out_iounmap;
  1522. }
  1523. }
  1524. hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
  1525. if (!hba->ccb) {
  1526. err = -ENOMEM;
  1527. printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
  1528. pci_name(pdev));
  1529. goto out_pci_free;
  1530. }
  1531. if (hba->cardtype == st_yel || hba->cardtype == st_P3)
  1532. hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
  1533. hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
  1534. hba->copy_buffer = hba->dma_mem + cp_offset;
  1535. hba->rq_count = ci->rq_count;
  1536. hba->rq_size = ci->rq_size;
  1537. hba->sts_count = ci->sts_count;
  1538. hba->alloc_rq = ci->alloc_rq;
  1539. hba->map_sg = ci->map_sg;
  1540. hba->send = ci->send;
  1541. hba->mu_status = MU_STATE_STARTING;
  1542. hba->msi_lock = 0;
  1543. if (hba->cardtype == st_yel || hba->cardtype == st_P3)
  1544. host->sg_tablesize = 38;
  1545. else
  1546. host->sg_tablesize = 32;
  1547. host->can_queue = ci->rq_count;
  1548. host->cmd_per_lun = ci->rq_count;
  1549. host->max_id = ci->max_id;
  1550. host->max_lun = ci->max_lun;
  1551. host->max_channel = ci->max_channel;
  1552. host->unique_id = host->host_no;
  1553. host->max_cmd_len = STEX_CDB_LENGTH;
  1554. hba->host = host;
  1555. hba->pdev = pdev;
  1556. init_waitqueue_head(&hba->reset_waitq);
  1557. snprintf(hba->work_q_name, sizeof(hba->work_q_name),
  1558. "stex_wq_%d", host->host_no);
  1559. hba->work_q = create_singlethread_workqueue(hba->work_q_name);
  1560. if (!hba->work_q) {
  1561. printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
  1562. pci_name(pdev));
  1563. err = -ENOMEM;
  1564. goto out_ccb_free;
  1565. }
  1566. INIT_WORK(&hba->reset_work, stex_reset_work);
  1567. err = stex_request_irq(hba);
  1568. if (err) {
  1569. printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
  1570. pci_name(pdev));
  1571. goto out_free_wq;
  1572. }
  1573. err = stex_handshake(hba);
  1574. if (err)
  1575. goto out_free_irq;
  1576. pci_set_drvdata(pdev, hba);
  1577. err = scsi_add_host(host, &pdev->dev);
  1578. if (err) {
  1579. printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
  1580. pci_name(pdev));
  1581. goto out_free_irq;
  1582. }
  1583. scsi_scan_host(host);
  1584. return 0;
  1585. out_free_irq:
  1586. stex_free_irq(hba);
  1587. out_free_wq:
  1588. destroy_workqueue(hba->work_q);
  1589. out_ccb_free:
  1590. kfree(hba->ccb);
  1591. out_pci_free:
  1592. dma_free_coherent(&pdev->dev, hba->dma_size,
  1593. hba->dma_mem, hba->dma_handle);
  1594. out_iounmap:
  1595. iounmap(hba->mmio_base);
  1596. out_release_regions:
  1597. pci_release_regions(pdev);
  1598. out_scsi_host_put:
  1599. scsi_host_put(host);
  1600. out_disable:
  1601. pci_disable_device(pdev);
  1602. return err;
  1603. }
  1604. static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
  1605. {
  1606. struct req_msg *req;
  1607. struct st_msg_header *msg_h;
  1608. unsigned long flags;
  1609. unsigned long before;
  1610. u16 tag = 0;
  1611. spin_lock_irqsave(hba->host->host_lock, flags);
  1612. if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
  1613. hba->supports_pm == 1) {
  1614. if (st_sleep_mic == ST_NOTHANDLED) {
  1615. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1616. return;
  1617. }
  1618. }
  1619. req = hba->alloc_rq(hba);
  1620. if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
  1621. msg_h = (struct st_msg_header *)req - 1;
  1622. memset(msg_h, 0, hba->rq_size);
  1623. } else
  1624. memset(req, 0, hba->rq_size);
  1625. if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
  1626. || hba->cardtype == st_P3)
  1627. && st_sleep_mic == ST_IGNORED) {
  1628. req->cdb[0] = MGT_CMD;
  1629. req->cdb[1] = MGT_CMD_SIGNATURE;
  1630. req->cdb[2] = CTLR_CONFIG_CMD;
  1631. req->cdb[3] = CTLR_SHUTDOWN;
  1632. } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
  1633. && st_sleep_mic != ST_IGNORED) {
  1634. req->cdb[0] = MGT_CMD;
  1635. req->cdb[1] = MGT_CMD_SIGNATURE;
  1636. req->cdb[2] = CTLR_CONFIG_CMD;
  1637. req->cdb[3] = PMIC_SHUTDOWN;
  1638. req->cdb[4] = st_sleep_mic;
  1639. } else {
  1640. req->cdb[0] = CONTROLLER_CMD;
  1641. req->cdb[1] = CTLR_POWER_STATE_CHANGE;
  1642. req->cdb[2] = CTLR_POWER_SAVING;
  1643. }
  1644. hba->ccb[tag].cmd = NULL;
  1645. hba->ccb[tag].sg_count = 0;
  1646. hba->ccb[tag].sense_bufflen = 0;
  1647. hba->ccb[tag].sense_buffer = NULL;
  1648. hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
  1649. hba->send(hba, req, tag);
  1650. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1651. before = jiffies;
  1652. while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
  1653. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  1654. hba->ccb[tag].req_type = 0;
  1655. hba->mu_status = MU_STATE_STOP;
  1656. return;
  1657. }
  1658. msleep(1);
  1659. }
  1660. hba->mu_status = MU_STATE_STOP;
  1661. }
  1662. static void stex_hba_free(struct st_hba *hba)
  1663. {
  1664. stex_free_irq(hba);
  1665. destroy_workqueue(hba->work_q);
  1666. iounmap(hba->mmio_base);
  1667. pci_release_regions(hba->pdev);
  1668. kfree(hba->ccb);
  1669. dma_free_coherent(&hba->pdev->dev, hba->dma_size,
  1670. hba->dma_mem, hba->dma_handle);
  1671. }
  1672. static void stex_remove(struct pci_dev *pdev)
  1673. {
  1674. struct st_hba *hba = pci_get_drvdata(pdev);
  1675. hba->mu_status = MU_STATE_NOCONNECT;
  1676. return_abnormal_state(hba, DID_NO_CONNECT);
  1677. scsi_remove_host(hba->host);
  1678. scsi_block_requests(hba->host);
  1679. stex_hba_free(hba);
  1680. scsi_host_put(hba->host);
  1681. pci_disable_device(pdev);
  1682. unregister_reboot_notifier(&stex_notifier);
  1683. }
  1684. static void stex_shutdown(struct pci_dev *pdev)
  1685. {
  1686. struct st_hba *hba = pci_get_drvdata(pdev);
  1687. if (hba->supports_pm == 0) {
  1688. stex_hba_stop(hba, ST_IGNORED);
  1689. } else if (hba->supports_pm == 1 && S6flag) {
  1690. unregister_reboot_notifier(&stex_notifier);
  1691. stex_hba_stop(hba, ST_S6);
  1692. } else
  1693. stex_hba_stop(hba, ST_S5);
  1694. }
  1695. static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
  1696. {
  1697. switch (state.event) {
  1698. case PM_EVENT_SUSPEND:
  1699. return ST_S3;
  1700. case PM_EVENT_HIBERNATE:
  1701. hba->msi_lock = 0;
  1702. return ST_S4;
  1703. default:
  1704. return ST_NOTHANDLED;
  1705. }
  1706. }
  1707. static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
  1708. {
  1709. struct st_hba *hba = pci_get_drvdata(pdev);
  1710. if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
  1711. && hba->supports_pm == 1)
  1712. stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
  1713. else
  1714. stex_hba_stop(hba, ST_IGNORED);
  1715. return 0;
  1716. }
  1717. static int stex_resume(struct pci_dev *pdev)
  1718. {
  1719. struct st_hba *hba = pci_get_drvdata(pdev);
  1720. hba->mu_status = MU_STATE_STARTING;
  1721. stex_handshake(hba);
  1722. return 0;
  1723. }
  1724. static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
  1725. {
  1726. S6flag = 1;
  1727. return NOTIFY_OK;
  1728. }
  1729. MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
  1730. static struct pci_driver stex_pci_driver = {
  1731. .name = DRV_NAME,
  1732. .id_table = stex_pci_tbl,
  1733. .probe = stex_probe,
  1734. .remove = stex_remove,
  1735. .shutdown = stex_shutdown,
  1736. .suspend = stex_suspend,
  1737. .resume = stex_resume,
  1738. };
  1739. static int __init stex_init(void)
  1740. {
  1741. printk(KERN_INFO DRV_NAME
  1742. ": Promise SuperTrak EX Driver version: %s\n",
  1743. ST_DRIVER_VERSION);
  1744. return pci_register_driver(&stex_pci_driver);
  1745. }
  1746. static void __exit stex_exit(void)
  1747. {
  1748. pci_unregister_driver(&stex_pci_driver);
  1749. }
  1750. module_init(stex_init);
  1751. module_exit(stex_exit);