vnic_wq.h 4.7 KB

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  1. /*
  2. * Copyright 2014 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This program is free software; you may redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  9. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  10. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  11. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  12. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  13. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  14. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  15. * SOFTWARE.
  16. */
  17. #ifndef _VNIC_WQ_H_
  18. #define _VNIC_WQ_H_
  19. #include <linux/pci.h>
  20. #include "vnic_dev.h"
  21. #include "vnic_cq.h"
  22. /* Work queue control */
  23. struct vnic_wq_ctrl {
  24. u64 ring_base; /* 0x00 */
  25. u32 ring_size; /* 0x08 */
  26. u32 pad0;
  27. u32 posted_index; /* 0x10 */
  28. u32 pad1;
  29. u32 cq_index; /* 0x18 */
  30. u32 pad2;
  31. u32 enable; /* 0x20 */
  32. u32 pad3;
  33. u32 running; /* 0x28 */
  34. u32 pad4;
  35. u32 fetch_index; /* 0x30 */
  36. u32 pad5;
  37. u32 dca_value; /* 0x38 */
  38. u32 pad6;
  39. u32 error_interrupt_enable; /* 0x40 */
  40. u32 pad7;
  41. u32 error_interrupt_offset; /* 0x48 */
  42. u32 pad8;
  43. u32 error_status; /* 0x50 */
  44. u32 pad9;
  45. };
  46. struct vnic_wq_buf {
  47. struct vnic_wq_buf *next;
  48. dma_addr_t dma_addr;
  49. void *os_buf;
  50. unsigned int len;
  51. unsigned int index;
  52. int sop;
  53. void *desc;
  54. };
  55. /* Break the vnic_wq_buf allocations into blocks of 64 entries */
  56. #define VNIC_WQ_BUF_MIN_BLK_ENTRIES 32
  57. #define VNIC_WQ_BUF_DFLT_BLK_ENTRIES 64
  58. #define VNIC_WQ_BUF_BLK_ENTRIES(entries) \
  59. ((unsigned int)(entries < VNIC_WQ_BUF_DFLT_BLK_ENTRIES) ? \
  60. VNIC_WQ_BUF_MIN_BLK_ENTRIES : VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
  61. #define VNIC_WQ_BUF_BLK_SZ \
  62. (VNIC_WQ_BUF_DFLT_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
  63. #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
  64. DIV_ROUND_UP(entries, VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
  65. #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
  66. DIV_ROUND_UP(entries, VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
  67. #define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
  68. struct vnic_wq {
  69. unsigned int index;
  70. struct vnic_dev *vdev;
  71. struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
  72. struct vnic_dev_ring ring;
  73. struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
  74. struct vnic_wq_buf *to_use;
  75. struct vnic_wq_buf *to_clean;
  76. unsigned int pkts_outstanding;
  77. };
  78. static inline unsigned int svnic_wq_desc_avail(struct vnic_wq *wq)
  79. {
  80. /* how many does SW own? */
  81. return wq->ring.desc_avail;
  82. }
  83. static inline unsigned int svnic_wq_desc_used(struct vnic_wq *wq)
  84. {
  85. /* how many does HW own? */
  86. return wq->ring.desc_count - wq->ring.desc_avail - 1;
  87. }
  88. static inline void *svnic_wq_next_desc(struct vnic_wq *wq)
  89. {
  90. return wq->to_use->desc;
  91. }
  92. static inline void svnic_wq_post(struct vnic_wq *wq,
  93. void *os_buf, dma_addr_t dma_addr,
  94. unsigned int len, int sop, int eop)
  95. {
  96. struct vnic_wq_buf *buf = wq->to_use;
  97. buf->sop = sop;
  98. buf->os_buf = eop ? os_buf : NULL;
  99. buf->dma_addr = dma_addr;
  100. buf->len = len;
  101. buf = buf->next;
  102. if (eop) {
  103. /* Adding write memory barrier prevents compiler and/or CPU
  104. * reordering, thus avoiding descriptor posting before
  105. * descriptor is initialized. Otherwise, hardware can read
  106. * stale descriptor fields.
  107. */
  108. wmb();
  109. iowrite32(buf->index, &wq->ctrl->posted_index);
  110. }
  111. wq->to_use = buf;
  112. wq->ring.desc_avail--;
  113. }
  114. static inline void svnic_wq_service(struct vnic_wq *wq,
  115. struct cq_desc *cq_desc, u16 completed_index,
  116. void (*buf_service)(struct vnic_wq *wq,
  117. struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
  118. void *opaque)
  119. {
  120. struct vnic_wq_buf *buf;
  121. buf = wq->to_clean;
  122. while (1) {
  123. (*buf_service)(wq, cq_desc, buf, opaque);
  124. wq->ring.desc_avail++;
  125. wq->to_clean = buf->next;
  126. if (buf->index == completed_index)
  127. break;
  128. buf = wq->to_clean;
  129. }
  130. }
  131. void svnic_wq_free(struct vnic_wq *wq);
  132. int svnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
  133. unsigned int index, unsigned int desc_count, unsigned int desc_size);
  134. int vnic_wq_devcmd2_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
  135. unsigned int desc_count, unsigned int desc_size);
  136. void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
  137. unsigned int fetch_index, unsigned int post_index,
  138. unsigned int error_interrupt_enable,
  139. unsigned int error_interrupt_offset);
  140. void svnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
  141. unsigned int error_interrupt_enable,
  142. unsigned int error_interrupt_offset);
  143. unsigned int svnic_wq_error_status(struct vnic_wq *wq);
  144. void svnic_wq_enable(struct vnic_wq *wq);
  145. int svnic_wq_disable(struct vnic_wq *wq);
  146. void svnic_wq_clean(struct vnic_wq *wq,
  147. void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
  148. #endif /* _VNIC_WQ_H_ */