vnic_dev.c 17 KB

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  1. /*
  2. * Copyright 2014 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This program is free software; you may redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  9. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  10. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  11. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  12. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  13. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  14. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  15. * SOFTWARE.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/types.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include <linux/if_ether.h>
  23. #include <linux/slab.h>
  24. #include "vnic_resource.h"
  25. #include "vnic_devcmd.h"
  26. #include "vnic_dev.h"
  27. #include "vnic_stats.h"
  28. #include "vnic_wq.h"
  29. #define VNIC_DVCMD_TMO 10000 /* Devcmd Timeout value */
  30. #define VNIC_NOTIFY_INTR_MASK 0x0000ffff00000000ULL
  31. struct devcmd2_controller {
  32. struct vnic_wq_ctrl __iomem *wq_ctrl;
  33. struct vnic_dev_ring results_ring;
  34. struct vnic_wq wq;
  35. struct vnic_devcmd2 *cmd_ring;
  36. struct devcmd2_result *result;
  37. u16 next_result;
  38. u16 result_size;
  39. int color;
  40. };
  41. struct vnic_res {
  42. void __iomem *vaddr;
  43. unsigned int count;
  44. };
  45. struct vnic_dev {
  46. void *priv;
  47. struct pci_dev *pdev;
  48. struct vnic_res res[RES_TYPE_MAX];
  49. enum vnic_dev_intr_mode intr_mode;
  50. struct vnic_devcmd __iomem *devcmd;
  51. struct vnic_devcmd_notify *notify;
  52. struct vnic_devcmd_notify notify_copy;
  53. dma_addr_t notify_pa;
  54. u32 *linkstatus;
  55. dma_addr_t linkstatus_pa;
  56. struct vnic_stats *stats;
  57. dma_addr_t stats_pa;
  58. struct vnic_devcmd_fw_info *fw_info;
  59. dma_addr_t fw_info_pa;
  60. u64 args[VNIC_DEVCMD_NARGS];
  61. struct devcmd2_controller *devcmd2;
  62. int (*devcmd_rtn)(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  63. int wait);
  64. };
  65. #define VNIC_MAX_RES_HDR_SIZE \
  66. (sizeof(struct vnic_resource_header) + \
  67. sizeof(struct vnic_resource) * RES_TYPE_MAX)
  68. #define VNIC_RES_STRIDE 128
  69. void *svnic_dev_priv(struct vnic_dev *vdev)
  70. {
  71. return vdev->priv;
  72. }
  73. static int vnic_dev_discover_res(struct vnic_dev *vdev,
  74. struct vnic_dev_bar *bar, unsigned int num_bars)
  75. {
  76. struct vnic_resource_header __iomem *rh;
  77. struct vnic_resource __iomem *r;
  78. u8 type;
  79. if (num_bars == 0)
  80. return -EINVAL;
  81. if (bar->len < VNIC_MAX_RES_HDR_SIZE) {
  82. pr_err("vNIC BAR0 res hdr length error\n");
  83. return -EINVAL;
  84. }
  85. rh = bar->vaddr;
  86. if (!rh) {
  87. pr_err("vNIC BAR0 res hdr not mem-mapped\n");
  88. return -EINVAL;
  89. }
  90. if (ioread32(&rh->magic) != VNIC_RES_MAGIC ||
  91. ioread32(&rh->version) != VNIC_RES_VERSION) {
  92. pr_err("vNIC BAR0 res magic/version error exp (%lx/%lx) curr (%x/%x)\n",
  93. VNIC_RES_MAGIC, VNIC_RES_VERSION,
  94. ioread32(&rh->magic), ioread32(&rh->version));
  95. return -EINVAL;
  96. }
  97. r = (struct vnic_resource __iomem *)(rh + 1);
  98. while ((type = ioread8(&r->type)) != RES_TYPE_EOL) {
  99. u8 bar_num = ioread8(&r->bar);
  100. u32 bar_offset = ioread32(&r->bar_offset);
  101. u32 count = ioread32(&r->count);
  102. u32 len;
  103. r++;
  104. if (bar_num >= num_bars)
  105. continue;
  106. if (!bar[bar_num].len || !bar[bar_num].vaddr)
  107. continue;
  108. switch (type) {
  109. case RES_TYPE_WQ:
  110. case RES_TYPE_RQ:
  111. case RES_TYPE_CQ:
  112. case RES_TYPE_INTR_CTRL:
  113. /* each count is stride bytes long */
  114. len = count * VNIC_RES_STRIDE;
  115. if (len + bar_offset > bar->len) {
  116. pr_err("vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
  117. type, bar_offset,
  118. len,
  119. bar->len);
  120. return -EINVAL;
  121. }
  122. break;
  123. case RES_TYPE_INTR_PBA_LEGACY:
  124. case RES_TYPE_DEVCMD:
  125. case RES_TYPE_DEVCMD2:
  126. len = count;
  127. break;
  128. default:
  129. continue;
  130. }
  131. vdev->res[type].count = count;
  132. vdev->res[type].vaddr = (char __iomem *)bar->vaddr + bar_offset;
  133. }
  134. return 0;
  135. }
  136. unsigned int svnic_dev_get_res_count(struct vnic_dev *vdev,
  137. enum vnic_res_type type)
  138. {
  139. return vdev->res[type].count;
  140. }
  141. void __iomem *svnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
  142. unsigned int index)
  143. {
  144. if (!vdev->res[type].vaddr)
  145. return NULL;
  146. switch (type) {
  147. case RES_TYPE_WQ:
  148. case RES_TYPE_RQ:
  149. case RES_TYPE_CQ:
  150. case RES_TYPE_INTR_CTRL:
  151. return (char __iomem *)vdev->res[type].vaddr +
  152. index * VNIC_RES_STRIDE;
  153. default:
  154. return (char __iomem *)vdev->res[type].vaddr;
  155. }
  156. }
  157. unsigned int svnic_dev_desc_ring_size(struct vnic_dev_ring *ring,
  158. unsigned int desc_count,
  159. unsigned int desc_size)
  160. {
  161. /* The base address of the desc rings must be 512 byte aligned.
  162. * Descriptor count is aligned to groups of 32 descriptors. A
  163. * count of 0 means the maximum 4096 descriptors. Descriptor
  164. * size is aligned to 16 bytes.
  165. */
  166. unsigned int count_align = 32;
  167. unsigned int desc_align = 16;
  168. ring->base_align = 512;
  169. if (desc_count == 0)
  170. desc_count = 4096;
  171. ring->desc_count = ALIGN(desc_count, count_align);
  172. ring->desc_size = ALIGN(desc_size, desc_align);
  173. ring->size = ring->desc_count * ring->desc_size;
  174. ring->size_unaligned = ring->size + ring->base_align;
  175. return ring->size_unaligned;
  176. }
  177. void svnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)
  178. {
  179. memset(ring->descs, 0, ring->size);
  180. }
  181. int svnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,
  182. unsigned int desc_count, unsigned int desc_size)
  183. {
  184. svnic_dev_desc_ring_size(ring, desc_count, desc_size);
  185. ring->descs_unaligned = dma_alloc_coherent(&vdev->pdev->dev,
  186. ring->size_unaligned, &ring->base_addr_unaligned,
  187. GFP_KERNEL);
  188. if (!ring->descs_unaligned) {
  189. pr_err("Failed to allocate ring (size=%d), aborting\n",
  190. (int)ring->size);
  191. return -ENOMEM;
  192. }
  193. ring->base_addr = ALIGN(ring->base_addr_unaligned,
  194. ring->base_align);
  195. ring->descs = (u8 *)ring->descs_unaligned +
  196. (ring->base_addr - ring->base_addr_unaligned);
  197. svnic_dev_clear_desc_ring(ring);
  198. ring->desc_avail = ring->desc_count - 1;
  199. return 0;
  200. }
  201. void svnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)
  202. {
  203. if (ring->descs) {
  204. dma_free_coherent(&vdev->pdev->dev,
  205. ring->size_unaligned,
  206. ring->descs_unaligned,
  207. ring->base_addr_unaligned);
  208. ring->descs = NULL;
  209. }
  210. }
  211. static int _svnic_dev_cmd2(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  212. int wait)
  213. {
  214. struct devcmd2_controller *dc2c = vdev->devcmd2;
  215. struct devcmd2_result *result = NULL;
  216. unsigned int i;
  217. int delay;
  218. int err;
  219. u32 posted;
  220. u32 fetch_idx;
  221. u32 new_posted;
  222. u8 color;
  223. fetch_idx = ioread32(&dc2c->wq_ctrl->fetch_index);
  224. if (fetch_idx == 0xFFFFFFFF) { /* check for hardware gone */
  225. /* Hardware surprise removal: return error */
  226. return -ENODEV;
  227. }
  228. posted = ioread32(&dc2c->wq_ctrl->posted_index);
  229. if (posted == 0xFFFFFFFF) { /* check for hardware gone */
  230. /* Hardware surprise removal: return error */
  231. return -ENODEV;
  232. }
  233. new_posted = (posted + 1) % DEVCMD2_RING_SIZE;
  234. if (new_posted == fetch_idx) {
  235. pr_err("%s: wq is full while issuing devcmd2 command %d, fetch index: %u, posted index: %u\n",
  236. pci_name(vdev->pdev), _CMD_N(cmd), fetch_idx, posted);
  237. return -EBUSY;
  238. }
  239. dc2c->cmd_ring[posted].cmd = cmd;
  240. dc2c->cmd_ring[posted].flags = 0;
  241. if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
  242. dc2c->cmd_ring[posted].flags |= DEVCMD2_FNORESULT;
  243. if (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {
  244. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  245. dc2c->cmd_ring[posted].args[i] = vdev->args[i];
  246. }
  247. /* Adding write memory barrier prevents compiler and/or CPU
  248. * reordering, thus avoiding descriptor posting before
  249. * descriptor is initialized. Otherwise, hardware can read
  250. * stale descriptor fields.
  251. */
  252. wmb();
  253. iowrite32(new_posted, &dc2c->wq_ctrl->posted_index);
  254. if (dc2c->cmd_ring[posted].flags & DEVCMD2_FNORESULT)
  255. return 0;
  256. result = dc2c->result + dc2c->next_result;
  257. color = dc2c->color;
  258. /*
  259. * Increment next_result, after posting the devcmd, irrespective of
  260. * devcmd result, and it should be done only once.
  261. */
  262. dc2c->next_result++;
  263. if (dc2c->next_result == dc2c->result_size) {
  264. dc2c->next_result = 0;
  265. dc2c->color = dc2c->color ? 0 : 1;
  266. }
  267. for (delay = 0; delay < wait; delay++) {
  268. udelay(100);
  269. if (result->color == color) {
  270. if (result->error) {
  271. err = (int) result->error;
  272. if (err != ERR_ECMDUNKNOWN ||
  273. cmd != CMD_CAPABILITY)
  274. pr_err("Error %d devcmd %d\n",
  275. err, _CMD_N(cmd));
  276. return err;
  277. }
  278. if (_CMD_DIR(cmd) & _CMD_DIR_READ) {
  279. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  280. vdev->args[i] = result->results[i];
  281. }
  282. return 0;
  283. }
  284. }
  285. pr_err("Timed out devcmd %d\n", _CMD_N(cmd));
  286. return -ETIMEDOUT;
  287. }
  288. static int svnic_dev_init_devcmd2(struct vnic_dev *vdev)
  289. {
  290. struct devcmd2_controller *dc2c = NULL;
  291. unsigned int fetch_idx;
  292. int ret;
  293. void __iomem *p;
  294. if (vdev->devcmd2)
  295. return 0;
  296. p = svnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
  297. if (!p)
  298. return -ENODEV;
  299. dc2c = kzalloc(sizeof(*dc2c), GFP_ATOMIC);
  300. if (!dc2c)
  301. return -ENOMEM;
  302. vdev->devcmd2 = dc2c;
  303. dc2c->color = 1;
  304. dc2c->result_size = DEVCMD2_RING_SIZE;
  305. ret = vnic_wq_devcmd2_alloc(vdev,
  306. &dc2c->wq,
  307. DEVCMD2_RING_SIZE,
  308. DEVCMD2_DESC_SIZE);
  309. if (ret)
  310. goto err_free_devcmd2;
  311. fetch_idx = ioread32(&dc2c->wq.ctrl->fetch_index);
  312. if (fetch_idx == 0xFFFFFFFF) { /* check for hardware gone */
  313. /* Hardware surprise removal: reset fetch_index */
  314. fetch_idx = 0;
  315. }
  316. /*
  317. * Don't change fetch_index ever and
  318. * set posted_index same as fetch_index
  319. * when setting up the WQ for devcmd2.
  320. */
  321. vnic_wq_init_start(&dc2c->wq, 0, fetch_idx, fetch_idx, 0, 0);
  322. svnic_wq_enable(&dc2c->wq);
  323. ret = svnic_dev_alloc_desc_ring(vdev,
  324. &dc2c->results_ring,
  325. DEVCMD2_RING_SIZE,
  326. DEVCMD2_DESC_SIZE);
  327. if (ret)
  328. goto err_free_wq;
  329. dc2c->result = (struct devcmd2_result *) dc2c->results_ring.descs;
  330. dc2c->cmd_ring = (struct vnic_devcmd2 *) dc2c->wq.ring.descs;
  331. dc2c->wq_ctrl = dc2c->wq.ctrl;
  332. vdev->args[0] = (u64) dc2c->results_ring.base_addr | VNIC_PADDR_TARGET;
  333. vdev->args[1] = DEVCMD2_RING_SIZE;
  334. ret = _svnic_dev_cmd2(vdev, CMD_INITIALIZE_DEVCMD2, VNIC_DVCMD_TMO);
  335. if (ret < 0)
  336. goto err_free_desc_ring;
  337. vdev->devcmd_rtn = &_svnic_dev_cmd2;
  338. pr_info("DEVCMD2 Initialized.\n");
  339. return ret;
  340. err_free_desc_ring:
  341. svnic_dev_free_desc_ring(vdev, &dc2c->results_ring);
  342. err_free_wq:
  343. svnic_wq_disable(&dc2c->wq);
  344. svnic_wq_free(&dc2c->wq);
  345. err_free_devcmd2:
  346. kfree(dc2c);
  347. vdev->devcmd2 = NULL;
  348. return ret;
  349. } /* end of svnic_dev_init_devcmd2 */
  350. static void vnic_dev_deinit_devcmd2(struct vnic_dev *vdev)
  351. {
  352. struct devcmd2_controller *dc2c = vdev->devcmd2;
  353. vdev->devcmd2 = NULL;
  354. vdev->devcmd_rtn = NULL;
  355. svnic_dev_free_desc_ring(vdev, &dc2c->results_ring);
  356. svnic_wq_disable(&dc2c->wq);
  357. svnic_wq_free(&dc2c->wq);
  358. kfree(dc2c);
  359. }
  360. int svnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  361. u64 *a0, u64 *a1, int wait)
  362. {
  363. int err;
  364. memset(vdev->args, 0, sizeof(vdev->args));
  365. vdev->args[0] = *a0;
  366. vdev->args[1] = *a1;
  367. err = (*vdev->devcmd_rtn)(vdev, cmd, wait);
  368. *a0 = vdev->args[0];
  369. *a1 = vdev->args[1];
  370. return err;
  371. }
  372. int svnic_dev_fw_info(struct vnic_dev *vdev,
  373. struct vnic_devcmd_fw_info **fw_info)
  374. {
  375. u64 a0, a1 = 0;
  376. int wait = VNIC_DVCMD_TMO;
  377. int err = 0;
  378. if (!vdev->fw_info) {
  379. vdev->fw_info = dma_alloc_coherent(&vdev->pdev->dev,
  380. sizeof(struct vnic_devcmd_fw_info),
  381. &vdev->fw_info_pa, GFP_KERNEL);
  382. if (!vdev->fw_info)
  383. return -ENOMEM;
  384. a0 = vdev->fw_info_pa;
  385. /* only get fw_info once and cache it */
  386. err = svnic_dev_cmd(vdev, CMD_MCPU_FW_INFO, &a0, &a1, wait);
  387. }
  388. *fw_info = vdev->fw_info;
  389. return err;
  390. }
  391. int svnic_dev_spec(struct vnic_dev *vdev, unsigned int offset,
  392. unsigned int size, void *value)
  393. {
  394. u64 a0, a1;
  395. int wait = VNIC_DVCMD_TMO;
  396. int err;
  397. a0 = offset;
  398. a1 = size;
  399. err = svnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
  400. switch (size) {
  401. case 1:
  402. *(u8 *)value = (u8)a0;
  403. break;
  404. case 2:
  405. *(u16 *)value = (u16)a0;
  406. break;
  407. case 4:
  408. *(u32 *)value = (u32)a0;
  409. break;
  410. case 8:
  411. *(u64 *)value = a0;
  412. break;
  413. default:
  414. BUG();
  415. break;
  416. }
  417. return err;
  418. }
  419. int svnic_dev_stats_clear(struct vnic_dev *vdev)
  420. {
  421. u64 a0 = 0, a1 = 0;
  422. int wait = VNIC_DVCMD_TMO;
  423. return svnic_dev_cmd(vdev, CMD_STATS_CLEAR, &a0, &a1, wait);
  424. }
  425. int svnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)
  426. {
  427. u64 a0, a1;
  428. int wait = VNIC_DVCMD_TMO;
  429. if (!vdev->stats) {
  430. vdev->stats = dma_alloc_coherent(&vdev->pdev->dev,
  431. sizeof(struct vnic_stats), &vdev->stats_pa, GFP_KERNEL);
  432. if (!vdev->stats)
  433. return -ENOMEM;
  434. }
  435. *stats = vdev->stats;
  436. a0 = vdev->stats_pa;
  437. a1 = sizeof(struct vnic_stats);
  438. return svnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);
  439. }
  440. int svnic_dev_close(struct vnic_dev *vdev)
  441. {
  442. u64 a0 = 0, a1 = 0;
  443. int wait = VNIC_DVCMD_TMO;
  444. return svnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);
  445. }
  446. int svnic_dev_enable_wait(struct vnic_dev *vdev)
  447. {
  448. u64 a0 = 0, a1 = 0;
  449. int wait = VNIC_DVCMD_TMO;
  450. int err = 0;
  451. err = svnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);
  452. if (err == ERR_ECMDUNKNOWN)
  453. return svnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);
  454. return err;
  455. }
  456. int svnic_dev_disable(struct vnic_dev *vdev)
  457. {
  458. u64 a0 = 0, a1 = 0;
  459. int wait = VNIC_DVCMD_TMO;
  460. return svnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);
  461. }
  462. int svnic_dev_open(struct vnic_dev *vdev, int arg)
  463. {
  464. u64 a0 = (u32)arg, a1 = 0;
  465. int wait = VNIC_DVCMD_TMO;
  466. return svnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);
  467. }
  468. int svnic_dev_open_done(struct vnic_dev *vdev, int *done)
  469. {
  470. u64 a0 = 0, a1 = 0;
  471. int wait = VNIC_DVCMD_TMO;
  472. int err;
  473. *done = 0;
  474. err = svnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);
  475. if (err)
  476. return err;
  477. *done = (a0 == 0);
  478. return 0;
  479. }
  480. int svnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)
  481. {
  482. u64 a0, a1;
  483. int wait = VNIC_DVCMD_TMO;
  484. if (!vdev->notify) {
  485. vdev->notify = dma_alloc_coherent(&vdev->pdev->dev,
  486. sizeof(struct vnic_devcmd_notify),
  487. &vdev->notify_pa, GFP_KERNEL);
  488. if (!vdev->notify)
  489. return -ENOMEM;
  490. }
  491. a0 = vdev->notify_pa;
  492. a1 = ((u64)intr << 32) & VNIC_NOTIFY_INTR_MASK;
  493. a1 += sizeof(struct vnic_devcmd_notify);
  494. return svnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
  495. }
  496. void svnic_dev_notify_unset(struct vnic_dev *vdev)
  497. {
  498. u64 a0, a1;
  499. int wait = VNIC_DVCMD_TMO;
  500. a0 = 0; /* paddr = 0 to unset notify buffer */
  501. a1 = VNIC_NOTIFY_INTR_MASK; /* intr num = -1 to unreg for intr */
  502. a1 += sizeof(struct vnic_devcmd_notify);
  503. svnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
  504. }
  505. static int vnic_dev_notify_ready(struct vnic_dev *vdev)
  506. {
  507. u32 *words;
  508. unsigned int nwords = sizeof(struct vnic_devcmd_notify) / 4;
  509. unsigned int i;
  510. u32 csum;
  511. if (!vdev->notify)
  512. return 0;
  513. do {
  514. csum = 0;
  515. memcpy(&vdev->notify_copy, vdev->notify,
  516. sizeof(struct vnic_devcmd_notify));
  517. words = (u32 *)&vdev->notify_copy;
  518. for (i = 1; i < nwords; i++)
  519. csum += words[i];
  520. } while (csum != words[0]);
  521. return 1;
  522. }
  523. int svnic_dev_init(struct vnic_dev *vdev, int arg)
  524. {
  525. u64 a0 = (u32)arg, a1 = 0;
  526. int wait = VNIC_DVCMD_TMO;
  527. return svnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);
  528. }
  529. int svnic_dev_link_status(struct vnic_dev *vdev)
  530. {
  531. if (vdev->linkstatus)
  532. return *vdev->linkstatus;
  533. if (!vnic_dev_notify_ready(vdev))
  534. return 0;
  535. return vdev->notify_copy.link_state;
  536. }
  537. u32 svnic_dev_link_down_cnt(struct vnic_dev *vdev)
  538. {
  539. if (!vnic_dev_notify_ready(vdev))
  540. return 0;
  541. return vdev->notify_copy.link_down_cnt;
  542. }
  543. void svnic_dev_set_intr_mode(struct vnic_dev *vdev,
  544. enum vnic_dev_intr_mode intr_mode)
  545. {
  546. vdev->intr_mode = intr_mode;
  547. }
  548. enum vnic_dev_intr_mode svnic_dev_get_intr_mode(struct vnic_dev *vdev)
  549. {
  550. return vdev->intr_mode;
  551. }
  552. void svnic_dev_unregister(struct vnic_dev *vdev)
  553. {
  554. if (vdev) {
  555. if (vdev->notify)
  556. dma_free_coherent(&vdev->pdev->dev,
  557. sizeof(struct vnic_devcmd_notify),
  558. vdev->notify,
  559. vdev->notify_pa);
  560. if (vdev->linkstatus)
  561. dma_free_coherent(&vdev->pdev->dev,
  562. sizeof(u32),
  563. vdev->linkstatus,
  564. vdev->linkstatus_pa);
  565. if (vdev->stats)
  566. dma_free_coherent(&vdev->pdev->dev,
  567. sizeof(struct vnic_stats),
  568. vdev->stats, vdev->stats_pa);
  569. if (vdev->fw_info)
  570. dma_free_coherent(&vdev->pdev->dev,
  571. sizeof(struct vnic_devcmd_fw_info),
  572. vdev->fw_info, vdev->fw_info_pa);
  573. if (vdev->devcmd2)
  574. vnic_dev_deinit_devcmd2(vdev);
  575. kfree(vdev);
  576. }
  577. }
  578. struct vnic_dev *svnic_dev_alloc_discover(struct vnic_dev *vdev,
  579. void *priv,
  580. struct pci_dev *pdev,
  581. struct vnic_dev_bar *bar,
  582. unsigned int num_bars)
  583. {
  584. if (!vdev) {
  585. vdev = kzalloc(sizeof(struct vnic_dev), GFP_ATOMIC);
  586. if (!vdev)
  587. return NULL;
  588. }
  589. vdev->priv = priv;
  590. vdev->pdev = pdev;
  591. if (vnic_dev_discover_res(vdev, bar, num_bars))
  592. goto err_out;
  593. return vdev;
  594. err_out:
  595. svnic_dev_unregister(vdev);
  596. return NULL;
  597. } /* end of svnic_dev_alloc_discover */
  598. /*
  599. * fallback option is left to keep the interface common for other vnics.
  600. */
  601. int svnic_dev_cmd_init(struct vnic_dev *vdev, int fallback)
  602. {
  603. int err = -ENODEV;
  604. void __iomem *p;
  605. p = svnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
  606. if (p)
  607. err = svnic_dev_init_devcmd2(vdev);
  608. else
  609. pr_err("DEVCMD2 resource not found.\n");
  610. return err;
  611. } /* end of svnic_dev_cmd_init */