snic_isr.c 5.0 KB

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  1. /*
  2. * Copyright 2014 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This program is free software; you may redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  9. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  10. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  11. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  12. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  13. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  14. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  15. * SOFTWARE.
  16. */
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/pci.h>
  20. #include <linux/interrupt.h>
  21. #include "vnic_dev.h"
  22. #include "vnic_intr.h"
  23. #include "vnic_stats.h"
  24. #include "snic_io.h"
  25. #include "snic.h"
  26. /*
  27. * snic_isr_msix_wq : MSIx ISR for work queue.
  28. */
  29. static irqreturn_t
  30. snic_isr_msix_wq(int irq, void *data)
  31. {
  32. struct snic *snic = data;
  33. unsigned long wq_work_done = 0;
  34. snic->s_stats.misc.last_isr_time = jiffies;
  35. atomic64_inc(&snic->s_stats.misc.ack_isr_cnt);
  36. wq_work_done = snic_wq_cmpl_handler(snic, -1);
  37. svnic_intr_return_credits(&snic->intr[SNIC_MSIX_WQ],
  38. wq_work_done,
  39. 1 /* unmask intr */,
  40. 1 /* reset intr timer */);
  41. return IRQ_HANDLED;
  42. } /* end of snic_isr_msix_wq */
  43. static irqreturn_t
  44. snic_isr_msix_io_cmpl(int irq, void *data)
  45. {
  46. struct snic *snic = data;
  47. unsigned long iocmpl_work_done = 0;
  48. snic->s_stats.misc.last_isr_time = jiffies;
  49. atomic64_inc(&snic->s_stats.misc.cmpl_isr_cnt);
  50. iocmpl_work_done = snic_fwcq_cmpl_handler(snic, -1);
  51. svnic_intr_return_credits(&snic->intr[SNIC_MSIX_IO_CMPL],
  52. iocmpl_work_done,
  53. 1 /* unmask intr */,
  54. 1 /* reset intr timer */);
  55. return IRQ_HANDLED;
  56. } /* end of snic_isr_msix_io_cmpl */
  57. static irqreturn_t
  58. snic_isr_msix_err_notify(int irq, void *data)
  59. {
  60. struct snic *snic = data;
  61. snic->s_stats.misc.last_isr_time = jiffies;
  62. atomic64_inc(&snic->s_stats.misc.errnotify_isr_cnt);
  63. svnic_intr_return_all_credits(&snic->intr[SNIC_MSIX_ERR_NOTIFY]);
  64. snic_log_q_error(snic);
  65. /*Handling link events */
  66. snic_handle_link_event(snic);
  67. return IRQ_HANDLED;
  68. } /* end of snic_isr_msix_err_notify */
  69. void
  70. snic_free_intr(struct snic *snic)
  71. {
  72. int i;
  73. /* ONLY interrupt mode MSIX is supported */
  74. for (i = 0; i < ARRAY_SIZE(snic->msix); i++) {
  75. if (snic->msix[i].requested) {
  76. free_irq(pci_irq_vector(snic->pdev, i),
  77. snic->msix[i].devid);
  78. }
  79. }
  80. } /* end of snic_free_intr */
  81. int
  82. snic_request_intr(struct snic *snic)
  83. {
  84. int ret = 0, i;
  85. enum vnic_dev_intr_mode intr_mode;
  86. intr_mode = svnic_dev_get_intr_mode(snic->vdev);
  87. SNIC_BUG_ON(intr_mode != VNIC_DEV_INTR_MODE_MSIX);
  88. /*
  89. * Currently HW supports single WQ and CQ. So passing devid as snic.
  90. * When hardware supports multiple WQs and CQs, one idea is
  91. * to pass devid as corresponding WQ or CQ ptr and retrieve snic
  92. * from queue ptr.
  93. * Except for err_notify, which is always one.
  94. */
  95. sprintf(snic->msix[SNIC_MSIX_WQ].devname,
  96. "%.11s-scsi-wq",
  97. snic->name);
  98. snic->msix[SNIC_MSIX_WQ].isr = snic_isr_msix_wq;
  99. snic->msix[SNIC_MSIX_WQ].devid = snic;
  100. sprintf(snic->msix[SNIC_MSIX_IO_CMPL].devname,
  101. "%.11s-io-cmpl",
  102. snic->name);
  103. snic->msix[SNIC_MSIX_IO_CMPL].isr = snic_isr_msix_io_cmpl;
  104. snic->msix[SNIC_MSIX_IO_CMPL].devid = snic;
  105. sprintf(snic->msix[SNIC_MSIX_ERR_NOTIFY].devname,
  106. "%.11s-err-notify",
  107. snic->name);
  108. snic->msix[SNIC_MSIX_ERR_NOTIFY].isr = snic_isr_msix_err_notify;
  109. snic->msix[SNIC_MSIX_ERR_NOTIFY].devid = snic;
  110. for (i = 0; i < ARRAY_SIZE(snic->msix); i++) {
  111. ret = request_irq(pci_irq_vector(snic->pdev, i),
  112. snic->msix[i].isr,
  113. 0,
  114. snic->msix[i].devname,
  115. snic->msix[i].devid);
  116. if (ret) {
  117. SNIC_HOST_ERR(snic->shost,
  118. "MSI-X: request_irq(%d) failed %d\n",
  119. i,
  120. ret);
  121. snic_free_intr(snic);
  122. break;
  123. }
  124. snic->msix[i].requested = 1;
  125. }
  126. return ret;
  127. } /* end of snic_request_intr */
  128. int
  129. snic_set_intr_mode(struct snic *snic)
  130. {
  131. unsigned int n = ARRAY_SIZE(snic->wq);
  132. unsigned int m = SNIC_CQ_IO_CMPL_MAX;
  133. unsigned int vecs = n + m + 1;
  134. /*
  135. * We need n WQs, m CQs, and n+m+1 INTRs
  136. * (last INTR is used for WQ/CQ errors and notification area
  137. */
  138. BUILD_BUG_ON((ARRAY_SIZE(snic->wq) + SNIC_CQ_IO_CMPL_MAX) >
  139. ARRAY_SIZE(snic->intr));
  140. if (snic->wq_count < n || snic->cq_count < n + m)
  141. goto fail;
  142. if (pci_alloc_irq_vectors(snic->pdev, vecs, vecs, PCI_IRQ_MSIX) < 0)
  143. goto fail;
  144. snic->wq_count = n;
  145. snic->cq_count = n + m;
  146. snic->intr_count = vecs;
  147. snic->err_intr_offset = SNIC_MSIX_ERR_NOTIFY;
  148. SNIC_ISR_DBG(snic->shost, "Using MSI-X Interrupts\n");
  149. svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_MSIX);
  150. return 0;
  151. fail:
  152. svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
  153. return -EINVAL;
  154. } /* end of snic_set_intr_mode */
  155. void
  156. snic_clear_intr_mode(struct snic *snic)
  157. {
  158. pci_free_irq_vectors(snic->pdev);
  159. svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_INTX);
  160. }