qlogicpti.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* qlogicpti.h: Performance Technologies QlogicISP sbus card defines.
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
  5. */
  6. #ifndef _QLOGICPTI_H
  7. #define _QLOGICPTI_H
  8. /* Qlogic/SBUS controller registers. */
  9. #define SBUS_CFG1 0x006UL
  10. #define SBUS_CTRL 0x008UL
  11. #define SBUS_STAT 0x00aUL
  12. #define SBUS_SEMAPHORE 0x00cUL
  13. #define CMD_DMA_CTRL 0x022UL
  14. #define DATA_DMA_CTRL 0x042UL
  15. #define MBOX0 0x080UL
  16. #define MBOX1 0x082UL
  17. #define MBOX2 0x084UL
  18. #define MBOX3 0x086UL
  19. #define MBOX4 0x088UL
  20. #define MBOX5 0x08aUL
  21. #define CPU_CMD 0x214UL
  22. #define CPU_ORIDE 0x224UL
  23. #define CPU_PCTRL 0x272UL
  24. #define CPU_PDIFF 0x276UL
  25. #define RISC_PSR 0x420UL
  26. #define RISC_MTREG 0x42EUL
  27. #define HCCTRL 0x440UL
  28. /* SCSI parameters for this driver. */
  29. #define MAX_TARGETS 16
  30. #define MAX_LUNS 8
  31. /* With the qlogic interface, every queue slot can hold a SCSI
  32. * command with up to 4 scatter/gather entries. If we need more
  33. * than 4 entries, continuation entries can be used that hold
  34. * another 7 entries each. Unlike for other drivers, this means
  35. * that the maximum number of scatter/gather entries we can
  36. * support at any given time is a function of the number of queue
  37. * slots available. That is, host->can_queue and host->sg_tablesize
  38. * are dynamic and _not_ independent. This all works fine because
  39. * requests are queued serially and the scatter/gather limit is
  40. * determined for each queue request anew.
  41. */
  42. #define QLOGICPTI_REQ_QUEUE_LEN 255 /* must be power of two - 1 */
  43. #define QLOGICPTI_MAX_SG(ql) (4 + (((ql) > 0) ? 7*((ql) - 1) : 0))
  44. /* mailbox command complete status codes */
  45. #define MBOX_COMMAND_COMPLETE 0x4000
  46. #define INVALID_COMMAND 0x4001
  47. #define HOST_INTERFACE_ERROR 0x4002
  48. #define TEST_FAILED 0x4003
  49. #define COMMAND_ERROR 0x4005
  50. #define COMMAND_PARAM_ERROR 0x4006
  51. /* async event status codes */
  52. #define ASYNC_SCSI_BUS_RESET 0x8001
  53. #define SYSTEM_ERROR 0x8002
  54. #define REQUEST_TRANSFER_ERROR 0x8003
  55. #define RESPONSE_TRANSFER_ERROR 0x8004
  56. #define REQUEST_QUEUE_WAKEUP 0x8005
  57. #define EXECUTION_TIMEOUT_RESET 0x8006
  58. /* Am I fucking pedantic or what? */
  59. struct Entry_header {
  60. #ifdef __BIG_ENDIAN
  61. u8 entry_cnt;
  62. u8 entry_type;
  63. u8 flags;
  64. u8 sys_def_1;
  65. #else /* __LITTLE_ENDIAN */
  66. u8 entry_type;
  67. u8 entry_cnt;
  68. u8 sys_def_1;
  69. u8 flags;
  70. #endif
  71. };
  72. /* entry header type commands */
  73. #define ENTRY_COMMAND 1
  74. #define ENTRY_CONTINUATION 2
  75. #define ENTRY_STATUS 3
  76. #define ENTRY_MARKER 4
  77. #define ENTRY_EXTENDED_COMMAND 5
  78. /* entry header flag definitions */
  79. #define EFLAG_CONTINUATION 1
  80. #define EFLAG_BUSY 2
  81. #define EFLAG_BAD_HEADER 4
  82. #define EFLAG_BAD_PAYLOAD 8
  83. struct dataseg {
  84. u32 d_base;
  85. u32 d_count;
  86. };
  87. struct Command_Entry {
  88. struct Entry_header hdr;
  89. u32 handle;
  90. #ifdef __BIG_ENDIAN
  91. u8 target_id;
  92. u8 target_lun;
  93. #else /* __LITTLE_ENDIAN */
  94. u8 target_lun;
  95. u8 target_id;
  96. #endif
  97. u16 cdb_length;
  98. u16 control_flags;
  99. u16 rsvd;
  100. u16 time_out;
  101. u16 segment_cnt;
  102. u8 cdb[12];
  103. struct dataseg dataseg[4];
  104. };
  105. /* command entry control flag definitions */
  106. #define CFLAG_NODISC 0x01
  107. #define CFLAG_HEAD_TAG 0x02
  108. #define CFLAG_ORDERED_TAG 0x04
  109. #define CFLAG_SIMPLE_TAG 0x08
  110. #define CFLAG_TAR_RTN 0x10
  111. #define CFLAG_READ 0x20
  112. #define CFLAG_WRITE 0x40
  113. struct Ext_Command_Entry {
  114. struct Entry_header hdr;
  115. u32 handle;
  116. #ifdef __BIG_ENDIAN
  117. u8 target_id;
  118. u8 target_lun;
  119. #else /* __LITTLE_ENDIAN */
  120. u8 target_lun;
  121. u8 target_id;
  122. #endif
  123. u16 cdb_length;
  124. u16 control_flags;
  125. u16 rsvd;
  126. u16 time_out;
  127. u16 segment_cnt;
  128. u8 cdb[44];
  129. };
  130. struct Continuation_Entry {
  131. struct Entry_header hdr;
  132. u32 reserved;
  133. struct dataseg dataseg[7];
  134. };
  135. struct Marker_Entry {
  136. struct Entry_header hdr;
  137. u32 reserved;
  138. #ifdef __BIG_ENDIAN
  139. u8 target_id;
  140. u8 target_lun;
  141. #else /* __LITTLE_ENDIAN */
  142. u8 target_lun;
  143. u8 target_id;
  144. #endif
  145. #ifdef __BIG_ENDIAN
  146. u8 rsvd;
  147. u8 modifier;
  148. #else /* __LITTLE_ENDIAN */
  149. u8 modifier;
  150. u8 rsvd;
  151. #endif
  152. u8 rsvds[52];
  153. };
  154. /* marker entry modifier definitions */
  155. #define SYNC_DEVICE 0
  156. #define SYNC_TARGET 1
  157. #define SYNC_ALL 2
  158. struct Status_Entry {
  159. struct Entry_header hdr;
  160. u32 handle;
  161. u16 scsi_status;
  162. u16 completion_status;
  163. u16 state_flags;
  164. u16 status_flags;
  165. u16 time;
  166. u16 req_sense_len;
  167. u32 residual;
  168. u8 rsvd[8];
  169. u8 req_sense_data[32];
  170. };
  171. /* status entry completion status definitions */
  172. #define CS_COMPLETE 0x0000
  173. #define CS_INCOMPLETE 0x0001
  174. #define CS_DMA_ERROR 0x0002
  175. #define CS_TRANSPORT_ERROR 0x0003
  176. #define CS_RESET_OCCURRED 0x0004
  177. #define CS_ABORTED 0x0005
  178. #define CS_TIMEOUT 0x0006
  179. #define CS_DATA_OVERRUN 0x0007
  180. #define CS_COMMAND_OVERRUN 0x0008
  181. #define CS_STATUS_OVERRUN 0x0009
  182. #define CS_BAD_MESSAGE 0x000a
  183. #define CS_NO_MESSAGE_OUT 0x000b
  184. #define CS_EXT_ID_FAILED 0x000c
  185. #define CS_IDE_MSG_FAILED 0x000d
  186. #define CS_ABORT_MSG_FAILED 0x000e
  187. #define CS_REJECT_MSG_FAILED 0x000f
  188. #define CS_NOP_MSG_FAILED 0x0010
  189. #define CS_PARITY_ERROR_MSG_FAILED 0x0011
  190. #define CS_DEVICE_RESET_MSG_FAILED 0x0012
  191. #define CS_ID_MSG_FAILED 0x0013
  192. #define CS_UNEXP_BUS_FREE 0x0014
  193. #define CS_DATA_UNDERRUN 0x0015
  194. #define CS_BUS_RESET 0x001c
  195. /* status entry state flag definitions */
  196. #define SF_GOT_BUS 0x0100
  197. #define SF_GOT_TARGET 0x0200
  198. #define SF_SENT_CDB 0x0400
  199. #define SF_TRANSFERRED_DATA 0x0800
  200. #define SF_GOT_STATUS 0x1000
  201. #define SF_GOT_SENSE 0x2000
  202. /* status entry status flag definitions */
  203. #define STF_DISCONNECT 0x0001
  204. #define STF_SYNCHRONOUS 0x0002
  205. #define STF_PARITY_ERROR 0x0004
  206. #define STF_BUS_RESET 0x0008
  207. #define STF_DEVICE_RESET 0x0010
  208. #define STF_ABORTED 0x0020
  209. #define STF_TIMEOUT 0x0040
  210. #define STF_NEGOTIATION 0x0080
  211. /* mailbox commands */
  212. #define MBOX_NO_OP 0x0000
  213. #define MBOX_LOAD_RAM 0x0001
  214. #define MBOX_EXEC_FIRMWARE 0x0002
  215. #define MBOX_DUMP_RAM 0x0003
  216. #define MBOX_WRITE_RAM_WORD 0x0004
  217. #define MBOX_READ_RAM_WORD 0x0005
  218. #define MBOX_MAILBOX_REG_TEST 0x0006
  219. #define MBOX_VERIFY_CHECKSUM 0x0007
  220. #define MBOX_ABOUT_FIRMWARE 0x0008
  221. #define MBOX_CHECK_FIRMWARE 0x000e
  222. #define MBOX_INIT_REQ_QUEUE 0x0010
  223. #define MBOX_INIT_RES_QUEUE 0x0011
  224. #define MBOX_EXECUTE_IOCB 0x0012
  225. #define MBOX_WAKE_UP 0x0013
  226. #define MBOX_STOP_FIRMWARE 0x0014
  227. #define MBOX_ABORT 0x0015
  228. #define MBOX_ABORT_DEVICE 0x0016
  229. #define MBOX_ABORT_TARGET 0x0017
  230. #define MBOX_BUS_RESET 0x0018
  231. #define MBOX_STOP_QUEUE 0x0019
  232. #define MBOX_START_QUEUE 0x001a
  233. #define MBOX_SINGLE_STEP_QUEUE 0x001b
  234. #define MBOX_ABORT_QUEUE 0x001c
  235. #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
  236. #define MBOX_GET_FIRMWARE_STATUS 0x001f
  237. #define MBOX_GET_INIT_SCSI_ID 0x0020
  238. #define MBOX_GET_SELECT_TIMEOUT 0x0021
  239. #define MBOX_GET_RETRY_COUNT 0x0022
  240. #define MBOX_GET_TAG_AGE_LIMIT 0x0023
  241. #define MBOX_GET_CLOCK_RATE 0x0024
  242. #define MBOX_GET_ACT_NEG_STATE 0x0025
  243. #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
  244. #define MBOX_GET_SBUS_PARAMS 0x0027
  245. #define MBOX_GET_TARGET_PARAMS 0x0028
  246. #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
  247. #define MBOX_SET_INIT_SCSI_ID 0x0030
  248. #define MBOX_SET_SELECT_TIMEOUT 0x0031
  249. #define MBOX_SET_RETRY_COUNT 0x0032
  250. #define MBOX_SET_TAG_AGE_LIMIT 0x0033
  251. #define MBOX_SET_CLOCK_RATE 0x0034
  252. #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
  253. #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
  254. #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
  255. #define MBOX_SET_TARGET_PARAMS 0x0038
  256. #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
  257. struct host_param {
  258. u_short initiator_scsi_id;
  259. u_short bus_reset_delay;
  260. u_short retry_count;
  261. u_short retry_delay;
  262. u_short async_data_setup_time;
  263. u_short req_ack_active_negation;
  264. u_short data_line_active_negation;
  265. u_short data_dma_burst_enable;
  266. u_short command_dma_burst_enable;
  267. u_short tag_aging;
  268. u_short selection_timeout;
  269. u_short max_queue_depth;
  270. };
  271. /*
  272. * Device Flags:
  273. *
  274. * Bit Name
  275. * ---------
  276. * 7 Disconnect Privilege
  277. * 6 Parity Checking
  278. * 5 Wide Data Transfers
  279. * 4 Synchronous Data Transfers
  280. * 3 Tagged Queuing
  281. * 2 Automatic Request Sense
  282. * 1 Stop Queue on Check Condition
  283. * 0 Renegotiate on Error
  284. */
  285. struct dev_param {
  286. u_short device_flags;
  287. u_short execution_throttle;
  288. u_short synchronous_period;
  289. u_short synchronous_offset;
  290. u_short device_enable;
  291. u_short reserved; /* pad */
  292. };
  293. /*
  294. * The result queue can be quite a bit smaller since continuation entries
  295. * do not show up there:
  296. */
  297. #define RES_QUEUE_LEN 255 /* Must be power of two - 1 */
  298. #define QUEUE_ENTRY_LEN 64
  299. #define NEXT_REQ_PTR(wheee) (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN)
  300. #define NEXT_RES_PTR(wheee) (((wheee) + 1) & RES_QUEUE_LEN)
  301. #define PREV_REQ_PTR(wheee) (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN)
  302. #define PREV_RES_PTR(wheee) (((wheee) - 1) & RES_QUEUE_LEN)
  303. struct pti_queue_entry {
  304. char __opaque[QUEUE_ENTRY_LEN];
  305. };
  306. struct scsi_cmnd;
  307. /* Software state for the driver. */
  308. struct qlogicpti {
  309. /* These are the hot elements in the cache, so they come first. */
  310. void __iomem *qregs; /* Adapter registers */
  311. struct pti_queue_entry *res_cpu; /* Ptr to RESPONSE bufs (CPU) */
  312. struct pti_queue_entry *req_cpu; /* Ptr to REQUEST bufs (CPU) */
  313. u_int req_in_ptr; /* index of next request slot */
  314. u_int res_out_ptr; /* index of next result slot */
  315. long send_marker; /* must we send a marker? */
  316. struct platform_device *op;
  317. unsigned long __pad;
  318. int cmd_count[MAX_TARGETS];
  319. unsigned long tag_ages[MAX_TARGETS];
  320. /* The cmd->handler is only 32-bits, so that things work even on monster
  321. * Ex000 sparc64 machines with >4GB of ram we just keep track of the
  322. * scsi command pointers here. This is essentially what Matt Jacob does. -DaveM
  323. */
  324. struct scsi_cmnd *cmd_slots[QLOGICPTI_REQ_QUEUE_LEN + 1];
  325. /* The rest of the elements are unimportant for performance. */
  326. struct qlogicpti *next;
  327. dma_addr_t res_dvma; /* Ptr to RESPONSE bufs (DVMA)*/
  328. dma_addr_t req_dvma; /* Ptr to REQUEST bufs (DVMA) */
  329. u_char fware_majrev, fware_minrev, fware_micrev;
  330. struct Scsi_Host *qhost;
  331. int qpti_id;
  332. int scsi_id;
  333. int prom_node;
  334. int irq;
  335. char differential, ultra, clock;
  336. unsigned char bursts;
  337. struct host_param host_param;
  338. struct dev_param dev_param[MAX_TARGETS];
  339. void __iomem *sreg;
  340. #define SREG_TPOWER 0x80 /* State of termpwr */
  341. #define SREG_FUSE 0x40 /* State of on board fuse */
  342. #define SREG_PDISAB 0x20 /* Disable state for power on */
  343. #define SREG_DSENSE 0x10 /* Sense for differential */
  344. #define SREG_IMASK 0x0c /* Interrupt level */
  345. #define SREG_SPMASK 0x03 /* Mask for switch pack */
  346. unsigned char swsreg;
  347. unsigned int
  348. gotirq : 1, /* this instance got an irq */
  349. is_pti : 1; /* Non-zero if this is a PTI board. */
  350. };
  351. /* How to twiddle them bits... */
  352. /* SBUS config register one. */
  353. #define SBUS_CFG1_EPAR 0x0100 /* Enable parity checking */
  354. #define SBUS_CFG1_FMASK 0x00f0 /* Forth code cycle mask */
  355. #define SBUS_CFG1_BENAB 0x0004 /* Burst dvma enable */
  356. #define SBUS_CFG1_B64 0x0003 /* Enable 64byte bursts */
  357. #define SBUS_CFG1_B32 0x0002 /* Enable 32byte bursts */
  358. #define SBUS_CFG1_B16 0x0001 /* Enable 16byte bursts */
  359. #define SBUS_CFG1_B8 0x0008 /* Enable 8byte bursts */
  360. /* SBUS control register */
  361. #define SBUS_CTRL_EDIRQ 0x0020 /* Enable Data DVMA Interrupts */
  362. #define SBUS_CTRL_ECIRQ 0x0010 /* Enable Command DVMA Interrupts */
  363. #define SBUS_CTRL_ESIRQ 0x0008 /* Enable SCSI Processor Interrupts */
  364. #define SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */
  365. #define SBUS_CTRL_GENAB 0x0002 /* Global Interrupt Enable */
  366. #define SBUS_CTRL_RESET 0x0001 /* Soft Reset */
  367. /* SBUS status register */
  368. #define SBUS_STAT_DINT 0x0020 /* Data DVMA IRQ pending */
  369. #define SBUS_STAT_CINT 0x0010 /* Command DVMA IRQ pending */
  370. #define SBUS_STAT_SINT 0x0008 /* SCSI Processor IRQ pending */
  371. #define SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */
  372. #define SBUS_STAT_GINT 0x0002 /* Global IRQ pending */
  373. /* SBUS semaphore register */
  374. #define SBUS_SEMAPHORE_STAT 0x0002 /* Semaphore status bit */
  375. #define SBUS_SEMAPHORE_LCK 0x0001 /* Semaphore lock bit */
  376. /* DVMA control register */
  377. #define DMA_CTRL_CSUSPEND 0x0010 /* DMA channel suspend */
  378. #define DMA_CTRL_CCLEAR 0x0008 /* DMA channel clear and reset */
  379. #define DMA_CTRL_FCLEAR 0x0004 /* DMA fifo clear */
  380. #define DMA_CTRL_CIRQ 0x0002 /* DMA irq clear */
  381. #define DMA_CTRL_DMASTART 0x0001 /* DMA transfer start */
  382. /* SCSI processor override register */
  383. #define CPU_ORIDE_ETRIG 0x8000 /* External trigger enable */
  384. #define CPU_ORIDE_STEP 0x4000 /* Single step mode enable */
  385. #define CPU_ORIDE_BKPT 0x2000 /* Breakpoint reg enable */
  386. #define CPU_ORIDE_PWRITE 0x1000 /* SCSI pin write enable */
  387. #define CPU_ORIDE_OFORCE 0x0800 /* Force outputs on */
  388. #define CPU_ORIDE_LBACK 0x0400 /* SCSI loopback enable */
  389. #define CPU_ORIDE_PTEST 0x0200 /* Parity test enable */
  390. #define CPU_ORIDE_TENAB 0x0100 /* SCSI pins tristate enable */
  391. #define CPU_ORIDE_TPINS 0x0080 /* SCSI pins enable */
  392. #define CPU_ORIDE_FRESET 0x0008 /* FIFO reset */
  393. #define CPU_ORIDE_CTERM 0x0004 /* Command terminate */
  394. #define CPU_ORIDE_RREG 0x0002 /* Reset SCSI processor regs */
  395. #define CPU_ORIDE_RMOD 0x0001 /* Reset SCSI processor module */
  396. /* SCSI processor commands */
  397. #define CPU_CMD_BRESET 0x300b /* Reset SCSI bus */
  398. /* SCSI processor pin control register */
  399. #define CPU_PCTRL_PVALID 0x8000 /* Phase bits are valid */
  400. #define CPU_PCTRL_PHI 0x0400 /* Parity bit high */
  401. #define CPU_PCTRL_PLO 0x0200 /* Parity bit low */
  402. #define CPU_PCTRL_REQ 0x0100 /* REQ bus signal */
  403. #define CPU_PCTRL_ACK 0x0080 /* ACK bus signal */
  404. #define CPU_PCTRL_RST 0x0040 /* RST bus signal */
  405. #define CPU_PCTRL_BSY 0x0020 /* BSY bus signal */
  406. #define CPU_PCTRL_SEL 0x0010 /* SEL bus signal */
  407. #define CPU_PCTRL_ATN 0x0008 /* ATN bus signal */
  408. #define CPU_PCTRL_MSG 0x0004 /* MSG bus signal */
  409. #define CPU_PCTRL_CD 0x0002 /* CD bus signal */
  410. #define CPU_PCTRL_IO 0x0001 /* IO bus signal */
  411. /* SCSI processor differential pins register */
  412. #define CPU_PDIFF_SENSE 0x0200 /* Differential sense */
  413. #define CPU_PDIFF_MODE 0x0100 /* Differential mode */
  414. #define CPU_PDIFF_OENAB 0x0080 /* Outputs enable */
  415. #define CPU_PDIFF_PMASK 0x007c /* Differential control pins */
  416. #define CPU_PDIFF_TGT 0x0002 /* Target mode enable */
  417. #define CPU_PDIFF_INIT 0x0001 /* Initiator mode enable */
  418. /* RISC processor status register */
  419. #define RISC_PSR_FTRUE 0x8000 /* Force true */
  420. #define RISC_PSR_LCD 0x4000 /* Loop counter shows done status */
  421. #define RISC_PSR_RIRQ 0x2000 /* RISC irq status */
  422. #define RISC_PSR_TOFLOW 0x1000 /* Timer overflow (rollover) */
  423. #define RISC_PSR_AOFLOW 0x0800 /* Arithmetic overflow */
  424. #define RISC_PSR_AMSB 0x0400 /* Arithmetic big endian */
  425. #define RISC_PSR_ACARRY 0x0200 /* Arithmetic carry */
  426. #define RISC_PSR_AZERO 0x0100 /* Arithmetic zero */
  427. #define RISC_PSR_ULTRA 0x0020 /* Ultra mode */
  428. #define RISC_PSR_DIRQ 0x0010 /* DVMA interrupt */
  429. #define RISC_PSR_SIRQ 0x0008 /* SCSI processor interrupt */
  430. #define RISC_PSR_HIRQ 0x0004 /* Host interrupt */
  431. #define RISC_PSR_IPEND 0x0002 /* Interrupt pending */
  432. #define RISC_PSR_FFALSE 0x0001 /* Force false */
  433. /* RISC processor memory timing register */
  434. #define RISC_MTREG_P1DFLT 0x1200 /* Default read/write timing, pg1 */
  435. #define RISC_MTREG_P0DFLT 0x0012 /* Default read/write timing, pg0 */
  436. #define RISC_MTREG_P1ULTRA 0x2300 /* Ultra-mode rw timing, pg1 */
  437. #define RISC_MTREG_P0ULTRA 0x0023 /* Ultra-mode rw timing, pg0 */
  438. /* Host command/ctrl register */
  439. #define HCCTRL_NOP 0x0000 /* CMD: No operation */
  440. #define HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */
  441. #define HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */
  442. #define HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */
  443. #define HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */
  444. #define HCCTRL_SHIRQ 0x5000 /* CMD: Set host irq */
  445. #define HCCTRL_CHIRQ 0x6000 /* CMD: Clear host irq */
  446. #define HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */
  447. #define HCCTRL_BKPT 0x8000 /* CMD: Breakpoint enables change */
  448. #define HCCTRL_TMODE 0xf000 /* CMD: Enable test mode */
  449. #define HCCTRL_HIRQ 0x0080 /* Host IRQ pending */
  450. #define HCCTRL_RRIP 0x0040 /* RISC cpu reset in happening now */
  451. #define HCCTRL_RPAUSED 0x0020 /* RISC cpu is paused now */
  452. #define HCCTRL_EBENAB 0x0010 /* External breakpoint enable */
  453. #define HCCTRL_B1ENAB 0x0008 /* Breakpoint 1 enable */
  454. #define HCCTRL_B0ENAB 0x0004 /* Breakpoint 0 enable */
  455. /* For our interrupt engine. */
  456. #define for_each_qlogicpti(qp) \
  457. for((qp) = qptichain; (qp); (qp) = (qp)->next)
  458. #endif /* !(_QLOGICPTI_H) */