ql4_nx.c 115 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QLogic iSCSI HBA Driver
  4. * Copyright (c) 2003-2013 QLogic Corporation
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/io.h>
  8. #include <linux/pci.h>
  9. #include <linux/ratelimit.h>
  10. #include "ql4_def.h"
  11. #include "ql4_glbl.h"
  12. #include "ql4_inline.h"
  13. #include <linux/io-64-nonatomic-lo-hi.h>
  14. #define TIMEOUT_100_MS 100
  15. #define MASK(n) DMA_BIT_MASK(n)
  16. #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  17. #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  18. #define MS_WIN(addr) (addr & 0x0ffc0000)
  19. #define QLA82XX_PCI_MN_2M (0)
  20. #define QLA82XX_PCI_MS_2M (0x80000)
  21. #define QLA82XX_PCI_OCM0_2M (0xc0000)
  22. #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  23. #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  24. /* CRB window related */
  25. #define CRB_BLK(off) ((off >> 20) & 0x3f)
  26. #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  27. #define CRB_WINDOW_2M (0x130060)
  28. #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  29. ((off) & 0xf0000))
  30. #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
  31. #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
  32. #define CRB_INDIRECT_2M (0x1e0000UL)
  33. static inline void __iomem *
  34. qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  35. {
  36. if ((off < ha->first_page_group_end) &&
  37. (off >= ha->first_page_group_start))
  38. return (void __iomem *)(ha->nx_pcibase + off);
  39. return NULL;
  40. }
  41. static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
  42. 0x410000AC, 0x410000B8, 0x410000BC };
  43. #define MAX_CRB_XFORM 60
  44. static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  45. static int qla4_8xxx_crb_table_initialized;
  46. #define qla4_8xxx_crb_addr_transform(name) \
  47. (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  48. QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  49. static void
  50. qla4_82xx_crb_addr_transform_setup(void)
  51. {
  52. qla4_8xxx_crb_addr_transform(XDMA);
  53. qla4_8xxx_crb_addr_transform(TIMR);
  54. qla4_8xxx_crb_addr_transform(SRE);
  55. qla4_8xxx_crb_addr_transform(SQN3);
  56. qla4_8xxx_crb_addr_transform(SQN2);
  57. qla4_8xxx_crb_addr_transform(SQN1);
  58. qla4_8xxx_crb_addr_transform(SQN0);
  59. qla4_8xxx_crb_addr_transform(SQS3);
  60. qla4_8xxx_crb_addr_transform(SQS2);
  61. qla4_8xxx_crb_addr_transform(SQS1);
  62. qla4_8xxx_crb_addr_transform(SQS0);
  63. qla4_8xxx_crb_addr_transform(RPMX7);
  64. qla4_8xxx_crb_addr_transform(RPMX6);
  65. qla4_8xxx_crb_addr_transform(RPMX5);
  66. qla4_8xxx_crb_addr_transform(RPMX4);
  67. qla4_8xxx_crb_addr_transform(RPMX3);
  68. qla4_8xxx_crb_addr_transform(RPMX2);
  69. qla4_8xxx_crb_addr_transform(RPMX1);
  70. qla4_8xxx_crb_addr_transform(RPMX0);
  71. qla4_8xxx_crb_addr_transform(ROMUSB);
  72. qla4_8xxx_crb_addr_transform(SN);
  73. qla4_8xxx_crb_addr_transform(QMN);
  74. qla4_8xxx_crb_addr_transform(QMS);
  75. qla4_8xxx_crb_addr_transform(PGNI);
  76. qla4_8xxx_crb_addr_transform(PGND);
  77. qla4_8xxx_crb_addr_transform(PGN3);
  78. qla4_8xxx_crb_addr_transform(PGN2);
  79. qla4_8xxx_crb_addr_transform(PGN1);
  80. qla4_8xxx_crb_addr_transform(PGN0);
  81. qla4_8xxx_crb_addr_transform(PGSI);
  82. qla4_8xxx_crb_addr_transform(PGSD);
  83. qla4_8xxx_crb_addr_transform(PGS3);
  84. qla4_8xxx_crb_addr_transform(PGS2);
  85. qla4_8xxx_crb_addr_transform(PGS1);
  86. qla4_8xxx_crb_addr_transform(PGS0);
  87. qla4_8xxx_crb_addr_transform(PS);
  88. qla4_8xxx_crb_addr_transform(PH);
  89. qla4_8xxx_crb_addr_transform(NIU);
  90. qla4_8xxx_crb_addr_transform(I2Q);
  91. qla4_8xxx_crb_addr_transform(EG);
  92. qla4_8xxx_crb_addr_transform(MN);
  93. qla4_8xxx_crb_addr_transform(MS);
  94. qla4_8xxx_crb_addr_transform(CAS2);
  95. qla4_8xxx_crb_addr_transform(CAS1);
  96. qla4_8xxx_crb_addr_transform(CAS0);
  97. qla4_8xxx_crb_addr_transform(CAM);
  98. qla4_8xxx_crb_addr_transform(C2C1);
  99. qla4_8xxx_crb_addr_transform(C2C0);
  100. qla4_8xxx_crb_addr_transform(SMB);
  101. qla4_8xxx_crb_addr_transform(OCM0);
  102. qla4_8xxx_crb_addr_transform(I2C0);
  103. qla4_8xxx_crb_table_initialized = 1;
  104. }
  105. static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
  106. {{{0, 0, 0, 0} } }, /* 0: PCI */
  107. {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
  108. {1, 0x0110000, 0x0120000, 0x130000},
  109. {1, 0x0120000, 0x0122000, 0x124000},
  110. {1, 0x0130000, 0x0132000, 0x126000},
  111. {1, 0x0140000, 0x0142000, 0x128000},
  112. {1, 0x0150000, 0x0152000, 0x12a000},
  113. {1, 0x0160000, 0x0170000, 0x110000},
  114. {1, 0x0170000, 0x0172000, 0x12e000},
  115. {0, 0x0000000, 0x0000000, 0x000000},
  116. {0, 0x0000000, 0x0000000, 0x000000},
  117. {0, 0x0000000, 0x0000000, 0x000000},
  118. {0, 0x0000000, 0x0000000, 0x000000},
  119. {0, 0x0000000, 0x0000000, 0x000000},
  120. {0, 0x0000000, 0x0000000, 0x000000},
  121. {1, 0x01e0000, 0x01e0800, 0x122000},
  122. {0, 0x0000000, 0x0000000, 0x000000} } },
  123. {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  124. {{{0, 0, 0, 0} } }, /* 3: */
  125. {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  126. {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
  127. {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
  128. {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
  129. {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
  130. {0, 0x0000000, 0x0000000, 0x000000},
  131. {0, 0x0000000, 0x0000000, 0x000000},
  132. {0, 0x0000000, 0x0000000, 0x000000},
  133. {0, 0x0000000, 0x0000000, 0x000000},
  134. {0, 0x0000000, 0x0000000, 0x000000},
  135. {0, 0x0000000, 0x0000000, 0x000000},
  136. {0, 0x0000000, 0x0000000, 0x000000},
  137. {0, 0x0000000, 0x0000000, 0x000000},
  138. {0, 0x0000000, 0x0000000, 0x000000},
  139. {0, 0x0000000, 0x0000000, 0x000000},
  140. {0, 0x0000000, 0x0000000, 0x000000},
  141. {0, 0x0000000, 0x0000000, 0x000000},
  142. {0, 0x0000000, 0x0000000, 0x000000},
  143. {0, 0x0000000, 0x0000000, 0x000000},
  144. {1, 0x08f0000, 0x08f2000, 0x172000} } },
  145. {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
  146. {0, 0x0000000, 0x0000000, 0x000000},
  147. {0, 0x0000000, 0x0000000, 0x000000},
  148. {0, 0x0000000, 0x0000000, 0x000000},
  149. {0, 0x0000000, 0x0000000, 0x000000},
  150. {0, 0x0000000, 0x0000000, 0x000000},
  151. {0, 0x0000000, 0x0000000, 0x000000},
  152. {0, 0x0000000, 0x0000000, 0x000000},
  153. {0, 0x0000000, 0x0000000, 0x000000},
  154. {0, 0x0000000, 0x0000000, 0x000000},
  155. {0, 0x0000000, 0x0000000, 0x000000},
  156. {0, 0x0000000, 0x0000000, 0x000000},
  157. {0, 0x0000000, 0x0000000, 0x000000},
  158. {0, 0x0000000, 0x0000000, 0x000000},
  159. {0, 0x0000000, 0x0000000, 0x000000},
  160. {1, 0x09f0000, 0x09f2000, 0x176000} } },
  161. {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
  162. {0, 0x0000000, 0x0000000, 0x000000},
  163. {0, 0x0000000, 0x0000000, 0x000000},
  164. {0, 0x0000000, 0x0000000, 0x000000},
  165. {0, 0x0000000, 0x0000000, 0x000000},
  166. {0, 0x0000000, 0x0000000, 0x000000},
  167. {0, 0x0000000, 0x0000000, 0x000000},
  168. {0, 0x0000000, 0x0000000, 0x000000},
  169. {0, 0x0000000, 0x0000000, 0x000000},
  170. {0, 0x0000000, 0x0000000, 0x000000},
  171. {0, 0x0000000, 0x0000000, 0x000000},
  172. {0, 0x0000000, 0x0000000, 0x000000},
  173. {0, 0x0000000, 0x0000000, 0x000000},
  174. {0, 0x0000000, 0x0000000, 0x000000},
  175. {0, 0x0000000, 0x0000000, 0x000000},
  176. {1, 0x0af0000, 0x0af2000, 0x17a000} } },
  177. {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
  178. {0, 0x0000000, 0x0000000, 0x000000},
  179. {0, 0x0000000, 0x0000000, 0x000000},
  180. {0, 0x0000000, 0x0000000, 0x000000},
  181. {0, 0x0000000, 0x0000000, 0x000000},
  182. {0, 0x0000000, 0x0000000, 0x000000},
  183. {0, 0x0000000, 0x0000000, 0x000000},
  184. {0, 0x0000000, 0x0000000, 0x000000},
  185. {0, 0x0000000, 0x0000000, 0x000000},
  186. {0, 0x0000000, 0x0000000, 0x000000},
  187. {0, 0x0000000, 0x0000000, 0x000000},
  188. {0, 0x0000000, 0x0000000, 0x000000},
  189. {0, 0x0000000, 0x0000000, 0x000000},
  190. {0, 0x0000000, 0x0000000, 0x000000},
  191. {0, 0x0000000, 0x0000000, 0x000000},
  192. {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
  193. {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
  194. {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
  195. {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
  196. {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
  197. {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
  198. {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
  199. {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
  200. {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
  201. {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
  202. {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
  203. {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
  204. {{{0, 0, 0, 0} } }, /* 23: */
  205. {{{0, 0, 0, 0} } }, /* 24: */
  206. {{{0, 0, 0, 0} } }, /* 25: */
  207. {{{0, 0, 0, 0} } }, /* 26: */
  208. {{{0, 0, 0, 0} } }, /* 27: */
  209. {{{0, 0, 0, 0} } }, /* 28: */
  210. {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
  211. {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
  212. {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
  213. {{{0} } }, /* 32: PCI */
  214. {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
  215. {1, 0x2110000, 0x2120000, 0x130000},
  216. {1, 0x2120000, 0x2122000, 0x124000},
  217. {1, 0x2130000, 0x2132000, 0x126000},
  218. {1, 0x2140000, 0x2142000, 0x128000},
  219. {1, 0x2150000, 0x2152000, 0x12a000},
  220. {1, 0x2160000, 0x2170000, 0x110000},
  221. {1, 0x2170000, 0x2172000, 0x12e000},
  222. {0, 0x0000000, 0x0000000, 0x000000},
  223. {0, 0x0000000, 0x0000000, 0x000000},
  224. {0, 0x0000000, 0x0000000, 0x000000},
  225. {0, 0x0000000, 0x0000000, 0x000000},
  226. {0, 0x0000000, 0x0000000, 0x000000},
  227. {0, 0x0000000, 0x0000000, 0x000000},
  228. {0, 0x0000000, 0x0000000, 0x000000},
  229. {0, 0x0000000, 0x0000000, 0x000000} } },
  230. {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
  231. {{{0} } }, /* 35: */
  232. {{{0} } }, /* 36: */
  233. {{{0} } }, /* 37: */
  234. {{{0} } }, /* 38: */
  235. {{{0} } }, /* 39: */
  236. {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
  237. {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
  238. {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
  239. {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
  240. {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
  241. {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
  242. {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
  243. {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
  244. {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
  245. {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
  246. {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
  247. {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
  248. {{{0} } }, /* 52: */
  249. {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
  250. {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
  251. {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
  252. {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
  253. {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
  254. {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
  255. {{{0} } }, /* 59: I2C0 */
  256. {{{0} } }, /* 60: I2C1 */
  257. {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
  258. {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
  259. {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
  260. };
  261. /*
  262. * top 12 bits of crb internal address (hub, agent)
  263. */
  264. static unsigned qla4_82xx_crb_hub_agt[64] = {
  265. 0,
  266. QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
  267. QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
  268. QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
  269. 0,
  270. QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
  271. QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
  272. QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
  273. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
  274. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
  275. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
  276. QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
  277. QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
  278. QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
  279. QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
  280. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
  281. QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
  282. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
  283. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
  284. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
  285. QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
  286. QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
  287. QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
  288. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
  289. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
  290. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
  291. QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
  292. 0,
  293. QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
  294. QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
  295. 0,
  296. QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
  297. 0,
  298. QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
  299. QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
  300. 0,
  301. 0,
  302. 0,
  303. 0,
  304. 0,
  305. QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
  306. 0,
  307. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
  308. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
  309. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
  310. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
  311. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
  312. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
  313. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
  314. QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
  315. QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
  316. QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
  317. 0,
  318. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
  319. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
  320. QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
  321. QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
  322. 0,
  323. QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
  324. QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
  325. QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
  326. 0,
  327. QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
  328. 0,
  329. };
  330. /* Device states */
  331. static char *qdev_state[] = {
  332. "Unknown",
  333. "Cold",
  334. "Initializing",
  335. "Ready",
  336. "Need Reset",
  337. "Need Quiescent",
  338. "Failed",
  339. "Quiescent",
  340. };
  341. /*
  342. * In: 'off' is offset from CRB space in 128M pci map
  343. * Out: 'off' is 2M pci map addr
  344. * side effect: lock crb window
  345. */
  346. static void
  347. qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
  348. {
  349. u32 win_read;
  350. ha->crb_win = CRB_HI(*off);
  351. writel(ha->crb_win,
  352. (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  353. /* Read back value to make sure write has gone through before trying
  354. * to use it. */
  355. win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  356. if (win_read != ha->crb_win) {
  357. DEBUG2(ql4_printk(KERN_INFO, ha,
  358. "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
  359. " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
  360. }
  361. *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
  362. }
  363. void
  364. qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
  365. {
  366. unsigned long flags = 0;
  367. int rv;
  368. rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
  369. BUG_ON(rv == -1);
  370. if (rv == 1) {
  371. write_lock_irqsave(&ha->hw_lock, flags);
  372. qla4_82xx_crb_win_lock(ha);
  373. qla4_82xx_pci_set_crbwindow_2M(ha, &off);
  374. }
  375. writel(data, (void __iomem *)off);
  376. if (rv == 1) {
  377. qla4_82xx_crb_win_unlock(ha);
  378. write_unlock_irqrestore(&ha->hw_lock, flags);
  379. }
  380. }
  381. uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
  382. {
  383. unsigned long flags = 0;
  384. int rv;
  385. u32 data;
  386. rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
  387. BUG_ON(rv == -1);
  388. if (rv == 1) {
  389. write_lock_irqsave(&ha->hw_lock, flags);
  390. qla4_82xx_crb_win_lock(ha);
  391. qla4_82xx_pci_set_crbwindow_2M(ha, &off);
  392. }
  393. data = readl((void __iomem *)off);
  394. if (rv == 1) {
  395. qla4_82xx_crb_win_unlock(ha);
  396. write_unlock_irqrestore(&ha->hw_lock, flags);
  397. }
  398. return data;
  399. }
  400. /* Minidump related functions */
  401. int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
  402. {
  403. uint32_t win_read, off_value;
  404. int rval = QLA_SUCCESS;
  405. off_value = off & 0xFFFF0000;
  406. writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  407. /*
  408. * Read back value to make sure write has gone through before trying
  409. * to use it.
  410. */
  411. win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  412. if (win_read != off_value) {
  413. DEBUG2(ql4_printk(KERN_INFO, ha,
  414. "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
  415. __func__, off_value, win_read, off));
  416. rval = QLA_ERROR;
  417. } else {
  418. off_value = off & 0x0000FFFF;
  419. *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
  420. ha->nx_pcibase));
  421. }
  422. return rval;
  423. }
  424. int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
  425. {
  426. uint32_t win_read, off_value;
  427. int rval = QLA_SUCCESS;
  428. off_value = off & 0xFFFF0000;
  429. writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  430. /* Read back value to make sure write has gone through before trying
  431. * to use it.
  432. */
  433. win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
  434. if (win_read != off_value) {
  435. DEBUG2(ql4_printk(KERN_INFO, ha,
  436. "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
  437. __func__, off_value, win_read, off));
  438. rval = QLA_ERROR;
  439. } else {
  440. off_value = off & 0x0000FFFF;
  441. writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
  442. ha->nx_pcibase));
  443. }
  444. return rval;
  445. }
  446. #define CRB_WIN_LOCK_TIMEOUT 100000000
  447. int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
  448. {
  449. int i;
  450. int done = 0, timeout = 0;
  451. while (!done) {
  452. /* acquire semaphore3 from PCI HW block */
  453. done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
  454. if (done == 1)
  455. break;
  456. if (timeout >= CRB_WIN_LOCK_TIMEOUT)
  457. return -1;
  458. timeout++;
  459. /* Yield CPU */
  460. if (!in_interrupt())
  461. schedule();
  462. else {
  463. for (i = 0; i < 20; i++)
  464. cpu_relax(); /*This a nop instr on i386*/
  465. }
  466. }
  467. qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
  468. return 0;
  469. }
  470. void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
  471. {
  472. qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
  473. }
  474. #define IDC_LOCK_TIMEOUT 100000000
  475. /**
  476. * qla4_82xx_idc_lock - hw_lock
  477. * @ha: pointer to adapter structure
  478. *
  479. * General purpose lock used to synchronize access to
  480. * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
  481. **/
  482. int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
  483. {
  484. int i;
  485. int done = 0, timeout = 0;
  486. while (!done) {
  487. /* acquire semaphore5 from PCI HW block */
  488. done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
  489. if (done == 1)
  490. break;
  491. if (timeout >= IDC_LOCK_TIMEOUT)
  492. return -1;
  493. timeout++;
  494. /* Yield CPU */
  495. if (!in_interrupt())
  496. schedule();
  497. else {
  498. for (i = 0; i < 20; i++)
  499. cpu_relax(); /*This a nop instr on i386*/
  500. }
  501. }
  502. return 0;
  503. }
  504. void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
  505. {
  506. qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
  507. }
  508. int
  509. qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
  510. {
  511. struct crb_128M_2M_sub_block_map *m;
  512. if (*off >= QLA82XX_CRB_MAX)
  513. return -1;
  514. if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
  515. *off = (*off - QLA82XX_PCI_CAMQM) +
  516. QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
  517. return 0;
  518. }
  519. if (*off < QLA82XX_PCI_CRBSPACE)
  520. return -1;
  521. *off -= QLA82XX_PCI_CRBSPACE;
  522. /*
  523. * Try direct map
  524. */
  525. m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
  526. if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
  527. *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
  528. return 0;
  529. }
  530. /*
  531. * Not in direct map, use crb window
  532. */
  533. return 1;
  534. }
  535. /*
  536. * check memory access boundary.
  537. * used by test agent. support ddr access only for now
  538. */
  539. static unsigned long
  540. qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
  541. unsigned long long addr, int size)
  542. {
  543. if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  544. QLA8XXX_ADDR_DDR_NET_MAX) ||
  545. !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
  546. QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
  547. ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
  548. return 0;
  549. }
  550. return 1;
  551. }
  552. static int qla4_82xx_pci_set_window_warning_count;
  553. static unsigned long
  554. qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
  555. {
  556. int window;
  557. u32 win_read;
  558. if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  559. QLA8XXX_ADDR_DDR_NET_MAX)) {
  560. /* DDR network side */
  561. window = MN_WIN(addr);
  562. ha->ddr_mn_window = window;
  563. qla4_82xx_wr_32(ha, ha->mn_win_crb |
  564. QLA82XX_PCI_CRBSPACE, window);
  565. win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
  566. QLA82XX_PCI_CRBSPACE);
  567. if ((win_read << 17) != window) {
  568. ql4_printk(KERN_WARNING, ha,
  569. "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
  570. __func__, window, win_read);
  571. }
  572. addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
  573. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
  574. QLA8XXX_ADDR_OCM0_MAX)) {
  575. unsigned int temp1;
  576. /* if bits 19:18&17:11 are on */
  577. if ((addr & 0x00ff800) == 0xff800) {
  578. printk("%s: QM access not handled.\n", __func__);
  579. addr = -1UL;
  580. }
  581. window = OCM_WIN(addr);
  582. ha->ddr_mn_window = window;
  583. qla4_82xx_wr_32(ha, ha->mn_win_crb |
  584. QLA82XX_PCI_CRBSPACE, window);
  585. win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
  586. QLA82XX_PCI_CRBSPACE);
  587. temp1 = ((window & 0x1FF) << 7) |
  588. ((window & 0x0FFFE0000) >> 17);
  589. if (win_read != temp1) {
  590. printk("%s: Written OCMwin (0x%x) != Read"
  591. " OCMwin (0x%x)\n", __func__, temp1, win_read);
  592. }
  593. addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
  594. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
  595. QLA82XX_P3_ADDR_QDR_NET_MAX)) {
  596. /* QDR network side */
  597. window = MS_WIN(addr);
  598. ha->qdr_sn_window = window;
  599. qla4_82xx_wr_32(ha, ha->ms_win_crb |
  600. QLA82XX_PCI_CRBSPACE, window);
  601. win_read = qla4_82xx_rd_32(ha,
  602. ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
  603. if (win_read != window) {
  604. printk("%s: Written MSwin (0x%x) != Read "
  605. "MSwin (0x%x)\n", __func__, window, win_read);
  606. }
  607. addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
  608. } else {
  609. /*
  610. * peg gdb frequently accesses memory that doesn't exist,
  611. * this limits the chit chat so debugging isn't slowed down.
  612. */
  613. if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
  614. (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
  615. printk("%s: Warning:%s Unknown address range!\n",
  616. __func__, DRIVER_NAME);
  617. }
  618. addr = -1UL;
  619. }
  620. return addr;
  621. }
  622. /* check if address is in the same windows as the previous access */
  623. static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
  624. unsigned long long addr)
  625. {
  626. int window;
  627. unsigned long long qdr_max;
  628. qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
  629. if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  630. QLA8XXX_ADDR_DDR_NET_MAX)) {
  631. /* DDR network side */
  632. BUG(); /* MN access can not come here */
  633. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
  634. QLA8XXX_ADDR_OCM0_MAX)) {
  635. return 1;
  636. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
  637. QLA8XXX_ADDR_OCM1_MAX)) {
  638. return 1;
  639. } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
  640. qdr_max)) {
  641. /* QDR network side */
  642. window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
  643. if (ha->qdr_sn_window == window)
  644. return 1;
  645. }
  646. return 0;
  647. }
  648. static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
  649. u64 off, void *data, int size)
  650. {
  651. unsigned long flags;
  652. void __iomem *addr;
  653. int ret = 0;
  654. u64 start;
  655. void __iomem *mem_ptr = NULL;
  656. unsigned long mem_base;
  657. unsigned long mem_page;
  658. write_lock_irqsave(&ha->hw_lock, flags);
  659. /*
  660. * If attempting to access unknown address or straddle hw windows,
  661. * do not access.
  662. */
  663. start = qla4_82xx_pci_set_window(ha, off);
  664. if ((start == -1UL) ||
  665. (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
  666. write_unlock_irqrestore(&ha->hw_lock, flags);
  667. printk(KERN_ERR"%s out of bound pci memory access. "
  668. "offset is 0x%llx\n", DRIVER_NAME, off);
  669. return -1;
  670. }
  671. addr = qla4_8xxx_pci_base_offsetfset(ha, start);
  672. if (!addr) {
  673. write_unlock_irqrestore(&ha->hw_lock, flags);
  674. mem_base = pci_resource_start(ha->pdev, 0);
  675. mem_page = start & PAGE_MASK;
  676. /* Map two pages whenever user tries to access addresses in two
  677. consecutive pages.
  678. */
  679. if (mem_page != ((start + size - 1) & PAGE_MASK))
  680. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
  681. else
  682. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
  683. if (mem_ptr == NULL) {
  684. *(u8 *)data = 0;
  685. return -1;
  686. }
  687. addr = mem_ptr;
  688. addr += start & (PAGE_SIZE - 1);
  689. write_lock_irqsave(&ha->hw_lock, flags);
  690. }
  691. switch (size) {
  692. case 1:
  693. *(u8 *)data = readb(addr);
  694. break;
  695. case 2:
  696. *(u16 *)data = readw(addr);
  697. break;
  698. case 4:
  699. *(u32 *)data = readl(addr);
  700. break;
  701. case 8:
  702. *(u64 *)data = readq(addr);
  703. break;
  704. default:
  705. ret = -1;
  706. break;
  707. }
  708. write_unlock_irqrestore(&ha->hw_lock, flags);
  709. if (mem_ptr)
  710. iounmap(mem_ptr);
  711. return ret;
  712. }
  713. static int
  714. qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
  715. void *data, int size)
  716. {
  717. unsigned long flags;
  718. void __iomem *addr;
  719. int ret = 0;
  720. u64 start;
  721. void __iomem *mem_ptr = NULL;
  722. unsigned long mem_base;
  723. unsigned long mem_page;
  724. write_lock_irqsave(&ha->hw_lock, flags);
  725. /*
  726. * If attempting to access unknown address or straddle hw windows,
  727. * do not access.
  728. */
  729. start = qla4_82xx_pci_set_window(ha, off);
  730. if ((start == -1UL) ||
  731. (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
  732. write_unlock_irqrestore(&ha->hw_lock, flags);
  733. printk(KERN_ERR"%s out of bound pci memory access. "
  734. "offset is 0x%llx\n", DRIVER_NAME, off);
  735. return -1;
  736. }
  737. addr = qla4_8xxx_pci_base_offsetfset(ha, start);
  738. if (!addr) {
  739. write_unlock_irqrestore(&ha->hw_lock, flags);
  740. mem_base = pci_resource_start(ha->pdev, 0);
  741. mem_page = start & PAGE_MASK;
  742. /* Map two pages whenever user tries to access addresses in two
  743. consecutive pages.
  744. */
  745. if (mem_page != ((start + size - 1) & PAGE_MASK))
  746. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
  747. else
  748. mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
  749. if (mem_ptr == NULL)
  750. return -1;
  751. addr = mem_ptr;
  752. addr += start & (PAGE_SIZE - 1);
  753. write_lock_irqsave(&ha->hw_lock, flags);
  754. }
  755. switch (size) {
  756. case 1:
  757. writeb(*(u8 *)data, addr);
  758. break;
  759. case 2:
  760. writew(*(u16 *)data, addr);
  761. break;
  762. case 4:
  763. writel(*(u32 *)data, addr);
  764. break;
  765. case 8:
  766. writeq(*(u64 *)data, addr);
  767. break;
  768. default:
  769. ret = -1;
  770. break;
  771. }
  772. write_unlock_irqrestore(&ha->hw_lock, flags);
  773. if (mem_ptr)
  774. iounmap(mem_ptr);
  775. return ret;
  776. }
  777. #define MTU_FUDGE_FACTOR 100
  778. static unsigned long
  779. qla4_82xx_decode_crb_addr(unsigned long addr)
  780. {
  781. int i;
  782. unsigned long base_addr, offset, pci_base;
  783. if (!qla4_8xxx_crb_table_initialized)
  784. qla4_82xx_crb_addr_transform_setup();
  785. pci_base = ADDR_ERROR;
  786. base_addr = addr & 0xfff00000;
  787. offset = addr & 0x000fffff;
  788. for (i = 0; i < MAX_CRB_XFORM; i++) {
  789. if (crb_addr_xform[i] == base_addr) {
  790. pci_base = i << 20;
  791. break;
  792. }
  793. }
  794. if (pci_base == ADDR_ERROR)
  795. return pci_base;
  796. else
  797. return pci_base + offset;
  798. }
  799. static long rom_max_timeout = 100;
  800. static long qla4_82xx_rom_lock_timeout = 100;
  801. static int
  802. qla4_82xx_rom_lock(struct scsi_qla_host *ha)
  803. {
  804. int i;
  805. int done = 0, timeout = 0;
  806. while (!done) {
  807. /* acquire semaphore2 from PCI HW block */
  808. done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
  809. if (done == 1)
  810. break;
  811. if (timeout >= qla4_82xx_rom_lock_timeout)
  812. return -1;
  813. timeout++;
  814. /* Yield CPU */
  815. if (!in_interrupt())
  816. schedule();
  817. else {
  818. for (i = 0; i < 20; i++)
  819. cpu_relax(); /*This a nop instr on i386*/
  820. }
  821. }
  822. qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  823. return 0;
  824. }
  825. static void
  826. qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
  827. {
  828. qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
  829. }
  830. static int
  831. qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
  832. {
  833. long timeout = 0;
  834. long done = 0 ;
  835. while (done == 0) {
  836. done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
  837. done &= 2;
  838. timeout++;
  839. if (timeout >= rom_max_timeout) {
  840. printk("%s: Timeout reached waiting for rom done",
  841. DRIVER_NAME);
  842. return -1;
  843. }
  844. }
  845. return 0;
  846. }
  847. static int
  848. qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
  849. {
  850. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
  851. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  852. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
  853. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  854. if (qla4_82xx_wait_rom_done(ha)) {
  855. printk("%s: Error waiting for rom done\n", DRIVER_NAME);
  856. return -1;
  857. }
  858. /* reset abyte_cnt and dummy_byte_cnt */
  859. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  860. udelay(10);
  861. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
  862. *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
  863. return 0;
  864. }
  865. static int
  866. qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
  867. {
  868. int ret, loops = 0;
  869. while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
  870. udelay(100);
  871. loops++;
  872. }
  873. if (loops >= 50000) {
  874. ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
  875. DRIVER_NAME);
  876. return -1;
  877. }
  878. ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
  879. qla4_82xx_rom_unlock(ha);
  880. return ret;
  881. }
  882. /*
  883. * This routine does CRB initialize sequence
  884. * to put the ISP into operational state
  885. */
  886. static int
  887. qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
  888. {
  889. int addr, val;
  890. int i ;
  891. struct crb_addr_pair *buf;
  892. unsigned long off;
  893. unsigned offset, n;
  894. struct crb_addr_pair {
  895. long addr;
  896. long data;
  897. };
  898. /* Halt all the indiviual PEGs and other blocks of the ISP */
  899. qla4_82xx_rom_lock(ha);
  900. /* disable all I2Q */
  901. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
  902. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
  903. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
  904. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
  905. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
  906. qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
  907. /* disable all niu interrupts */
  908. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
  909. /* disable xge rx/tx */
  910. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
  911. /* disable xg1 rx/tx */
  912. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
  913. /* disable sideband mac */
  914. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
  915. /* disable ap0 mac */
  916. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
  917. /* disable ap1 mac */
  918. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
  919. /* halt sre */
  920. val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
  921. qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
  922. /* halt epg */
  923. qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
  924. /* halt timers */
  925. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
  926. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
  927. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
  928. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
  929. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
  930. qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
  931. /* halt pegs */
  932. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
  933. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
  934. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
  935. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
  936. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
  937. msleep(5);
  938. /* big hammer */
  939. if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
  940. /* don't reset CAM block on reset */
  941. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  942. else
  943. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
  944. qla4_82xx_rom_unlock(ha);
  945. /* Read the signature value from the flash.
  946. * Offset 0: Contain signature (0xcafecafe)
  947. * Offset 4: Offset and number of addr/value pairs
  948. * that present in CRB initialize sequence
  949. */
  950. if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
  951. qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
  952. ql4_printk(KERN_WARNING, ha,
  953. "[ERROR] Reading crb_init area: n: %08x\n", n);
  954. return -1;
  955. }
  956. /* Offset in flash = lower 16 bits
  957. * Number of enteries = upper 16 bits
  958. */
  959. offset = n & 0xffffU;
  960. n = (n >> 16) & 0xffffU;
  961. /* number of addr/value pair should not exceed 1024 enteries */
  962. if (n >= 1024) {
  963. ql4_printk(KERN_WARNING, ha,
  964. "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
  965. DRIVER_NAME, __func__, n);
  966. return -1;
  967. }
  968. ql4_printk(KERN_INFO, ha,
  969. "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
  970. buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  971. if (buf == NULL) {
  972. ql4_printk(KERN_WARNING, ha,
  973. "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
  974. return -1;
  975. }
  976. for (i = 0; i < n; i++) {
  977. if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
  978. qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
  979. 0) {
  980. kfree(buf);
  981. return -1;
  982. }
  983. buf[i].addr = addr;
  984. buf[i].data = val;
  985. }
  986. for (i = 0; i < n; i++) {
  987. /* Translate internal CRB initialization
  988. * address to PCI bus address
  989. */
  990. off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
  991. QLA82XX_PCI_CRBSPACE;
  992. /* Not all CRB addr/value pair to be written,
  993. * some of them are skipped
  994. */
  995. /* skip if LS bit is set*/
  996. if (off & 0x1) {
  997. DEBUG2(ql4_printk(KERN_WARNING, ha,
  998. "Skip CRB init replay for offset = 0x%lx\n", off));
  999. continue;
  1000. }
  1001. /* skipping cold reboot MAGIC */
  1002. if (off == QLA82XX_CAM_RAM(0x1fc))
  1003. continue;
  1004. /* do not reset PCI */
  1005. if (off == (ROMUSB_GLB + 0xbc))
  1006. continue;
  1007. /* skip core clock, so that firmware can increase the clock */
  1008. if (off == (ROMUSB_GLB + 0xc8))
  1009. continue;
  1010. /* skip the function enable register */
  1011. if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
  1012. continue;
  1013. if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
  1014. continue;
  1015. if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
  1016. continue;
  1017. if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
  1018. continue;
  1019. if (off == ADDR_ERROR) {
  1020. ql4_printk(KERN_WARNING, ha,
  1021. "%s: [ERROR] Unknown addr: 0x%08lx\n",
  1022. DRIVER_NAME, buf[i].addr);
  1023. continue;
  1024. }
  1025. qla4_82xx_wr_32(ha, off, buf[i].data);
  1026. /* ISP requires much bigger delay to settle down,
  1027. * else crb_window returns 0xffffffff
  1028. */
  1029. if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
  1030. msleep(1000);
  1031. /* ISP requires millisec delay between
  1032. * successive CRB register updation
  1033. */
  1034. msleep(1);
  1035. }
  1036. kfree(buf);
  1037. /* Resetting the data and instruction cache */
  1038. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
  1039. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
  1040. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
  1041. /* Clear all protocol processing engines */
  1042. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
  1043. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
  1044. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
  1045. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
  1046. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
  1047. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
  1048. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
  1049. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
  1050. return 0;
  1051. }
  1052. /**
  1053. * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
  1054. * @ha: Pointer to adapter structure
  1055. * @addr: Flash address to write to
  1056. * @data: Data to be written
  1057. * @count: word_count to be written
  1058. *
  1059. * Return: On success return QLA_SUCCESS
  1060. * On error return QLA_ERROR
  1061. **/
  1062. int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
  1063. uint32_t *data, uint32_t count)
  1064. {
  1065. int i, j;
  1066. uint32_t agt_ctrl;
  1067. unsigned long flags;
  1068. int ret_val = QLA_SUCCESS;
  1069. /* Only 128-bit aligned access */
  1070. if (addr & 0xF) {
  1071. ret_val = QLA_ERROR;
  1072. goto exit_ms_mem_write;
  1073. }
  1074. write_lock_irqsave(&ha->hw_lock, flags);
  1075. /* Write address */
  1076. ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
  1077. if (ret_val == QLA_ERROR) {
  1078. ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
  1079. __func__);
  1080. goto exit_ms_mem_write_unlock;
  1081. }
  1082. for (i = 0; i < count; i++, addr += 16) {
  1083. if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
  1084. QLA8XXX_ADDR_QDR_NET_MAX)) ||
  1085. (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
  1086. QLA8XXX_ADDR_DDR_NET_MAX)))) {
  1087. ret_val = QLA_ERROR;
  1088. goto exit_ms_mem_write_unlock;
  1089. }
  1090. ret_val = ha->isp_ops->wr_reg_indirect(ha,
  1091. MD_MIU_TEST_AGT_ADDR_LO,
  1092. addr);
  1093. /* Write data */
  1094. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1095. MD_MIU_TEST_AGT_WRDATA_LO,
  1096. *data++);
  1097. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1098. MD_MIU_TEST_AGT_WRDATA_HI,
  1099. *data++);
  1100. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1101. MD_MIU_TEST_AGT_WRDATA_ULO,
  1102. *data++);
  1103. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1104. MD_MIU_TEST_AGT_WRDATA_UHI,
  1105. *data++);
  1106. if (ret_val == QLA_ERROR) {
  1107. ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
  1108. __func__);
  1109. goto exit_ms_mem_write_unlock;
  1110. }
  1111. /* Check write status */
  1112. ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
  1113. MIU_TA_CTL_WRITE_ENABLE);
  1114. ret_val |= ha->isp_ops->wr_reg_indirect(ha,
  1115. MD_MIU_TEST_AGT_CTRL,
  1116. MIU_TA_CTL_WRITE_START);
  1117. if (ret_val == QLA_ERROR) {
  1118. ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
  1119. __func__);
  1120. goto exit_ms_mem_write_unlock;
  1121. }
  1122. for (j = 0; j < MAX_CTL_CHECK; j++) {
  1123. ret_val = ha->isp_ops->rd_reg_indirect(ha,
  1124. MD_MIU_TEST_AGT_CTRL,
  1125. &agt_ctrl);
  1126. if (ret_val == QLA_ERROR) {
  1127. ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
  1128. __func__);
  1129. goto exit_ms_mem_write_unlock;
  1130. }
  1131. if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
  1132. break;
  1133. }
  1134. /* Status check failed */
  1135. if (j >= MAX_CTL_CHECK) {
  1136. printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
  1137. __func__);
  1138. ret_val = QLA_ERROR;
  1139. goto exit_ms_mem_write_unlock;
  1140. }
  1141. }
  1142. exit_ms_mem_write_unlock:
  1143. write_unlock_irqrestore(&ha->hw_lock, flags);
  1144. exit_ms_mem_write:
  1145. return ret_val;
  1146. }
  1147. static int
  1148. qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
  1149. {
  1150. int i, rval = 0;
  1151. long size = 0;
  1152. long flashaddr, memaddr;
  1153. u64 data;
  1154. u32 high, low;
  1155. flashaddr = memaddr = ha->hw.flt_region_bootload;
  1156. size = (image_start - flashaddr) / 8;
  1157. DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
  1158. ha->host_no, __func__, flashaddr, image_start));
  1159. for (i = 0; i < size; i++) {
  1160. if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
  1161. (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
  1162. (int *)&high))) {
  1163. rval = -1;
  1164. goto exit_load_from_flash;
  1165. }
  1166. data = ((u64)high << 32) | low ;
  1167. rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
  1168. if (rval)
  1169. goto exit_load_from_flash;
  1170. flashaddr += 8;
  1171. memaddr += 8;
  1172. if (i % 0x1000 == 0)
  1173. msleep(1);
  1174. }
  1175. udelay(100);
  1176. read_lock(&ha->hw_lock);
  1177. qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
  1178. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
  1179. read_unlock(&ha->hw_lock);
  1180. exit_load_from_flash:
  1181. return rval;
  1182. }
  1183. static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
  1184. {
  1185. u32 rst;
  1186. qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
  1187. if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
  1188. printk(KERN_WARNING "%s: Error during CRB Initialization\n",
  1189. __func__);
  1190. return QLA_ERROR;
  1191. }
  1192. udelay(500);
  1193. /* at this point, QM is in reset. This could be a problem if there are
  1194. * incoming d* transition queue messages. QM/PCIE could wedge.
  1195. * To get around this, QM is brought out of reset.
  1196. */
  1197. rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
  1198. /* unreset qm */
  1199. rst &= ~(1 << 28);
  1200. qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
  1201. if (qla4_82xx_load_from_flash(ha, image_start)) {
  1202. printk("%s: Error trying to load fw from flash!\n", __func__);
  1203. return QLA_ERROR;
  1204. }
  1205. return QLA_SUCCESS;
  1206. }
  1207. int
  1208. qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
  1209. u64 off, void *data, int size)
  1210. {
  1211. int i, j = 0, k, start, end, loop, sz[2], off0[2];
  1212. int shift_amount;
  1213. uint32_t temp;
  1214. uint64_t off8, val, mem_crb, word[2] = {0, 0};
  1215. /*
  1216. * If not MN, go check for MS or invalid.
  1217. */
  1218. if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
  1219. mem_crb = QLA82XX_CRB_QDR_NET;
  1220. else {
  1221. mem_crb = QLA82XX_CRB_DDR_NET;
  1222. if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
  1223. return qla4_82xx_pci_mem_read_direct(ha,
  1224. off, data, size);
  1225. }
  1226. off8 = off & 0xfffffff0;
  1227. off0[0] = off & 0xf;
  1228. sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
  1229. shift_amount = 4;
  1230. loop = ((off0[0] + size - 1) >> shift_amount) + 1;
  1231. off0[1] = 0;
  1232. sz[1] = size - sz[0];
  1233. for (i = 0; i < loop; i++) {
  1234. temp = off8 + (i << shift_amount);
  1235. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
  1236. temp = 0;
  1237. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
  1238. temp = MIU_TA_CTL_ENABLE;
  1239. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
  1240. temp = MIU_TA_CTL_START_ENABLE;
  1241. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
  1242. for (j = 0; j < MAX_CTL_CHECK; j++) {
  1243. temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
  1244. if ((temp & MIU_TA_CTL_BUSY) == 0)
  1245. break;
  1246. }
  1247. if (j >= MAX_CTL_CHECK) {
  1248. printk_ratelimited(KERN_ERR
  1249. "%s: failed to read through agent\n",
  1250. __func__);
  1251. break;
  1252. }
  1253. start = off0[i] >> 2;
  1254. end = (off0[i] + sz[i] - 1) >> 2;
  1255. for (k = start; k <= end; k++) {
  1256. temp = qla4_82xx_rd_32(ha,
  1257. mem_crb + MIU_TEST_AGT_RDDATA(k));
  1258. word[i] |= ((uint64_t)temp << (32 * (k & 1)));
  1259. }
  1260. }
  1261. if (j >= MAX_CTL_CHECK)
  1262. return -1;
  1263. if ((off0[0] & 7) == 0) {
  1264. val = word[0];
  1265. } else {
  1266. val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
  1267. ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
  1268. }
  1269. switch (size) {
  1270. case 1:
  1271. *(uint8_t *)data = val;
  1272. break;
  1273. case 2:
  1274. *(uint16_t *)data = val;
  1275. break;
  1276. case 4:
  1277. *(uint32_t *)data = val;
  1278. break;
  1279. case 8:
  1280. *(uint64_t *)data = val;
  1281. break;
  1282. }
  1283. return 0;
  1284. }
  1285. int
  1286. qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
  1287. u64 off, void *data, int size)
  1288. {
  1289. int i, j, ret = 0, loop, sz[2], off0;
  1290. int scale, shift_amount, startword;
  1291. uint32_t temp;
  1292. uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
  1293. /*
  1294. * If not MN, go check for MS or invalid.
  1295. */
  1296. if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
  1297. mem_crb = QLA82XX_CRB_QDR_NET;
  1298. else {
  1299. mem_crb = QLA82XX_CRB_DDR_NET;
  1300. if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
  1301. return qla4_82xx_pci_mem_write_direct(ha,
  1302. off, data, size);
  1303. }
  1304. off0 = off & 0x7;
  1305. sz[0] = (size < (8 - off0)) ? size : (8 - off0);
  1306. sz[1] = size - sz[0];
  1307. off8 = off & 0xfffffff0;
  1308. loop = (((off & 0xf) + size - 1) >> 4) + 1;
  1309. shift_amount = 4;
  1310. scale = 2;
  1311. startword = (off & 0xf)/8;
  1312. for (i = 0; i < loop; i++) {
  1313. if (qla4_82xx_pci_mem_read_2M(ha, off8 +
  1314. (i << shift_amount), &word[i * scale], 8))
  1315. return -1;
  1316. }
  1317. switch (size) {
  1318. case 1:
  1319. tmpw = *((uint8_t *)data);
  1320. break;
  1321. case 2:
  1322. tmpw = *((uint16_t *)data);
  1323. break;
  1324. case 4:
  1325. tmpw = *((uint32_t *)data);
  1326. break;
  1327. case 8:
  1328. default:
  1329. tmpw = *((uint64_t *)data);
  1330. break;
  1331. }
  1332. if (sz[0] == 8)
  1333. word[startword] = tmpw;
  1334. else {
  1335. word[startword] &=
  1336. ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
  1337. word[startword] |= tmpw << (off0 * 8);
  1338. }
  1339. if (sz[1] != 0) {
  1340. word[startword+1] &= ~(~0ULL << (sz[1] * 8));
  1341. word[startword+1] |= tmpw >> (sz[0] * 8);
  1342. }
  1343. for (i = 0; i < loop; i++) {
  1344. temp = off8 + (i << shift_amount);
  1345. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
  1346. temp = 0;
  1347. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
  1348. temp = word[i * scale] & 0xffffffff;
  1349. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
  1350. temp = (word[i * scale] >> 32) & 0xffffffff;
  1351. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
  1352. temp = word[i*scale + 1] & 0xffffffff;
  1353. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
  1354. temp);
  1355. temp = (word[i*scale + 1] >> 32) & 0xffffffff;
  1356. qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
  1357. temp);
  1358. temp = MIU_TA_CTL_WRITE_ENABLE;
  1359. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
  1360. temp = MIU_TA_CTL_WRITE_START;
  1361. qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
  1362. for (j = 0; j < MAX_CTL_CHECK; j++) {
  1363. temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
  1364. if ((temp & MIU_TA_CTL_BUSY) == 0)
  1365. break;
  1366. }
  1367. if (j >= MAX_CTL_CHECK) {
  1368. if (printk_ratelimit())
  1369. ql4_printk(KERN_ERR, ha,
  1370. "%s: failed to read through agent\n",
  1371. __func__);
  1372. ret = -1;
  1373. break;
  1374. }
  1375. }
  1376. return ret;
  1377. }
  1378. static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
  1379. {
  1380. u32 val = 0;
  1381. int retries = 60;
  1382. if (!pegtune_val) {
  1383. do {
  1384. val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
  1385. if ((val == PHAN_INITIALIZE_COMPLETE) ||
  1386. (val == PHAN_INITIALIZE_ACK))
  1387. return 0;
  1388. set_current_state(TASK_UNINTERRUPTIBLE);
  1389. schedule_timeout(500);
  1390. } while (--retries);
  1391. if (!retries) {
  1392. pegtune_val = qla4_82xx_rd_32(ha,
  1393. QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
  1394. printk(KERN_WARNING "%s: init failed, "
  1395. "pegtune_val = %x\n", __func__, pegtune_val);
  1396. return -1;
  1397. }
  1398. }
  1399. return 0;
  1400. }
  1401. static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
  1402. {
  1403. uint32_t state = 0;
  1404. int loops = 0;
  1405. /* Window 1 call */
  1406. read_lock(&ha->hw_lock);
  1407. state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
  1408. read_unlock(&ha->hw_lock);
  1409. while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
  1410. udelay(100);
  1411. /* Window 1 call */
  1412. read_lock(&ha->hw_lock);
  1413. state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
  1414. read_unlock(&ha->hw_lock);
  1415. loops++;
  1416. }
  1417. if (loops >= 30000) {
  1418. DEBUG2(ql4_printk(KERN_INFO, ha,
  1419. "Receive Peg initialization not complete: 0x%x.\n", state));
  1420. return QLA_ERROR;
  1421. }
  1422. return QLA_SUCCESS;
  1423. }
  1424. void
  1425. qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
  1426. {
  1427. uint32_t drv_active;
  1428. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1429. /*
  1430. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1431. * shift 1 by func_num to set a bit for the function.
  1432. * For ISP8022, drv_active has 4 bits per function
  1433. */
  1434. if (is_qla8032(ha) || is_qla8042(ha))
  1435. drv_active |= (1 << ha->func_num);
  1436. else
  1437. drv_active |= (1 << (ha->func_num * 4));
  1438. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
  1439. __func__, ha->host_no, drv_active);
  1440. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
  1441. }
  1442. void
  1443. qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
  1444. {
  1445. uint32_t drv_active;
  1446. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1447. /*
  1448. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1449. * shift 1 by func_num to set a bit for the function.
  1450. * For ISP8022, drv_active has 4 bits per function
  1451. */
  1452. if (is_qla8032(ha) || is_qla8042(ha))
  1453. drv_active &= ~(1 << (ha->func_num));
  1454. else
  1455. drv_active &= ~(1 << (ha->func_num * 4));
  1456. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
  1457. __func__, ha->host_no, drv_active);
  1458. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
  1459. }
  1460. inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
  1461. {
  1462. uint32_t drv_state, drv_active;
  1463. int rval;
  1464. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1465. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1466. /*
  1467. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1468. * shift 1 by func_num to set a bit for the function.
  1469. * For ISP8022, drv_active has 4 bits per function
  1470. */
  1471. if (is_qla8032(ha) || is_qla8042(ha))
  1472. rval = drv_state & (1 << ha->func_num);
  1473. else
  1474. rval = drv_state & (1 << (ha->func_num * 4));
  1475. if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
  1476. rval = 1;
  1477. return rval;
  1478. }
  1479. void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
  1480. {
  1481. uint32_t drv_state;
  1482. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1483. /*
  1484. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1485. * shift 1 by func_num to set a bit for the function.
  1486. * For ISP8022, drv_active has 4 bits per function
  1487. */
  1488. if (is_qla8032(ha) || is_qla8042(ha))
  1489. drv_state |= (1 << ha->func_num);
  1490. else
  1491. drv_state |= (1 << (ha->func_num * 4));
  1492. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
  1493. __func__, ha->host_no, drv_state);
  1494. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
  1495. }
  1496. void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
  1497. {
  1498. uint32_t drv_state;
  1499. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1500. /*
  1501. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1502. * shift 1 by func_num to set a bit for the function.
  1503. * For ISP8022, drv_active has 4 bits per function
  1504. */
  1505. if (is_qla8032(ha) || is_qla8042(ha))
  1506. drv_state &= ~(1 << ha->func_num);
  1507. else
  1508. drv_state &= ~(1 << (ha->func_num * 4));
  1509. ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
  1510. __func__, ha->host_no, drv_state);
  1511. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
  1512. }
  1513. static inline void
  1514. qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
  1515. {
  1516. uint32_t qsnt_state;
  1517. qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  1518. /*
  1519. * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
  1520. * shift 1 by func_num to set a bit for the function.
  1521. * For ISP8022, drv_active has 4 bits per function.
  1522. */
  1523. if (is_qla8032(ha) || is_qla8042(ha))
  1524. qsnt_state |= (1 << ha->func_num);
  1525. else
  1526. qsnt_state |= (2 << (ha->func_num * 4));
  1527. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
  1528. }
  1529. static int
  1530. qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
  1531. {
  1532. uint16_t lnk;
  1533. /* scrub dma mask expansion register */
  1534. qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
  1535. /* Overwrite stale initialization register values */
  1536. qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
  1537. qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
  1538. qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
  1539. qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
  1540. if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
  1541. printk("%s: Error trying to start fw!\n", __func__);
  1542. return QLA_ERROR;
  1543. }
  1544. /* Handshake with the card before we register the devices. */
  1545. if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
  1546. printk("%s: Error during card handshake!\n", __func__);
  1547. return QLA_ERROR;
  1548. }
  1549. /* Negotiated Link width */
  1550. pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
  1551. ha->link_width = (lnk >> 4) & 0x3f;
  1552. /* Synchronize with Receive peg */
  1553. return qla4_82xx_rcvpeg_ready(ha);
  1554. }
  1555. int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
  1556. {
  1557. int rval = QLA_ERROR;
  1558. /*
  1559. * FW Load priority:
  1560. * 1) Operational firmware residing in flash.
  1561. * 2) Fail
  1562. */
  1563. ql4_printk(KERN_INFO, ha,
  1564. "FW: Retrieving flash offsets from FLT/FDT ...\n");
  1565. rval = qla4_8xxx_get_flash_info(ha);
  1566. if (rval != QLA_SUCCESS)
  1567. return rval;
  1568. ql4_printk(KERN_INFO, ha,
  1569. "FW: Attempting to load firmware from flash...\n");
  1570. rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
  1571. if (rval != QLA_SUCCESS) {
  1572. ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
  1573. " FAILED...\n");
  1574. return rval;
  1575. }
  1576. return rval;
  1577. }
  1578. void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
  1579. {
  1580. if (qla4_82xx_rom_lock(ha)) {
  1581. /* Someone else is holding the lock. */
  1582. dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
  1583. }
  1584. /*
  1585. * Either we got the lock, or someone
  1586. * else died while holding it.
  1587. * In either case, unlock.
  1588. */
  1589. qla4_82xx_rom_unlock(ha);
  1590. }
  1591. static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
  1592. uint32_t addr1, uint32_t mask)
  1593. {
  1594. unsigned long timeout;
  1595. uint32_t rval = QLA_SUCCESS;
  1596. uint32_t temp;
  1597. timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
  1598. do {
  1599. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  1600. if ((temp & mask) != 0)
  1601. break;
  1602. if (time_after_eq(jiffies, timeout)) {
  1603. ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
  1604. return QLA_ERROR;
  1605. }
  1606. } while (1);
  1607. return rval;
  1608. }
  1609. static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
  1610. uint32_t addr3, uint32_t mask, uint32_t addr,
  1611. uint32_t *data_ptr)
  1612. {
  1613. int rval = QLA_SUCCESS;
  1614. uint32_t temp;
  1615. uint32_t data;
  1616. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1617. if (rval)
  1618. goto exit_ipmdio_rd_reg;
  1619. temp = (0x40000000 | addr);
  1620. ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
  1621. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1622. if (rval)
  1623. goto exit_ipmdio_rd_reg;
  1624. ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
  1625. *data_ptr = data;
  1626. exit_ipmdio_rd_reg:
  1627. return rval;
  1628. }
  1629. static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
  1630. uint32_t addr1,
  1631. uint32_t addr2,
  1632. uint32_t addr3,
  1633. uint32_t mask)
  1634. {
  1635. unsigned long timeout;
  1636. uint32_t temp;
  1637. uint32_t rval = QLA_SUCCESS;
  1638. timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
  1639. do {
  1640. ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
  1641. if ((temp & 0x1) != 1)
  1642. break;
  1643. if (time_after_eq(jiffies, timeout)) {
  1644. ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
  1645. return QLA_ERROR;
  1646. }
  1647. } while (1);
  1648. return rval;
  1649. }
  1650. static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
  1651. uint32_t addr1, uint32_t addr3,
  1652. uint32_t mask, uint32_t addr,
  1653. uint32_t value)
  1654. {
  1655. int rval = QLA_SUCCESS;
  1656. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1657. if (rval)
  1658. goto exit_ipmdio_wr_reg;
  1659. ha->isp_ops->wr_reg_indirect(ha, addr3, value);
  1660. ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
  1661. rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
  1662. if (rval)
  1663. goto exit_ipmdio_wr_reg;
  1664. exit_ipmdio_wr_reg:
  1665. return rval;
  1666. }
  1667. static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
  1668. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  1669. uint32_t **d_ptr)
  1670. {
  1671. uint32_t r_addr, r_stride, loop_cnt, i, r_value;
  1672. struct qla8xxx_minidump_entry_crb *crb_hdr;
  1673. uint32_t *data_ptr = *d_ptr;
  1674. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1675. crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
  1676. r_addr = crb_hdr->addr;
  1677. r_stride = crb_hdr->crb_strd.addr_stride;
  1678. loop_cnt = crb_hdr->op_count;
  1679. for (i = 0; i < loop_cnt; i++) {
  1680. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  1681. *data_ptr++ = cpu_to_le32(r_addr);
  1682. *data_ptr++ = cpu_to_le32(r_value);
  1683. r_addr += r_stride;
  1684. }
  1685. *d_ptr = data_ptr;
  1686. }
  1687. static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
  1688. {
  1689. int rval = QLA_SUCCESS;
  1690. uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
  1691. uint64_t dma_base_addr = 0;
  1692. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
  1693. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  1694. ha->fw_dump_tmplt_hdr;
  1695. dma_eng_num =
  1696. tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
  1697. dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
  1698. (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
  1699. /* Read the pex-dma's command-status-and-control register. */
  1700. rval = ha->isp_ops->rd_reg_indirect(ha,
  1701. (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
  1702. &cmd_sts_and_cntrl);
  1703. if (rval)
  1704. return QLA_ERROR;
  1705. /* Check if requested pex-dma engine is available. */
  1706. if (cmd_sts_and_cntrl & BIT_31)
  1707. return QLA_SUCCESS;
  1708. else
  1709. return QLA_ERROR;
  1710. }
  1711. static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
  1712. struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
  1713. {
  1714. int rval = QLA_SUCCESS, wait = 0;
  1715. uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
  1716. uint64_t dma_base_addr = 0;
  1717. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
  1718. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  1719. ha->fw_dump_tmplt_hdr;
  1720. dma_eng_num =
  1721. tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
  1722. dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
  1723. (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
  1724. rval = ha->isp_ops->wr_reg_indirect(ha,
  1725. dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
  1726. m_hdr->desc_card_addr);
  1727. if (rval)
  1728. goto error_exit;
  1729. rval = ha->isp_ops->wr_reg_indirect(ha,
  1730. dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
  1731. if (rval)
  1732. goto error_exit;
  1733. rval = ha->isp_ops->wr_reg_indirect(ha,
  1734. dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
  1735. m_hdr->start_dma_cmd);
  1736. if (rval)
  1737. goto error_exit;
  1738. /* Wait for dma operation to complete. */
  1739. for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
  1740. rval = ha->isp_ops->rd_reg_indirect(ha,
  1741. (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
  1742. &cmd_sts_and_cntrl);
  1743. if (rval)
  1744. goto error_exit;
  1745. if ((cmd_sts_and_cntrl & BIT_1) == 0)
  1746. break;
  1747. else
  1748. udelay(10);
  1749. }
  1750. /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
  1751. if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
  1752. rval = QLA_ERROR;
  1753. goto error_exit;
  1754. }
  1755. error_exit:
  1756. return rval;
  1757. }
  1758. static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
  1759. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  1760. uint32_t **d_ptr)
  1761. {
  1762. int rval = QLA_SUCCESS;
  1763. struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
  1764. uint32_t size, read_size;
  1765. uint8_t *data_ptr = (uint8_t *)*d_ptr;
  1766. void *rdmem_buffer = NULL;
  1767. dma_addr_t rdmem_dma;
  1768. struct qla4_83xx_pex_dma_descriptor dma_desc;
  1769. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1770. rval = qla4_83xx_check_dma_engine_state(ha);
  1771. if (rval != QLA_SUCCESS) {
  1772. DEBUG2(ql4_printk(KERN_INFO, ha,
  1773. "%s: DMA engine not available. Fallback to rdmem-read.\n",
  1774. __func__));
  1775. return QLA_ERROR;
  1776. }
  1777. m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
  1778. rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
  1779. QLA83XX_PEX_DMA_READ_SIZE,
  1780. &rdmem_dma, GFP_KERNEL);
  1781. if (!rdmem_buffer) {
  1782. DEBUG2(ql4_printk(KERN_INFO, ha,
  1783. "%s: Unable to allocate rdmem dma buffer\n",
  1784. __func__));
  1785. return QLA_ERROR;
  1786. }
  1787. /* Prepare pex-dma descriptor to be written to MS memory. */
  1788. /* dma-desc-cmd layout:
  1789. * 0-3: dma-desc-cmd 0-3
  1790. * 4-7: pcid function number
  1791. * 8-15: dma-desc-cmd 8-15
  1792. */
  1793. dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
  1794. dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
  1795. dma_desc.dma_bus_addr = rdmem_dma;
  1796. size = 0;
  1797. read_size = 0;
  1798. /*
  1799. * Perform rdmem operation using pex-dma.
  1800. * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
  1801. */
  1802. while (read_size < m_hdr->read_data_size) {
  1803. if (m_hdr->read_data_size - read_size >=
  1804. QLA83XX_PEX_DMA_READ_SIZE)
  1805. size = QLA83XX_PEX_DMA_READ_SIZE;
  1806. else {
  1807. size = (m_hdr->read_data_size - read_size);
  1808. if (rdmem_buffer)
  1809. dma_free_coherent(&ha->pdev->dev,
  1810. QLA83XX_PEX_DMA_READ_SIZE,
  1811. rdmem_buffer, rdmem_dma);
  1812. rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
  1813. &rdmem_dma,
  1814. GFP_KERNEL);
  1815. if (!rdmem_buffer) {
  1816. DEBUG2(ql4_printk(KERN_INFO, ha,
  1817. "%s: Unable to allocate rdmem dma buffer\n",
  1818. __func__));
  1819. return QLA_ERROR;
  1820. }
  1821. dma_desc.dma_bus_addr = rdmem_dma;
  1822. }
  1823. dma_desc.src_addr = m_hdr->read_addr + read_size;
  1824. dma_desc.cmd.read_data_size = size;
  1825. /* Prepare: Write pex-dma descriptor to MS memory. */
  1826. rval = qla4_8xxx_ms_mem_write_128b(ha,
  1827. (uint64_t)m_hdr->desc_card_addr,
  1828. (uint32_t *)&dma_desc,
  1829. (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
  1830. if (rval != QLA_SUCCESS) {
  1831. ql4_printk(KERN_INFO, ha,
  1832. "%s: Error writing rdmem-dma-init to MS !!!\n",
  1833. __func__);
  1834. goto error_exit;
  1835. }
  1836. DEBUG2(ql4_printk(KERN_INFO, ha,
  1837. "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
  1838. __func__, size));
  1839. /* Execute: Start pex-dma operation. */
  1840. rval = qla4_83xx_start_pex_dma(ha, m_hdr);
  1841. if (rval != QLA_SUCCESS) {
  1842. DEBUG2(ql4_printk(KERN_INFO, ha,
  1843. "scsi(%ld): start-pex-dma failed rval=0x%x\n",
  1844. ha->host_no, rval));
  1845. goto error_exit;
  1846. }
  1847. memcpy(data_ptr, rdmem_buffer, size);
  1848. data_ptr += size;
  1849. read_size += size;
  1850. }
  1851. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
  1852. *d_ptr = (uint32_t *)data_ptr;
  1853. error_exit:
  1854. if (rdmem_buffer)
  1855. dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
  1856. rdmem_dma);
  1857. return rval;
  1858. }
  1859. static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
  1860. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  1861. uint32_t **d_ptr)
  1862. {
  1863. uint32_t addr, r_addr, c_addr, t_r_addr;
  1864. uint32_t i, k, loop_count, t_value, r_cnt, r_value;
  1865. unsigned long p_wait, w_time, p_mask;
  1866. uint32_t c_value_w, c_value_r;
  1867. struct qla8xxx_minidump_entry_cache *cache_hdr;
  1868. int rval = QLA_ERROR;
  1869. uint32_t *data_ptr = *d_ptr;
  1870. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1871. cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
  1872. loop_count = cache_hdr->op_count;
  1873. r_addr = cache_hdr->read_addr;
  1874. c_addr = cache_hdr->control_addr;
  1875. c_value_w = cache_hdr->cache_ctrl.write_value;
  1876. t_r_addr = cache_hdr->tag_reg_addr;
  1877. t_value = cache_hdr->addr_ctrl.init_tag_value;
  1878. r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
  1879. p_wait = cache_hdr->cache_ctrl.poll_wait;
  1880. p_mask = cache_hdr->cache_ctrl.poll_mask;
  1881. for (i = 0; i < loop_count; i++) {
  1882. ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
  1883. if (c_value_w)
  1884. ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
  1885. if (p_mask) {
  1886. w_time = jiffies + p_wait;
  1887. do {
  1888. ha->isp_ops->rd_reg_indirect(ha, c_addr,
  1889. &c_value_r);
  1890. if ((c_value_r & p_mask) == 0) {
  1891. break;
  1892. } else if (time_after_eq(jiffies, w_time)) {
  1893. /* capturing dump failed */
  1894. return rval;
  1895. }
  1896. } while (1);
  1897. }
  1898. addr = r_addr;
  1899. for (k = 0; k < r_cnt; k++) {
  1900. ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
  1901. *data_ptr++ = cpu_to_le32(r_value);
  1902. addr += cache_hdr->read_ctrl.read_addr_stride;
  1903. }
  1904. t_value += cache_hdr->addr_ctrl.tag_value_stride;
  1905. }
  1906. *d_ptr = data_ptr;
  1907. return QLA_SUCCESS;
  1908. }
  1909. static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
  1910. struct qla8xxx_minidump_entry_hdr *entry_hdr)
  1911. {
  1912. struct qla8xxx_minidump_entry_crb *crb_entry;
  1913. uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
  1914. uint32_t crb_addr;
  1915. unsigned long wtime;
  1916. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
  1917. int i;
  1918. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  1919. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  1920. ha->fw_dump_tmplt_hdr;
  1921. crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
  1922. crb_addr = crb_entry->addr;
  1923. for (i = 0; i < crb_entry->op_count; i++) {
  1924. opcode = crb_entry->crb_ctrl.opcode;
  1925. if (opcode & QLA8XXX_DBG_OPCODE_WR) {
  1926. ha->isp_ops->wr_reg_indirect(ha, crb_addr,
  1927. crb_entry->value_1);
  1928. opcode &= ~QLA8XXX_DBG_OPCODE_WR;
  1929. }
  1930. if (opcode & QLA8XXX_DBG_OPCODE_RW) {
  1931. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1932. ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
  1933. opcode &= ~QLA8XXX_DBG_OPCODE_RW;
  1934. }
  1935. if (opcode & QLA8XXX_DBG_OPCODE_AND) {
  1936. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1937. read_value &= crb_entry->value_2;
  1938. opcode &= ~QLA8XXX_DBG_OPCODE_AND;
  1939. if (opcode & QLA8XXX_DBG_OPCODE_OR) {
  1940. read_value |= crb_entry->value_3;
  1941. opcode &= ~QLA8XXX_DBG_OPCODE_OR;
  1942. }
  1943. ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
  1944. }
  1945. if (opcode & QLA8XXX_DBG_OPCODE_OR) {
  1946. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1947. read_value |= crb_entry->value_3;
  1948. ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
  1949. opcode &= ~QLA8XXX_DBG_OPCODE_OR;
  1950. }
  1951. if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
  1952. poll_time = crb_entry->crb_strd.poll_timeout;
  1953. wtime = jiffies + poll_time;
  1954. ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
  1955. do {
  1956. if ((read_value & crb_entry->value_2) ==
  1957. crb_entry->value_1) {
  1958. break;
  1959. } else if (time_after_eq(jiffies, wtime)) {
  1960. /* capturing dump failed */
  1961. rval = QLA_ERROR;
  1962. break;
  1963. } else {
  1964. ha->isp_ops->rd_reg_indirect(ha,
  1965. crb_addr, &read_value);
  1966. }
  1967. } while (1);
  1968. opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
  1969. }
  1970. if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
  1971. if (crb_entry->crb_strd.state_index_a) {
  1972. index = crb_entry->crb_strd.state_index_a;
  1973. addr = tmplt_hdr->saved_state_array[index];
  1974. } else {
  1975. addr = crb_addr;
  1976. }
  1977. ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
  1978. index = crb_entry->crb_ctrl.state_index_v;
  1979. tmplt_hdr->saved_state_array[index] = read_value;
  1980. opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
  1981. }
  1982. if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
  1983. if (crb_entry->crb_strd.state_index_a) {
  1984. index = crb_entry->crb_strd.state_index_a;
  1985. addr = tmplt_hdr->saved_state_array[index];
  1986. } else {
  1987. addr = crb_addr;
  1988. }
  1989. if (crb_entry->crb_ctrl.state_index_v) {
  1990. index = crb_entry->crb_ctrl.state_index_v;
  1991. read_value =
  1992. tmplt_hdr->saved_state_array[index];
  1993. } else {
  1994. read_value = crb_entry->value_1;
  1995. }
  1996. ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
  1997. opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
  1998. }
  1999. if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
  2000. index = crb_entry->crb_ctrl.state_index_v;
  2001. read_value = tmplt_hdr->saved_state_array[index];
  2002. read_value <<= crb_entry->crb_ctrl.shl;
  2003. read_value >>= crb_entry->crb_ctrl.shr;
  2004. if (crb_entry->value_2)
  2005. read_value &= crb_entry->value_2;
  2006. read_value |= crb_entry->value_3;
  2007. read_value += crb_entry->value_1;
  2008. tmplt_hdr->saved_state_array[index] = read_value;
  2009. opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
  2010. }
  2011. crb_addr += crb_entry->crb_strd.addr_stride;
  2012. }
  2013. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
  2014. return rval;
  2015. }
  2016. static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
  2017. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2018. uint32_t **d_ptr)
  2019. {
  2020. uint32_t r_addr, r_stride, loop_cnt, i, r_value;
  2021. struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
  2022. uint32_t *data_ptr = *d_ptr;
  2023. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2024. ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
  2025. r_addr = ocm_hdr->read_addr;
  2026. r_stride = ocm_hdr->read_addr_stride;
  2027. loop_cnt = ocm_hdr->op_count;
  2028. DEBUG2(ql4_printk(KERN_INFO, ha,
  2029. "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
  2030. __func__, r_addr, r_stride, loop_cnt));
  2031. for (i = 0; i < loop_cnt; i++) {
  2032. r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
  2033. *data_ptr++ = cpu_to_le32(r_value);
  2034. r_addr += r_stride;
  2035. }
  2036. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
  2037. __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
  2038. *d_ptr = data_ptr;
  2039. }
  2040. static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
  2041. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2042. uint32_t **d_ptr)
  2043. {
  2044. uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
  2045. struct qla8xxx_minidump_entry_mux *mux_hdr;
  2046. uint32_t *data_ptr = *d_ptr;
  2047. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2048. mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
  2049. r_addr = mux_hdr->read_addr;
  2050. s_addr = mux_hdr->select_addr;
  2051. s_stride = mux_hdr->select_value_stride;
  2052. s_value = mux_hdr->select_value;
  2053. loop_cnt = mux_hdr->op_count;
  2054. for (i = 0; i < loop_cnt; i++) {
  2055. ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
  2056. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  2057. *data_ptr++ = cpu_to_le32(s_value);
  2058. *data_ptr++ = cpu_to_le32(r_value);
  2059. s_value += s_stride;
  2060. }
  2061. *d_ptr = data_ptr;
  2062. }
  2063. static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
  2064. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2065. uint32_t **d_ptr)
  2066. {
  2067. uint32_t addr, r_addr, c_addr, t_r_addr;
  2068. uint32_t i, k, loop_count, t_value, r_cnt, r_value;
  2069. uint32_t c_value_w;
  2070. struct qla8xxx_minidump_entry_cache *cache_hdr;
  2071. uint32_t *data_ptr = *d_ptr;
  2072. cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
  2073. loop_count = cache_hdr->op_count;
  2074. r_addr = cache_hdr->read_addr;
  2075. c_addr = cache_hdr->control_addr;
  2076. c_value_w = cache_hdr->cache_ctrl.write_value;
  2077. t_r_addr = cache_hdr->tag_reg_addr;
  2078. t_value = cache_hdr->addr_ctrl.init_tag_value;
  2079. r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
  2080. for (i = 0; i < loop_count; i++) {
  2081. ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
  2082. ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
  2083. addr = r_addr;
  2084. for (k = 0; k < r_cnt; k++) {
  2085. ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
  2086. *data_ptr++ = cpu_to_le32(r_value);
  2087. addr += cache_hdr->read_ctrl.read_addr_stride;
  2088. }
  2089. t_value += cache_hdr->addr_ctrl.tag_value_stride;
  2090. }
  2091. *d_ptr = data_ptr;
  2092. }
  2093. static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
  2094. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2095. uint32_t **d_ptr)
  2096. {
  2097. uint32_t s_addr, r_addr;
  2098. uint32_t r_stride, r_value, r_cnt, qid = 0;
  2099. uint32_t i, k, loop_cnt;
  2100. struct qla8xxx_minidump_entry_queue *q_hdr;
  2101. uint32_t *data_ptr = *d_ptr;
  2102. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2103. q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
  2104. s_addr = q_hdr->select_addr;
  2105. r_cnt = q_hdr->rd_strd.read_addr_cnt;
  2106. r_stride = q_hdr->rd_strd.read_addr_stride;
  2107. loop_cnt = q_hdr->op_count;
  2108. for (i = 0; i < loop_cnt; i++) {
  2109. ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
  2110. r_addr = q_hdr->read_addr;
  2111. for (k = 0; k < r_cnt; k++) {
  2112. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  2113. *data_ptr++ = cpu_to_le32(r_value);
  2114. r_addr += r_stride;
  2115. }
  2116. qid += q_hdr->q_strd.queue_id_stride;
  2117. }
  2118. *d_ptr = data_ptr;
  2119. }
  2120. #define MD_DIRECT_ROM_WINDOW 0x42110030
  2121. #define MD_DIRECT_ROM_READ_BASE 0x42150000
  2122. static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
  2123. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2124. uint32_t **d_ptr)
  2125. {
  2126. uint32_t r_addr, r_value;
  2127. uint32_t i, loop_cnt;
  2128. struct qla8xxx_minidump_entry_rdrom *rom_hdr;
  2129. uint32_t *data_ptr = *d_ptr;
  2130. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2131. rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
  2132. r_addr = rom_hdr->read_addr;
  2133. loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
  2134. DEBUG2(ql4_printk(KERN_INFO, ha,
  2135. "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
  2136. __func__, r_addr, loop_cnt));
  2137. for (i = 0; i < loop_cnt; i++) {
  2138. ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
  2139. (r_addr & 0xFFFF0000));
  2140. ha->isp_ops->rd_reg_indirect(ha,
  2141. MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
  2142. &r_value);
  2143. *data_ptr++ = cpu_to_le32(r_value);
  2144. r_addr += sizeof(uint32_t);
  2145. }
  2146. *d_ptr = data_ptr;
  2147. }
  2148. #define MD_MIU_TEST_AGT_CTRL 0x41000090
  2149. #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
  2150. #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
  2151. static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
  2152. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2153. uint32_t **d_ptr)
  2154. {
  2155. uint32_t r_addr, r_value, r_data;
  2156. uint32_t i, j, loop_cnt;
  2157. struct qla8xxx_minidump_entry_rdmem *m_hdr;
  2158. unsigned long flags;
  2159. uint32_t *data_ptr = *d_ptr;
  2160. DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
  2161. m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
  2162. r_addr = m_hdr->read_addr;
  2163. loop_cnt = m_hdr->read_data_size/16;
  2164. DEBUG2(ql4_printk(KERN_INFO, ha,
  2165. "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
  2166. __func__, r_addr, m_hdr->read_data_size));
  2167. if (r_addr & 0xf) {
  2168. DEBUG2(ql4_printk(KERN_INFO, ha,
  2169. "[%s]: Read addr 0x%x not 16 bytes aligned\n",
  2170. __func__, r_addr));
  2171. return QLA_ERROR;
  2172. }
  2173. if (m_hdr->read_data_size % 16) {
  2174. DEBUG2(ql4_printk(KERN_INFO, ha,
  2175. "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
  2176. __func__, m_hdr->read_data_size));
  2177. return QLA_ERROR;
  2178. }
  2179. DEBUG2(ql4_printk(KERN_INFO, ha,
  2180. "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
  2181. __func__, r_addr, m_hdr->read_data_size, loop_cnt));
  2182. write_lock_irqsave(&ha->hw_lock, flags);
  2183. for (i = 0; i < loop_cnt; i++) {
  2184. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
  2185. r_addr);
  2186. r_value = 0;
  2187. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
  2188. r_value);
  2189. r_value = MIU_TA_CTL_ENABLE;
  2190. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
  2191. r_value = MIU_TA_CTL_START_ENABLE;
  2192. ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
  2193. for (j = 0; j < MAX_CTL_CHECK; j++) {
  2194. ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
  2195. &r_value);
  2196. if ((r_value & MIU_TA_CTL_BUSY) == 0)
  2197. break;
  2198. }
  2199. if (j >= MAX_CTL_CHECK) {
  2200. printk_ratelimited(KERN_ERR
  2201. "%s: failed to read through agent\n",
  2202. __func__);
  2203. write_unlock_irqrestore(&ha->hw_lock, flags);
  2204. return QLA_SUCCESS;
  2205. }
  2206. for (j = 0; j < 4; j++) {
  2207. ha->isp_ops->rd_reg_indirect(ha,
  2208. MD_MIU_TEST_AGT_RDDATA[j],
  2209. &r_data);
  2210. *data_ptr++ = cpu_to_le32(r_data);
  2211. }
  2212. r_addr += 16;
  2213. }
  2214. write_unlock_irqrestore(&ha->hw_lock, flags);
  2215. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
  2216. __func__, (loop_cnt * 16)));
  2217. *d_ptr = data_ptr;
  2218. return QLA_SUCCESS;
  2219. }
  2220. static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
  2221. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2222. uint32_t **d_ptr)
  2223. {
  2224. uint32_t *data_ptr = *d_ptr;
  2225. int rval = QLA_SUCCESS;
  2226. rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
  2227. if (rval != QLA_SUCCESS)
  2228. rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
  2229. &data_ptr);
  2230. *d_ptr = data_ptr;
  2231. return rval;
  2232. }
  2233. static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
  2234. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2235. int index)
  2236. {
  2237. entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
  2238. DEBUG2(ql4_printk(KERN_INFO, ha,
  2239. "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
  2240. ha->host_no, index, entry_hdr->entry_type,
  2241. entry_hdr->d_ctrl.entry_capture_mask));
  2242. /* If driver encounters a new entry type that it cannot process,
  2243. * it should just skip the entry and adjust the total buffer size by
  2244. * from subtracting the skipped bytes from it
  2245. */
  2246. ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
  2247. }
  2248. /* ISP83xx functions to process new minidump entries... */
  2249. static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
  2250. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2251. uint32_t **d_ptr)
  2252. {
  2253. uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
  2254. uint16_t s_stride, i;
  2255. uint32_t *data_ptr = *d_ptr;
  2256. uint32_t rval = QLA_SUCCESS;
  2257. struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
  2258. pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
  2259. s_addr = le32_to_cpu(pollrd_hdr->select_addr);
  2260. r_addr = le32_to_cpu(pollrd_hdr->read_addr);
  2261. s_value = le32_to_cpu(pollrd_hdr->select_value);
  2262. s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
  2263. poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
  2264. poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
  2265. for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
  2266. ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
  2267. poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
  2268. while (1) {
  2269. ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
  2270. if ((r_value & poll_mask) != 0) {
  2271. break;
  2272. } else {
  2273. msleep(1);
  2274. if (--poll_wait == 0) {
  2275. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
  2276. __func__);
  2277. rval = QLA_ERROR;
  2278. goto exit_process_pollrd;
  2279. }
  2280. }
  2281. }
  2282. ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
  2283. *data_ptr++ = cpu_to_le32(s_value);
  2284. *data_ptr++ = cpu_to_le32(r_value);
  2285. s_value += s_stride;
  2286. }
  2287. *d_ptr = data_ptr;
  2288. exit_process_pollrd:
  2289. return rval;
  2290. }
  2291. static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
  2292. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2293. uint32_t **d_ptr)
  2294. {
  2295. int loop_cnt;
  2296. uint32_t addr1, addr2, value, data, temp, wrval;
  2297. uint8_t stride, stride2;
  2298. uint16_t count;
  2299. uint32_t poll, mask, modify_mask;
  2300. uint32_t wait_count = 0;
  2301. uint32_t *data_ptr = *d_ptr;
  2302. struct qla8044_minidump_entry_rddfe *rddfe;
  2303. uint32_t rval = QLA_SUCCESS;
  2304. rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
  2305. addr1 = le32_to_cpu(rddfe->addr_1);
  2306. value = le32_to_cpu(rddfe->value);
  2307. stride = le32_to_cpu(rddfe->stride);
  2308. stride2 = le32_to_cpu(rddfe->stride2);
  2309. count = le32_to_cpu(rddfe->count);
  2310. poll = le32_to_cpu(rddfe->poll);
  2311. mask = le32_to_cpu(rddfe->mask);
  2312. modify_mask = le32_to_cpu(rddfe->modify_mask);
  2313. addr2 = addr1 + stride;
  2314. for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
  2315. ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
  2316. wait_count = 0;
  2317. while (wait_count < poll) {
  2318. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  2319. if ((temp & mask) != 0)
  2320. break;
  2321. wait_count++;
  2322. }
  2323. if (wait_count == poll) {
  2324. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
  2325. rval = QLA_ERROR;
  2326. goto exit_process_rddfe;
  2327. } else {
  2328. ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
  2329. temp = temp & modify_mask;
  2330. temp = (temp | ((loop_cnt << 16) | loop_cnt));
  2331. wrval = ((temp << 16) | temp);
  2332. ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
  2333. ha->isp_ops->wr_reg_indirect(ha, addr1, value);
  2334. wait_count = 0;
  2335. while (wait_count < poll) {
  2336. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  2337. if ((temp & mask) != 0)
  2338. break;
  2339. wait_count++;
  2340. }
  2341. if (wait_count == poll) {
  2342. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
  2343. __func__);
  2344. rval = QLA_ERROR;
  2345. goto exit_process_rddfe;
  2346. }
  2347. ha->isp_ops->wr_reg_indirect(ha, addr1,
  2348. ((0x40000000 | value) +
  2349. stride2));
  2350. wait_count = 0;
  2351. while (wait_count < poll) {
  2352. ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
  2353. if ((temp & mask) != 0)
  2354. break;
  2355. wait_count++;
  2356. }
  2357. if (wait_count == poll) {
  2358. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
  2359. __func__);
  2360. rval = QLA_ERROR;
  2361. goto exit_process_rddfe;
  2362. }
  2363. ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
  2364. *data_ptr++ = cpu_to_le32(wrval);
  2365. *data_ptr++ = cpu_to_le32(data);
  2366. }
  2367. }
  2368. *d_ptr = data_ptr;
  2369. exit_process_rddfe:
  2370. return rval;
  2371. }
  2372. static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
  2373. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2374. uint32_t **d_ptr)
  2375. {
  2376. int rval = QLA_SUCCESS;
  2377. uint32_t addr1, addr2, value1, value2, data, selval;
  2378. uint8_t stride1, stride2;
  2379. uint32_t addr3, addr4, addr5, addr6, addr7;
  2380. uint16_t count, loop_cnt;
  2381. uint32_t mask;
  2382. uint32_t *data_ptr = *d_ptr;
  2383. struct qla8044_minidump_entry_rdmdio *rdmdio;
  2384. rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
  2385. addr1 = le32_to_cpu(rdmdio->addr_1);
  2386. addr2 = le32_to_cpu(rdmdio->addr_2);
  2387. value1 = le32_to_cpu(rdmdio->value_1);
  2388. stride1 = le32_to_cpu(rdmdio->stride_1);
  2389. stride2 = le32_to_cpu(rdmdio->stride_2);
  2390. count = le32_to_cpu(rdmdio->count);
  2391. mask = le32_to_cpu(rdmdio->mask);
  2392. value2 = le32_to_cpu(rdmdio->value_2);
  2393. addr3 = addr1 + stride1;
  2394. for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
  2395. rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
  2396. addr3, mask);
  2397. if (rval)
  2398. goto exit_process_rdmdio;
  2399. addr4 = addr2 - stride1;
  2400. rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
  2401. value2);
  2402. if (rval)
  2403. goto exit_process_rdmdio;
  2404. addr5 = addr2 - (2 * stride1);
  2405. rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
  2406. value1);
  2407. if (rval)
  2408. goto exit_process_rdmdio;
  2409. addr6 = addr2 - (3 * stride1);
  2410. rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
  2411. addr6, 0x2);
  2412. if (rval)
  2413. goto exit_process_rdmdio;
  2414. rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
  2415. addr3, mask);
  2416. if (rval)
  2417. goto exit_process_rdmdio;
  2418. addr7 = addr2 - (4 * stride1);
  2419. rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
  2420. mask, addr7, &data);
  2421. if (rval)
  2422. goto exit_process_rdmdio;
  2423. selval = (value2 << 18) | (value1 << 2) | 2;
  2424. stride2 = le32_to_cpu(rdmdio->stride_2);
  2425. *data_ptr++ = cpu_to_le32(selval);
  2426. *data_ptr++ = cpu_to_le32(data);
  2427. value1 = value1 + stride2;
  2428. *d_ptr = data_ptr;
  2429. }
  2430. exit_process_rdmdio:
  2431. return rval;
  2432. }
  2433. static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
  2434. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2435. uint32_t **d_ptr)
  2436. {
  2437. uint32_t addr1, addr2, value1, value2, poll, r_value;
  2438. struct qla8044_minidump_entry_pollwr *pollwr_hdr;
  2439. uint32_t wait_count = 0;
  2440. uint32_t rval = QLA_SUCCESS;
  2441. pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
  2442. addr1 = le32_to_cpu(pollwr_hdr->addr_1);
  2443. addr2 = le32_to_cpu(pollwr_hdr->addr_2);
  2444. value1 = le32_to_cpu(pollwr_hdr->value_1);
  2445. value2 = le32_to_cpu(pollwr_hdr->value_2);
  2446. poll = le32_to_cpu(pollwr_hdr->poll);
  2447. while (wait_count < poll) {
  2448. ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
  2449. if ((r_value & poll) != 0)
  2450. break;
  2451. wait_count++;
  2452. }
  2453. if (wait_count == poll) {
  2454. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
  2455. rval = QLA_ERROR;
  2456. goto exit_process_pollwr;
  2457. }
  2458. ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
  2459. ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
  2460. wait_count = 0;
  2461. while (wait_count < poll) {
  2462. ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
  2463. if ((r_value & poll) != 0)
  2464. break;
  2465. wait_count++;
  2466. }
  2467. exit_process_pollwr:
  2468. return rval;
  2469. }
  2470. static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
  2471. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2472. uint32_t **d_ptr)
  2473. {
  2474. uint32_t sel_val1, sel_val2, t_sel_val, data, i;
  2475. uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
  2476. struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
  2477. uint32_t *data_ptr = *d_ptr;
  2478. rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
  2479. sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
  2480. sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
  2481. sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
  2482. sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
  2483. sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
  2484. read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
  2485. for (i = 0; i < rdmux2_hdr->op_count; i++) {
  2486. ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
  2487. t_sel_val = sel_val1 & sel_val_mask;
  2488. *data_ptr++ = cpu_to_le32(t_sel_val);
  2489. ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
  2490. ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
  2491. *data_ptr++ = cpu_to_le32(data);
  2492. ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
  2493. t_sel_val = sel_val2 & sel_val_mask;
  2494. *data_ptr++ = cpu_to_le32(t_sel_val);
  2495. ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
  2496. ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
  2497. *data_ptr++ = cpu_to_le32(data);
  2498. sel_val1 += rdmux2_hdr->select_value_stride;
  2499. sel_val2 += rdmux2_hdr->select_value_stride;
  2500. }
  2501. *d_ptr = data_ptr;
  2502. }
  2503. static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
  2504. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2505. uint32_t **d_ptr)
  2506. {
  2507. uint32_t poll_wait, poll_mask, r_value, data;
  2508. uint32_t addr_1, addr_2, value_1, value_2;
  2509. uint32_t *data_ptr = *d_ptr;
  2510. uint32_t rval = QLA_SUCCESS;
  2511. struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
  2512. poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
  2513. addr_1 = le32_to_cpu(poll_hdr->addr_1);
  2514. addr_2 = le32_to_cpu(poll_hdr->addr_2);
  2515. value_1 = le32_to_cpu(poll_hdr->value_1);
  2516. value_2 = le32_to_cpu(poll_hdr->value_2);
  2517. poll_mask = le32_to_cpu(poll_hdr->poll_mask);
  2518. ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
  2519. poll_wait = le32_to_cpu(poll_hdr->poll_wait);
  2520. while (1) {
  2521. ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
  2522. if ((r_value & poll_mask) != 0) {
  2523. break;
  2524. } else {
  2525. msleep(1);
  2526. if (--poll_wait == 0) {
  2527. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
  2528. __func__);
  2529. rval = QLA_ERROR;
  2530. goto exit_process_pollrdmwr;
  2531. }
  2532. }
  2533. }
  2534. ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
  2535. data &= le32_to_cpu(poll_hdr->modify_mask);
  2536. ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
  2537. ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
  2538. poll_wait = le32_to_cpu(poll_hdr->poll_wait);
  2539. while (1) {
  2540. ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
  2541. if ((r_value & poll_mask) != 0) {
  2542. break;
  2543. } else {
  2544. msleep(1);
  2545. if (--poll_wait == 0) {
  2546. ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
  2547. __func__);
  2548. rval = QLA_ERROR;
  2549. goto exit_process_pollrdmwr;
  2550. }
  2551. }
  2552. }
  2553. *data_ptr++ = cpu_to_le32(addr_2);
  2554. *data_ptr++ = cpu_to_le32(data);
  2555. *d_ptr = data_ptr;
  2556. exit_process_pollrdmwr:
  2557. return rval;
  2558. }
  2559. static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
  2560. struct qla8xxx_minidump_entry_hdr *entry_hdr,
  2561. uint32_t **d_ptr)
  2562. {
  2563. uint32_t fl_addr, u32_count, rval;
  2564. struct qla8xxx_minidump_entry_rdrom *rom_hdr;
  2565. uint32_t *data_ptr = *d_ptr;
  2566. rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
  2567. fl_addr = le32_to_cpu(rom_hdr->read_addr);
  2568. u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
  2569. DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
  2570. __func__, fl_addr, u32_count));
  2571. rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
  2572. (u8 *)(data_ptr), u32_count);
  2573. if (rval == QLA_ERROR) {
  2574. ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
  2575. __func__, u32_count);
  2576. goto exit_process_rdrom;
  2577. }
  2578. data_ptr += u32_count;
  2579. *d_ptr = data_ptr;
  2580. exit_process_rdrom:
  2581. return rval;
  2582. }
  2583. /**
  2584. * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
  2585. * @ha: pointer to adapter structure
  2586. **/
  2587. static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
  2588. {
  2589. int num_entry_hdr = 0;
  2590. struct qla8xxx_minidump_entry_hdr *entry_hdr;
  2591. struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
  2592. uint32_t *data_ptr;
  2593. uint32_t data_collected = 0;
  2594. int i, rval = QLA_ERROR;
  2595. uint64_t now;
  2596. uint32_t timestamp;
  2597. ha->fw_dump_skip_size = 0;
  2598. if (!ha->fw_dump) {
  2599. ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
  2600. __func__, ha->host_no);
  2601. return rval;
  2602. }
  2603. tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
  2604. ha->fw_dump_tmplt_hdr;
  2605. data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
  2606. ha->fw_dump_tmplt_size);
  2607. data_collected += ha->fw_dump_tmplt_size;
  2608. num_entry_hdr = tmplt_hdr->num_of_entries;
  2609. ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
  2610. __func__, data_ptr);
  2611. ql4_printk(KERN_INFO, ha,
  2612. "[%s]: no of entry headers in Template: 0x%x\n",
  2613. __func__, num_entry_hdr);
  2614. ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
  2615. __func__, ha->fw_dump_capture_mask);
  2616. ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
  2617. __func__, ha->fw_dump_size, ha->fw_dump_size);
  2618. /* Update current timestamp before taking dump */
  2619. now = get_jiffies_64();
  2620. timestamp = (u32)(jiffies_to_msecs(now) / 1000);
  2621. tmplt_hdr->driver_timestamp = timestamp;
  2622. entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
  2623. (((uint8_t *)ha->fw_dump_tmplt_hdr) +
  2624. tmplt_hdr->first_entry_offset);
  2625. if (is_qla8032(ha) || is_qla8042(ha))
  2626. tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
  2627. tmplt_hdr->ocm_window_reg[ha->func_num];
  2628. /* Walk through the entry headers - validate/perform required action */
  2629. for (i = 0; i < num_entry_hdr; i++) {
  2630. if (data_collected > ha->fw_dump_size) {
  2631. ql4_printk(KERN_INFO, ha,
  2632. "Data collected: [0x%x], Total Dump size: [0x%x]\n",
  2633. data_collected, ha->fw_dump_size);
  2634. return rval;
  2635. }
  2636. if (!(entry_hdr->d_ctrl.entry_capture_mask &
  2637. ha->fw_dump_capture_mask)) {
  2638. entry_hdr->d_ctrl.driver_flags |=
  2639. QLA8XXX_DBG_SKIPPED_FLAG;
  2640. goto skip_nxt_entry;
  2641. }
  2642. DEBUG2(ql4_printk(KERN_INFO, ha,
  2643. "Data collected: [0x%x], Dump size left:[0x%x]\n",
  2644. data_collected,
  2645. (ha->fw_dump_size - data_collected)));
  2646. /* Decode the entry type and take required action to capture
  2647. * debug data
  2648. */
  2649. switch (entry_hdr->entry_type) {
  2650. case QLA8XXX_RDEND:
  2651. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2652. break;
  2653. case QLA8XXX_CNTRL:
  2654. rval = qla4_8xxx_minidump_process_control(ha,
  2655. entry_hdr);
  2656. if (rval != QLA_SUCCESS) {
  2657. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2658. goto md_failed;
  2659. }
  2660. break;
  2661. case QLA8XXX_RDCRB:
  2662. qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
  2663. &data_ptr);
  2664. break;
  2665. case QLA8XXX_RDMEM:
  2666. rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
  2667. &data_ptr);
  2668. if (rval != QLA_SUCCESS) {
  2669. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2670. goto md_failed;
  2671. }
  2672. break;
  2673. case QLA8XXX_BOARD:
  2674. case QLA8XXX_RDROM:
  2675. if (is_qla8022(ha)) {
  2676. qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
  2677. &data_ptr);
  2678. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  2679. rval = qla4_83xx_minidump_process_rdrom(ha,
  2680. entry_hdr,
  2681. &data_ptr);
  2682. if (rval != QLA_SUCCESS)
  2683. qla4_8xxx_mark_entry_skipped(ha,
  2684. entry_hdr,
  2685. i);
  2686. }
  2687. break;
  2688. case QLA8XXX_L2DTG:
  2689. case QLA8XXX_L2ITG:
  2690. case QLA8XXX_L2DAT:
  2691. case QLA8XXX_L2INS:
  2692. rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
  2693. &data_ptr);
  2694. if (rval != QLA_SUCCESS) {
  2695. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2696. goto md_failed;
  2697. }
  2698. break;
  2699. case QLA8XXX_L1DTG:
  2700. case QLA8XXX_L1ITG:
  2701. case QLA8XXX_L1DAT:
  2702. case QLA8XXX_L1INS:
  2703. qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
  2704. &data_ptr);
  2705. break;
  2706. case QLA8XXX_RDOCM:
  2707. qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
  2708. &data_ptr);
  2709. break;
  2710. case QLA8XXX_RDMUX:
  2711. qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
  2712. &data_ptr);
  2713. break;
  2714. case QLA8XXX_QUEUE:
  2715. qla4_8xxx_minidump_process_queue(ha, entry_hdr,
  2716. &data_ptr);
  2717. break;
  2718. case QLA83XX_POLLRD:
  2719. if (is_qla8022(ha)) {
  2720. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2721. break;
  2722. }
  2723. rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
  2724. &data_ptr);
  2725. if (rval != QLA_SUCCESS)
  2726. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2727. break;
  2728. case QLA83XX_RDMUX2:
  2729. if (is_qla8022(ha)) {
  2730. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2731. break;
  2732. }
  2733. qla83xx_minidump_process_rdmux2(ha, entry_hdr,
  2734. &data_ptr);
  2735. break;
  2736. case QLA83XX_POLLRDMWR:
  2737. if (is_qla8022(ha)) {
  2738. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2739. break;
  2740. }
  2741. rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
  2742. &data_ptr);
  2743. if (rval != QLA_SUCCESS)
  2744. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2745. break;
  2746. case QLA8044_RDDFE:
  2747. rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
  2748. &data_ptr);
  2749. if (rval != QLA_SUCCESS)
  2750. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2751. break;
  2752. case QLA8044_RDMDIO:
  2753. rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
  2754. &data_ptr);
  2755. if (rval != QLA_SUCCESS)
  2756. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2757. break;
  2758. case QLA8044_POLLWR:
  2759. rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
  2760. &data_ptr);
  2761. if (rval != QLA_SUCCESS)
  2762. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2763. break;
  2764. case QLA8XXX_RDNOP:
  2765. default:
  2766. qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
  2767. break;
  2768. }
  2769. data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
  2770. skip_nxt_entry:
  2771. /* next entry in the template */
  2772. entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
  2773. (((uint8_t *)entry_hdr) +
  2774. entry_hdr->entry_size);
  2775. }
  2776. if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
  2777. ql4_printk(KERN_INFO, ha,
  2778. "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
  2779. data_collected, ha->fw_dump_size);
  2780. rval = QLA_ERROR;
  2781. goto md_failed;
  2782. }
  2783. DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
  2784. __func__, i));
  2785. md_failed:
  2786. return rval;
  2787. }
  2788. /**
  2789. * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
  2790. * @ha: pointer to adapter structure
  2791. * @code: uevent code to act upon
  2792. **/
  2793. static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
  2794. {
  2795. char event_string[40];
  2796. char *envp[] = { event_string, NULL };
  2797. switch (code) {
  2798. case QL4_UEVENT_CODE_FW_DUMP:
  2799. snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
  2800. ha->host_no);
  2801. break;
  2802. default:
  2803. /*do nothing*/
  2804. break;
  2805. }
  2806. kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
  2807. }
  2808. void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
  2809. {
  2810. if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
  2811. !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
  2812. if (!qla4_8xxx_collect_md_data(ha)) {
  2813. qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
  2814. set_bit(AF_82XX_FW_DUMPED, &ha->flags);
  2815. } else {
  2816. ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
  2817. __func__);
  2818. }
  2819. }
  2820. }
  2821. /**
  2822. * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
  2823. * @ha: pointer to adapter structure
  2824. *
  2825. * Note: IDC lock must be held upon entry
  2826. **/
  2827. int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
  2828. {
  2829. int rval = QLA_ERROR;
  2830. int i;
  2831. uint32_t old_count, count;
  2832. int need_reset = 0;
  2833. need_reset = ha->isp_ops->need_reset(ha);
  2834. if (need_reset) {
  2835. /* We are trying to perform a recovery here. */
  2836. if (test_bit(AF_FW_RECOVERY, &ha->flags))
  2837. ha->isp_ops->rom_lock_recovery(ha);
  2838. } else {
  2839. old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
  2840. for (i = 0; i < 10; i++) {
  2841. msleep(200);
  2842. count = qla4_8xxx_rd_direct(ha,
  2843. QLA8XXX_PEG_ALIVE_COUNTER);
  2844. if (count != old_count) {
  2845. rval = QLA_SUCCESS;
  2846. goto dev_ready;
  2847. }
  2848. }
  2849. ha->isp_ops->rom_lock_recovery(ha);
  2850. }
  2851. /* set to DEV_INITIALIZING */
  2852. ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
  2853. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  2854. QLA8XXX_DEV_INITIALIZING);
  2855. ha->isp_ops->idc_unlock(ha);
  2856. if (is_qla8022(ha))
  2857. qla4_8xxx_get_minidump(ha);
  2858. rval = ha->isp_ops->restart_firmware(ha);
  2859. ha->isp_ops->idc_lock(ha);
  2860. if (rval != QLA_SUCCESS) {
  2861. ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
  2862. qla4_8xxx_clear_drv_active(ha);
  2863. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  2864. QLA8XXX_DEV_FAILED);
  2865. return rval;
  2866. }
  2867. dev_ready:
  2868. ql4_printk(KERN_INFO, ha, "HW State: READY\n");
  2869. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
  2870. return rval;
  2871. }
  2872. /**
  2873. * qla4_82xx_need_reset_handler - Code to start reset sequence
  2874. * @ha: pointer to adapter structure
  2875. *
  2876. * Note: IDC lock must be held upon entry
  2877. **/
  2878. static void
  2879. qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
  2880. {
  2881. uint32_t dev_state, drv_state, drv_active;
  2882. uint32_t active_mask = 0xFFFFFFFF;
  2883. unsigned long reset_timeout;
  2884. ql4_printk(KERN_INFO, ha,
  2885. "Performing ISP error recovery\n");
  2886. if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
  2887. qla4_82xx_idc_unlock(ha);
  2888. ha->isp_ops->disable_intrs(ha);
  2889. qla4_82xx_idc_lock(ha);
  2890. }
  2891. if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
  2892. DEBUG2(ql4_printk(KERN_INFO, ha,
  2893. "%s(%ld): reset acknowledged\n",
  2894. __func__, ha->host_no));
  2895. qla4_8xxx_set_rst_ready(ha);
  2896. } else {
  2897. active_mask = (~(1 << (ha->func_num * 4)));
  2898. }
  2899. /* wait for 10 seconds for reset ack from all functions */
  2900. reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
  2901. drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
  2902. drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  2903. ql4_printk(KERN_INFO, ha,
  2904. "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
  2905. __func__, ha->host_no, drv_state, drv_active);
  2906. while (drv_state != (drv_active & active_mask)) {
  2907. if (time_after_eq(jiffies, reset_timeout)) {
  2908. ql4_printk(KERN_INFO, ha,
  2909. "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
  2910. DRIVER_NAME, drv_state, drv_active);
  2911. break;
  2912. }
  2913. /*
  2914. * When reset_owner times out, check which functions
  2915. * acked/did not ack
  2916. */
  2917. if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
  2918. ql4_printk(KERN_INFO, ha,
  2919. "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
  2920. __func__, ha->host_no, drv_state,
  2921. drv_active);
  2922. }
  2923. qla4_82xx_idc_unlock(ha);
  2924. msleep(1000);
  2925. qla4_82xx_idc_lock(ha);
  2926. drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
  2927. drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  2928. }
  2929. /* Clear RESET OWNER as we are not going to use it any further */
  2930. clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
  2931. dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  2932. ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
  2933. dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
  2934. /* Force to DEV_COLD unless someone else is starting a reset */
  2935. if (dev_state != QLA8XXX_DEV_INITIALIZING) {
  2936. ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
  2937. qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
  2938. qla4_8xxx_set_rst_ready(ha);
  2939. }
  2940. }
  2941. /**
  2942. * qla4_8xxx_need_qsnt_handler - Code to start qsnt
  2943. * @ha: pointer to adapter structure
  2944. **/
  2945. void
  2946. qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
  2947. {
  2948. ha->isp_ops->idc_lock(ha);
  2949. qla4_8xxx_set_qsnt_ready(ha);
  2950. ha->isp_ops->idc_unlock(ha);
  2951. }
  2952. static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
  2953. {
  2954. int idc_ver;
  2955. uint32_t drv_active;
  2956. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  2957. if (drv_active == (1 << (ha->func_num * 4))) {
  2958. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
  2959. QLA82XX_IDC_VERSION);
  2960. ql4_printk(KERN_INFO, ha,
  2961. "%s: IDC version updated to %d\n", __func__,
  2962. QLA82XX_IDC_VERSION);
  2963. } else {
  2964. idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
  2965. if (QLA82XX_IDC_VERSION != idc_ver) {
  2966. ql4_printk(KERN_INFO, ha,
  2967. "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
  2968. __func__, QLA82XX_IDC_VERSION, idc_ver);
  2969. }
  2970. }
  2971. }
  2972. static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
  2973. {
  2974. int idc_ver;
  2975. uint32_t drv_active;
  2976. int rval = QLA_SUCCESS;
  2977. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  2978. if (drv_active == (1 << ha->func_num)) {
  2979. idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
  2980. idc_ver &= (~0xFF);
  2981. idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
  2982. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
  2983. ql4_printk(KERN_INFO, ha,
  2984. "%s: IDC version updated to %d\n", __func__,
  2985. idc_ver);
  2986. } else {
  2987. idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
  2988. idc_ver &= 0xFF;
  2989. if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
  2990. ql4_printk(KERN_INFO, ha,
  2991. "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
  2992. __func__, QLA83XX_IDC_VER_MAJ_VALUE,
  2993. idc_ver);
  2994. rval = QLA_ERROR;
  2995. goto exit_set_idc_ver;
  2996. }
  2997. }
  2998. /* Update IDC_MINOR_VERSION */
  2999. idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
  3000. idc_ver &= ~(0x03 << (ha->func_num * 2));
  3001. idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
  3002. qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
  3003. exit_set_idc_ver:
  3004. return rval;
  3005. }
  3006. int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
  3007. {
  3008. uint32_t drv_active;
  3009. int rval = QLA_SUCCESS;
  3010. if (test_bit(AF_INIT_DONE, &ha->flags))
  3011. goto exit_update_idc_reg;
  3012. ha->isp_ops->idc_lock(ha);
  3013. qla4_8xxx_set_drv_active(ha);
  3014. /*
  3015. * If we are the first driver to load and
  3016. * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
  3017. */
  3018. if (is_qla8032(ha) || is_qla8042(ha)) {
  3019. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  3020. if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
  3021. qla4_83xx_clear_idc_dontreset(ha);
  3022. }
  3023. if (is_qla8022(ha)) {
  3024. qla4_82xx_set_idc_ver(ha);
  3025. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  3026. rval = qla4_83xx_set_idc_ver(ha);
  3027. if (rval == QLA_ERROR)
  3028. qla4_8xxx_clear_drv_active(ha);
  3029. }
  3030. ha->isp_ops->idc_unlock(ha);
  3031. exit_update_idc_reg:
  3032. return rval;
  3033. }
  3034. /**
  3035. * qla4_8xxx_device_state_handler - Adapter state machine
  3036. * @ha: pointer to host adapter structure.
  3037. *
  3038. * Note: IDC lock must be UNLOCKED upon entry
  3039. **/
  3040. int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
  3041. {
  3042. uint32_t dev_state;
  3043. int rval = QLA_SUCCESS;
  3044. unsigned long dev_init_timeout;
  3045. rval = qla4_8xxx_update_idc_reg(ha);
  3046. if (rval == QLA_ERROR)
  3047. goto exit_state_handler;
  3048. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  3049. DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
  3050. dev_state, dev_state < MAX_STATES ?
  3051. qdev_state[dev_state] : "Unknown"));
  3052. /* wait for 30 seconds for device to go ready */
  3053. dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
  3054. ha->isp_ops->idc_lock(ha);
  3055. while (1) {
  3056. if (time_after_eq(jiffies, dev_init_timeout)) {
  3057. ql4_printk(KERN_WARNING, ha,
  3058. "%s: Device Init Failed 0x%x = %s\n",
  3059. DRIVER_NAME,
  3060. dev_state, dev_state < MAX_STATES ?
  3061. qdev_state[dev_state] : "Unknown");
  3062. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  3063. QLA8XXX_DEV_FAILED);
  3064. }
  3065. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  3066. ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
  3067. dev_state, dev_state < MAX_STATES ?
  3068. qdev_state[dev_state] : "Unknown");
  3069. /* NOTE: Make sure idc unlocked upon exit of switch statement */
  3070. switch (dev_state) {
  3071. case QLA8XXX_DEV_READY:
  3072. goto exit;
  3073. case QLA8XXX_DEV_COLD:
  3074. rval = qla4_8xxx_device_bootstrap(ha);
  3075. goto exit;
  3076. case QLA8XXX_DEV_INITIALIZING:
  3077. ha->isp_ops->idc_unlock(ha);
  3078. msleep(1000);
  3079. ha->isp_ops->idc_lock(ha);
  3080. break;
  3081. case QLA8XXX_DEV_NEED_RESET:
  3082. /*
  3083. * For ISP8324 and ISP8042, if NEED_RESET is set by any
  3084. * driver, it should be honored, irrespective of
  3085. * IDC_CTRL DONTRESET_BIT0
  3086. */
  3087. if (is_qla8032(ha) || is_qla8042(ha)) {
  3088. qla4_83xx_need_reset_handler(ha);
  3089. } else if (is_qla8022(ha)) {
  3090. if (!ql4xdontresethba) {
  3091. qla4_82xx_need_reset_handler(ha);
  3092. /* Update timeout value after need
  3093. * reset handler */
  3094. dev_init_timeout = jiffies +
  3095. (ha->nx_dev_init_timeout * HZ);
  3096. } else {
  3097. ha->isp_ops->idc_unlock(ha);
  3098. msleep(1000);
  3099. ha->isp_ops->idc_lock(ha);
  3100. }
  3101. }
  3102. break;
  3103. case QLA8XXX_DEV_NEED_QUIESCENT:
  3104. /* idc locked/unlocked in handler */
  3105. qla4_8xxx_need_qsnt_handler(ha);
  3106. break;
  3107. case QLA8XXX_DEV_QUIESCENT:
  3108. ha->isp_ops->idc_unlock(ha);
  3109. msleep(1000);
  3110. ha->isp_ops->idc_lock(ha);
  3111. break;
  3112. case QLA8XXX_DEV_FAILED:
  3113. ha->isp_ops->idc_unlock(ha);
  3114. qla4xxx_dead_adapter_cleanup(ha);
  3115. rval = QLA_ERROR;
  3116. ha->isp_ops->idc_lock(ha);
  3117. goto exit;
  3118. default:
  3119. ha->isp_ops->idc_unlock(ha);
  3120. qla4xxx_dead_adapter_cleanup(ha);
  3121. rval = QLA_ERROR;
  3122. ha->isp_ops->idc_lock(ha);
  3123. goto exit;
  3124. }
  3125. }
  3126. exit:
  3127. ha->isp_ops->idc_unlock(ha);
  3128. exit_state_handler:
  3129. return rval;
  3130. }
  3131. int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
  3132. {
  3133. int retval;
  3134. /* clear the interrupt */
  3135. if (is_qla8032(ha) || is_qla8042(ha)) {
  3136. writel(0, &ha->qla4_83xx_reg->risc_intr);
  3137. readl(&ha->qla4_83xx_reg->risc_intr);
  3138. } else if (is_qla8022(ha)) {
  3139. writel(0, &ha->qla4_82xx_reg->host_int);
  3140. readl(&ha->qla4_82xx_reg->host_int);
  3141. }
  3142. retval = qla4_8xxx_device_state_handler(ha);
  3143. /* Initialize request and response queues. */
  3144. if (retval == QLA_SUCCESS)
  3145. qla4xxx_init_rings(ha);
  3146. if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
  3147. retval = qla4xxx_request_irqs(ha);
  3148. return retval;
  3149. }
  3150. /*****************************************************************************/
  3151. /* Flash Manipulation Routines */
  3152. /*****************************************************************************/
  3153. #define OPTROM_BURST_SIZE 0x1000
  3154. #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
  3155. #define FARX_DATA_FLAG BIT_31
  3156. #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
  3157. #define FARX_ACCESS_FLASH_DATA 0x7FF00000
  3158. static inline uint32_t
  3159. flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
  3160. {
  3161. return hw->flash_conf_off | faddr;
  3162. }
  3163. static inline uint32_t
  3164. flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
  3165. {
  3166. return hw->flash_data_off | faddr;
  3167. }
  3168. static uint32_t *
  3169. qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
  3170. uint32_t faddr, uint32_t length)
  3171. {
  3172. uint32_t i;
  3173. uint32_t val;
  3174. int loops = 0;
  3175. while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
  3176. udelay(100);
  3177. cond_resched();
  3178. loops++;
  3179. }
  3180. if (loops >= 50000) {
  3181. ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
  3182. return dwptr;
  3183. }
  3184. /* Dword reads to flash. */
  3185. for (i = 0; i < length/4; i++, faddr += 4) {
  3186. if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
  3187. ql4_printk(KERN_WARNING, ha,
  3188. "Do ROM fast read failed\n");
  3189. goto done_read;
  3190. }
  3191. dwptr[i] = __constant_cpu_to_le32(val);
  3192. }
  3193. done_read:
  3194. qla4_82xx_rom_unlock(ha);
  3195. return dwptr;
  3196. }
  3197. /*
  3198. * Address and length are byte address
  3199. */
  3200. static uint8_t *
  3201. qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
  3202. uint32_t offset, uint32_t length)
  3203. {
  3204. qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
  3205. return buf;
  3206. }
  3207. static int
  3208. qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
  3209. {
  3210. const char *loc, *locations[] = { "DEF", "PCI" };
  3211. /*
  3212. * FLT-location structure resides after the last PCI region.
  3213. */
  3214. /* Begin with sane defaults. */
  3215. loc = locations[0];
  3216. *start = FA_FLASH_LAYOUT_ADDR_82;
  3217. DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
  3218. return QLA_SUCCESS;
  3219. }
  3220. static void
  3221. qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
  3222. {
  3223. const char *loc, *locations[] = { "DEF", "FLT" };
  3224. uint16_t *wptr;
  3225. uint16_t cnt, chksum;
  3226. uint32_t start, status;
  3227. struct qla_flt_header *flt;
  3228. struct qla_flt_region *region;
  3229. struct ql82xx_hw_data *hw = &ha->hw;
  3230. hw->flt_region_flt = flt_addr;
  3231. wptr = (uint16_t *)ha->request_ring;
  3232. flt = (struct qla_flt_header *)ha->request_ring;
  3233. region = (struct qla_flt_region *)&flt[1];
  3234. if (is_qla8022(ha)) {
  3235. qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
  3236. flt_addr << 2, OPTROM_BURST_SIZE);
  3237. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  3238. status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
  3239. (uint8_t *)ha->request_ring,
  3240. 0x400);
  3241. if (status != QLA_SUCCESS)
  3242. goto no_flash_data;
  3243. }
  3244. if (*wptr == __constant_cpu_to_le16(0xffff))
  3245. goto no_flash_data;
  3246. if (flt->version != __constant_cpu_to_le16(1)) {
  3247. DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
  3248. "version=0x%x length=0x%x checksum=0x%x.\n",
  3249. le16_to_cpu(flt->version), le16_to_cpu(flt->length),
  3250. le16_to_cpu(flt->checksum)));
  3251. goto no_flash_data;
  3252. }
  3253. cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
  3254. for (chksum = 0; cnt; cnt--)
  3255. chksum += le16_to_cpu(*wptr++);
  3256. if (chksum) {
  3257. DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
  3258. "version=0x%x length=0x%x checksum=0x%x.\n",
  3259. le16_to_cpu(flt->version), le16_to_cpu(flt->length),
  3260. chksum));
  3261. goto no_flash_data;
  3262. }
  3263. loc = locations[1];
  3264. cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
  3265. for ( ; cnt; cnt--, region++) {
  3266. /* Store addresses as DWORD offsets. */
  3267. start = le32_to_cpu(region->start) >> 2;
  3268. DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
  3269. "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
  3270. le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
  3271. switch (le32_to_cpu(region->code) & 0xff) {
  3272. case FLT_REG_FDT:
  3273. hw->flt_region_fdt = start;
  3274. break;
  3275. case FLT_REG_BOOT_CODE_82:
  3276. hw->flt_region_boot = start;
  3277. break;
  3278. case FLT_REG_FW_82:
  3279. case FLT_REG_FW_82_1:
  3280. hw->flt_region_fw = start;
  3281. break;
  3282. case FLT_REG_BOOTLOAD_82:
  3283. hw->flt_region_bootload = start;
  3284. break;
  3285. case FLT_REG_ISCSI_PARAM:
  3286. hw->flt_iscsi_param = start;
  3287. break;
  3288. case FLT_REG_ISCSI_CHAP:
  3289. hw->flt_region_chap = start;
  3290. hw->flt_chap_size = le32_to_cpu(region->size);
  3291. break;
  3292. case FLT_REG_ISCSI_DDB:
  3293. hw->flt_region_ddb = start;
  3294. hw->flt_ddb_size = le32_to_cpu(region->size);
  3295. break;
  3296. }
  3297. }
  3298. goto done;
  3299. no_flash_data:
  3300. /* Use hardcoded defaults. */
  3301. loc = locations[0];
  3302. hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
  3303. hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
  3304. hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
  3305. hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
  3306. hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2;
  3307. hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
  3308. hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2;
  3309. hw->flt_ddb_size = FA_FLASH_DDB_SIZE;
  3310. done:
  3311. DEBUG2(ql4_printk(KERN_INFO, ha,
  3312. "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n",
  3313. loc, hw->flt_region_flt, hw->flt_region_fdt,
  3314. hw->flt_region_boot, hw->flt_region_bootload,
  3315. hw->flt_region_fw, hw->flt_region_chap,
  3316. hw->flt_chap_size, hw->flt_region_ddb,
  3317. hw->flt_ddb_size));
  3318. }
  3319. static void
  3320. qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
  3321. {
  3322. #define FLASH_BLK_SIZE_4K 0x1000
  3323. #define FLASH_BLK_SIZE_32K 0x8000
  3324. #define FLASH_BLK_SIZE_64K 0x10000
  3325. const char *loc, *locations[] = { "MID", "FDT" };
  3326. uint16_t cnt, chksum;
  3327. uint16_t *wptr;
  3328. struct qla_fdt_layout *fdt;
  3329. uint16_t mid = 0;
  3330. uint16_t fid = 0;
  3331. struct ql82xx_hw_data *hw = &ha->hw;
  3332. hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  3333. hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
  3334. wptr = (uint16_t *)ha->request_ring;
  3335. fdt = (struct qla_fdt_layout *)ha->request_ring;
  3336. qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
  3337. hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
  3338. if (*wptr == __constant_cpu_to_le16(0xffff))
  3339. goto no_flash_data;
  3340. if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
  3341. fdt->sig[3] != 'D')
  3342. goto no_flash_data;
  3343. for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
  3344. cnt++)
  3345. chksum += le16_to_cpu(*wptr++);
  3346. if (chksum) {
  3347. DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
  3348. "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
  3349. le16_to_cpu(fdt->version)));
  3350. goto no_flash_data;
  3351. }
  3352. loc = locations[1];
  3353. mid = le16_to_cpu(fdt->man_id);
  3354. fid = le16_to_cpu(fdt->id);
  3355. hw->fdt_wrt_disable = fdt->wrt_disable_bits;
  3356. hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
  3357. hw->fdt_block_size = le32_to_cpu(fdt->block_size);
  3358. if (fdt->unprotect_sec_cmd) {
  3359. hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
  3360. fdt->unprotect_sec_cmd);
  3361. hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
  3362. flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
  3363. flash_conf_addr(hw, 0x0336);
  3364. }
  3365. goto done;
  3366. no_flash_data:
  3367. loc = locations[0];
  3368. hw->fdt_block_size = FLASH_BLK_SIZE_64K;
  3369. done:
  3370. DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
  3371. "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
  3372. hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
  3373. hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
  3374. hw->fdt_block_size));
  3375. }
  3376. static void
  3377. qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
  3378. {
  3379. #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
  3380. uint32_t *wptr;
  3381. if (!is_qla8022(ha))
  3382. return;
  3383. wptr = (uint32_t *)ha->request_ring;
  3384. qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
  3385. QLA82XX_IDC_PARAM_ADDR , 8);
  3386. if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
  3387. ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
  3388. ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
  3389. } else {
  3390. ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
  3391. ha->nx_reset_timeout = le32_to_cpu(*wptr);
  3392. }
  3393. DEBUG2(ql4_printk(KERN_DEBUG, ha,
  3394. "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
  3395. DEBUG2(ql4_printk(KERN_DEBUG, ha,
  3396. "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
  3397. return;
  3398. }
  3399. void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  3400. int in_count)
  3401. {
  3402. int i;
  3403. /* Load all mailbox registers, except mailbox 0. */
  3404. for (i = 1; i < in_count; i++)
  3405. writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
  3406. /* Wakeup firmware */
  3407. writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
  3408. readl(&ha->qla4_82xx_reg->mailbox_in[0]);
  3409. writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
  3410. readl(&ha->qla4_82xx_reg->hint);
  3411. }
  3412. void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  3413. {
  3414. int intr_status;
  3415. intr_status = readl(&ha->qla4_82xx_reg->host_int);
  3416. if (intr_status & ISRX_82XX_RISC_INT) {
  3417. ha->mbox_status_count = out_count;
  3418. intr_status = readl(&ha->qla4_82xx_reg->host_status);
  3419. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  3420. if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  3421. (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled))
  3422. qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
  3423. 0xfbff);
  3424. }
  3425. }
  3426. int
  3427. qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
  3428. {
  3429. int ret;
  3430. uint32_t flt_addr;
  3431. ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
  3432. if (ret != QLA_SUCCESS)
  3433. return ret;
  3434. qla4_8xxx_get_flt_info(ha, flt_addr);
  3435. if (is_qla8022(ha)) {
  3436. qla4_82xx_get_fdt_info(ha);
  3437. qla4_82xx_get_idc_param(ha);
  3438. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  3439. qla4_83xx_get_idc_param(ha);
  3440. }
  3441. return QLA_SUCCESS;
  3442. }
  3443. /**
  3444. * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
  3445. * @ha: pointer to host adapter structure.
  3446. *
  3447. * Remarks:
  3448. * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
  3449. * not be available after successful return. Driver must cleanup potential
  3450. * outstanding I/O's after calling this funcion.
  3451. **/
  3452. int
  3453. qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
  3454. {
  3455. int status;
  3456. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3457. uint32_t mbox_sts[MBOX_REG_COUNT];
  3458. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3459. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3460. mbox_cmd[0] = MBOX_CMD_STOP_FW;
  3461. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
  3462. &mbox_cmd[0], &mbox_sts[0]);
  3463. DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
  3464. __func__, status));
  3465. return status;
  3466. }
  3467. /**
  3468. * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
  3469. * @ha: pointer to host adapter structure.
  3470. **/
  3471. int
  3472. qla4_82xx_isp_reset(struct scsi_qla_host *ha)
  3473. {
  3474. int rval;
  3475. uint32_t dev_state;
  3476. qla4_82xx_idc_lock(ha);
  3477. dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  3478. if (dev_state == QLA8XXX_DEV_READY) {
  3479. ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
  3480. qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3481. QLA8XXX_DEV_NEED_RESET);
  3482. set_bit(AF_8XXX_RST_OWNER, &ha->flags);
  3483. } else
  3484. ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
  3485. qla4_82xx_idc_unlock(ha);
  3486. rval = qla4_8xxx_device_state_handler(ha);
  3487. qla4_82xx_idc_lock(ha);
  3488. qla4_8xxx_clear_rst_ready(ha);
  3489. qla4_82xx_idc_unlock(ha);
  3490. if (rval == QLA_SUCCESS) {
  3491. ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
  3492. clear_bit(AF_FW_RECOVERY, &ha->flags);
  3493. }
  3494. return rval;
  3495. }
  3496. /**
  3497. * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
  3498. * @ha: pointer to host adapter structure.
  3499. *
  3500. **/
  3501. int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
  3502. {
  3503. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3504. uint32_t mbox_sts[MBOX_REG_COUNT];
  3505. struct mbx_sys_info *sys_info;
  3506. dma_addr_t sys_info_dma;
  3507. int status = QLA_ERROR;
  3508. sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
  3509. &sys_info_dma, GFP_KERNEL);
  3510. if (sys_info == NULL) {
  3511. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  3512. ha->host_no, __func__));
  3513. return status;
  3514. }
  3515. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3516. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3517. mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
  3518. mbox_cmd[1] = LSDW(sys_info_dma);
  3519. mbox_cmd[2] = MSDW(sys_info_dma);
  3520. mbox_cmd[4] = sizeof(*sys_info);
  3521. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
  3522. &mbox_sts[0]) != QLA_SUCCESS) {
  3523. DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
  3524. ha->host_no, __func__));
  3525. goto exit_validate_mac82;
  3526. }
  3527. /* Make sure we receive the minimum required data to cache internally */
  3528. if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
  3529. offsetof(struct mbx_sys_info, reserved)) {
  3530. DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
  3531. " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
  3532. goto exit_validate_mac82;
  3533. }
  3534. /* Save M.A.C. address & serial_number */
  3535. ha->port_num = sys_info->port_num;
  3536. memcpy(ha->my_mac, &sys_info->mac_addr[0],
  3537. min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
  3538. memcpy(ha->serial_number, &sys_info->serial_number,
  3539. min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
  3540. memcpy(ha->model_name, &sys_info->board_id_str,
  3541. min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
  3542. ha->phy_port_cnt = sys_info->phys_port_cnt;
  3543. ha->phy_port_num = sys_info->port_num;
  3544. ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
  3545. DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n",
  3546. ha->host_no, __func__, ha->my_mac, ha->serial_number));
  3547. status = QLA_SUCCESS;
  3548. exit_validate_mac82:
  3549. dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
  3550. sys_info_dma);
  3551. return status;
  3552. }
  3553. /* Interrupt handling helpers. */
  3554. int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
  3555. {
  3556. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3557. uint32_t mbox_sts[MBOX_REG_COUNT];
  3558. DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
  3559. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3560. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3561. mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
  3562. mbox_cmd[1] = INTR_ENABLE;
  3563. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  3564. &mbox_sts[0]) != QLA_SUCCESS) {
  3565. DEBUG2(ql4_printk(KERN_INFO, ha,
  3566. "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
  3567. __func__, mbox_sts[0]));
  3568. return QLA_ERROR;
  3569. }
  3570. return QLA_SUCCESS;
  3571. }
  3572. int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
  3573. {
  3574. uint32_t mbox_cmd[MBOX_REG_COUNT];
  3575. uint32_t mbox_sts[MBOX_REG_COUNT];
  3576. DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
  3577. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  3578. memset(&mbox_sts, 0, sizeof(mbox_sts));
  3579. mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
  3580. mbox_cmd[1] = INTR_DISABLE;
  3581. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  3582. &mbox_sts[0]) != QLA_SUCCESS) {
  3583. DEBUG2(ql4_printk(KERN_INFO, ha,
  3584. "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
  3585. __func__, mbox_sts[0]));
  3586. return QLA_ERROR;
  3587. }
  3588. return QLA_SUCCESS;
  3589. }
  3590. void
  3591. qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
  3592. {
  3593. qla4_8xxx_intr_enable(ha);
  3594. spin_lock_irq(&ha->hardware_lock);
  3595. /* BIT 10 - reset */
  3596. qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
  3597. spin_unlock_irq(&ha->hardware_lock);
  3598. set_bit(AF_INTERRUPTS_ON, &ha->flags);
  3599. }
  3600. void
  3601. qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
  3602. {
  3603. if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
  3604. qla4_8xxx_intr_disable(ha);
  3605. spin_lock_irq(&ha->hardware_lock);
  3606. /* BIT 10 - set */
  3607. qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
  3608. spin_unlock_irq(&ha->hardware_lock);
  3609. }
  3610. int
  3611. qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
  3612. {
  3613. int ret;
  3614. ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES,
  3615. QLA_MSIX_ENTRIES, PCI_IRQ_MSIX);
  3616. if (ret < 0) {
  3617. ql4_printk(KERN_WARNING, ha,
  3618. "MSI-X: Failed to enable support -- %d/%d\n",
  3619. QLA_MSIX_ENTRIES, ret);
  3620. return ret;
  3621. }
  3622. ret = request_irq(pci_irq_vector(ha->pdev, 0),
  3623. qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)",
  3624. ha);
  3625. if (ret)
  3626. goto out_free_vectors;
  3627. ret = request_irq(pci_irq_vector(ha->pdev, 1),
  3628. qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha);
  3629. if (ret)
  3630. goto out_free_default_irq;
  3631. return 0;
  3632. out_free_default_irq:
  3633. free_irq(pci_irq_vector(ha->pdev, 0), ha);
  3634. out_free_vectors:
  3635. pci_free_irq_vectors(ha->pdev);
  3636. return ret;
  3637. }
  3638. int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
  3639. {
  3640. int status = QLA_SUCCESS;
  3641. /* Dont retry adapter initialization if IRQ allocation failed */
  3642. if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
  3643. ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
  3644. __func__);
  3645. status = QLA_ERROR;
  3646. goto exit_init_adapter_failure;
  3647. }
  3648. /* Since interrupts are registered in start_firmware for
  3649. * 8xxx, release them here if initialize_adapter fails
  3650. * and retry adapter initialization */
  3651. qla4xxx_free_irqs(ha);
  3652. exit_init_adapter_failure:
  3653. return status;
  3654. }