ql4_fw.h 45 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * QLogic iSCSI HBA Driver
  4. * Copyright (c) 2003-2013 QLogic Corporation
  5. */
  6. #ifndef _QLA4X_FW_H
  7. #define _QLA4X_FW_H
  8. #define MAX_PRST_DEV_DB_ENTRIES 64
  9. #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
  10. #define MAX_DEV_DB_ENTRIES 512
  11. #define MAX_DEV_DB_ENTRIES_40XX 256
  12. /*************************************************************************
  13. *
  14. * ISP 4010 I/O Register Set Structure and Definitions
  15. *
  16. *************************************************************************/
  17. struct port_ctrl_stat_regs {
  18. __le32 ext_hw_conf; /* 0x50 R/W */
  19. __le32 rsrvd0; /* 0x54 */
  20. __le32 port_ctrl; /* 0x58 */
  21. __le32 port_status; /* 0x5c */
  22. __le32 rsrvd1[32]; /* 0x60-0xdf */
  23. __le32 gp_out; /* 0xe0 */
  24. __le32 gp_in; /* 0xe4 */
  25. __le32 rsrvd2[5]; /* 0xe8-0xfb */
  26. __le32 port_err_status; /* 0xfc */
  27. };
  28. struct host_mem_cfg_regs {
  29. __le32 rsrvd0[12]; /* 0x50-0x79 */
  30. __le32 req_q_out; /* 0x80 */
  31. __le32 rsrvd1[31]; /* 0x84-0xFF */
  32. };
  33. /*
  34. * ISP 82xx I/O Register Set structure definitions.
  35. */
  36. struct device_reg_82xx {
  37. __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */
  38. __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */
  39. __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */
  40. __le32 reserve2[63]; /* Response Queue In-Pointer. */
  41. __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */
  42. __le32 reserve3[63]; /* Response Queue Out-Pointer. */
  43. __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */
  44. __le32 reserve4[24];
  45. __le32 hint; /* 0x0380 (R/W): Host interrupt register */
  46. #define HINT_MBX_INT_PENDING BIT_0
  47. __le32 reserve5[31];
  48. __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */
  49. __le32 reserve6[56];
  50. __le32 host_status; /* Offset 0x500 (R): host status */
  51. #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */
  52. #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */
  53. __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */
  54. #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
  55. };
  56. /* ISP 83xx I/O Register Set structure */
  57. struct device_reg_83xx {
  58. __le32 mailbox_in[16]; /* 0x0000 */
  59. __le32 reserve1[496]; /* 0x0040 */
  60. __le32 mailbox_out[16]; /* 0x0800 */
  61. __le32 reserve2[496];
  62. __le32 mbox_int; /* 0x1000 */
  63. __le32 reserve3[63];
  64. __le32 req_q_out; /* 0x1100 */
  65. __le32 reserve4[63];
  66. __le32 rsp_q_in; /* 0x1200 */
  67. __le32 reserve5[1919];
  68. __le32 req_q_in; /* 0x3000 */
  69. __le32 reserve6[3];
  70. __le32 iocb_int_mask; /* 0x3010 */
  71. __le32 reserve7[3];
  72. __le32 rsp_q_out; /* 0x3020 */
  73. __le32 reserve8[3];
  74. __le32 anonymousbuff; /* 0x3030 */
  75. __le32 mb_int_mask; /* 0x3034 */
  76. __le32 host_intr; /* 0x3038 - Host Interrupt Register */
  77. __le32 risc_intr; /* 0x303C - RISC Interrupt Register */
  78. __le32 reserve9[544];
  79. __le32 leg_int_ptr; /* 0x38C0 - Legacy Interrupt Pointer Register */
  80. __le32 leg_int_trig; /* 0x38C4 - Legacy Interrupt Trigger Control */
  81. __le32 leg_int_mask; /* 0x38C8 - Legacy Interrupt Mask Register */
  82. };
  83. #define INT_ENABLE_FW_MB (1 << 2)
  84. #define INT_MASK_FW_MB (1 << 2)
  85. /* remote register set (access via PCI memory read/write) */
  86. struct isp_reg {
  87. #define MBOX_REG_COUNT 8
  88. __le32 mailbox[MBOX_REG_COUNT];
  89. __le32 flash_address; /* 0x20 */
  90. __le32 flash_data;
  91. __le32 ctrl_status;
  92. union {
  93. struct {
  94. __le32 nvram;
  95. __le32 reserved1[2]; /* 0x30 */
  96. } __attribute__ ((packed)) isp4010;
  97. struct {
  98. __le32 intr_mask;
  99. __le32 nvram; /* 0x30 */
  100. __le32 semaphore;
  101. } __attribute__ ((packed)) isp4022;
  102. } u1;
  103. __le32 req_q_in; /* SCSI Request Queue Producer Index */
  104. __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */
  105. __le32 reserved2[4]; /* 0x40 */
  106. union {
  107. struct {
  108. __le32 ext_hw_conf; /* 0x50 */
  109. __le32 flow_ctrl;
  110. __le32 port_ctrl;
  111. __le32 port_status;
  112. __le32 reserved3[8]; /* 0x60 */
  113. __le32 req_q_out; /* 0x80 */
  114. __le32 reserved4[23]; /* 0x84 */
  115. __le32 gp_out; /* 0xe0 */
  116. __le32 gp_in;
  117. __le32 reserved5[5];
  118. __le32 port_err_status; /* 0xfc */
  119. } __attribute__ ((packed)) isp4010;
  120. struct {
  121. union {
  122. struct port_ctrl_stat_regs p0;
  123. struct host_mem_cfg_regs p1;
  124. };
  125. } __attribute__ ((packed)) isp4022;
  126. } u2;
  127. }; /* 256 x100 */
  128. /* Semaphore Defines for 4010 */
  129. #define QL4010_DRVR_SEM_BITS 0x00000030
  130. #define QL4010_GPIO_SEM_BITS 0x000000c0
  131. #define QL4010_SDRAM_SEM_BITS 0x00000300
  132. #define QL4010_PHY_SEM_BITS 0x00000c00
  133. #define QL4010_NVRAM_SEM_BITS 0x00003000
  134. #define QL4010_FLASH_SEM_BITS 0x0000c000
  135. #define QL4010_DRVR_SEM_MASK 0x00300000
  136. #define QL4010_GPIO_SEM_MASK 0x00c00000
  137. #define QL4010_SDRAM_SEM_MASK 0x03000000
  138. #define QL4010_PHY_SEM_MASK 0x0c000000
  139. #define QL4010_NVRAM_SEM_MASK 0x30000000
  140. #define QL4010_FLASH_SEM_MASK 0xc0000000
  141. /* Semaphore Defines for 4022 */
  142. #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
  143. #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
  144. #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
  145. #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
  146. #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
  147. #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
  148. #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
  149. /* nvram address for 4032 */
  150. #define NVRAM_PORT0_BOOT_MODE 0x03b1
  151. #define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2
  152. #define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb
  153. #define NVRAM_PORT1_BOOT_MODE 0x07b1
  154. #define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2
  155. #define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb
  156. /* Page # defines for 4022 */
  157. #define PORT_CTRL_STAT_PAGE 0 /* 4022 */
  158. #define HOST_MEM_CFG_PAGE 1 /* 4022 */
  159. #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */
  160. #define PROT_STAT_PAGE 3 /* 4022 */
  161. /* Register Mask - sets corresponding mask bits in the upper word */
  162. static inline uint32_t set_rmask(uint32_t val)
  163. {
  164. return (val & 0xffff) | (val << 16);
  165. }
  166. static inline uint32_t clr_rmask(uint32_t val)
  167. {
  168. return 0 | (val << 16);
  169. }
  170. /* ctrl_status definitions */
  171. #define CSR_SCSI_PAGE_SELECT 0x00000003
  172. #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */
  173. #define CSR_SCSI_RESET_INTR 0x00000008
  174. #define CSR_SCSI_COMPLETION_INTR 0x00000010
  175. #define CSR_SCSI_PROCESSOR_INTR 0x00000020
  176. #define CSR_INTR_RISC 0x00000040
  177. #define CSR_BOOT_ENABLE 0x00000080
  178. #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */
  179. #define CSR_FUNC_NUM 0x00000700 /* 4022 */
  180. #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */
  181. #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */
  182. #define CSR_FATAL_ERROR 0x00004000
  183. #define CSR_SOFT_RESET 0x00008000
  184. #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM
  185. #define ISP_CONTROL_FN0_SCSI 0x0500
  186. #define ISP_CONTROL_FN1_SCSI 0x0700
  187. #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\
  188. CSR_SCSI_PROCESSOR_INTR |\
  189. CSR_SCSI_RESET_INTR)
  190. /* ISP InterruptMask definitions */
  191. #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */
  192. /* ISP 4022 nvram definitions */
  193. #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */
  194. #define QL4010_NVRAM_SIZE 0x200
  195. #define QL40X2_NVRAM_SIZE 0x800
  196. /* ISP port_status definitions */
  197. /* ISP Semaphore definitions */
  198. /* ISP General Purpose Output definitions */
  199. #define GPOR_TOPCAT_RESET 0x00000004
  200. /* shadow registers (DMA'd from HA to system memory. read only) */
  201. struct shadow_regs {
  202. /* SCSI Request Queue Consumer Index */
  203. __le32 req_q_out; /* 0 x0 R */
  204. /* SCSI Completion Queue Producer Index */
  205. __le32 rsp_q_in; /* 4 x4 R */
  206. }; /* 8 x8 */
  207. /* External hardware configuration register */
  208. union external_hw_config_reg {
  209. struct {
  210. /* FIXME: Do we even need this? All values are
  211. * referred to by 16 bit quantities. Platform and
  212. * endianess issues. */
  213. __le32 bReserved0:1;
  214. __le32 bSDRAMProtectionMethod:2;
  215. __le32 bSDRAMBanks:1;
  216. __le32 bSDRAMChipWidth:1;
  217. __le32 bSDRAMChipSize:2;
  218. __le32 bParityDisable:1;
  219. __le32 bExternalMemoryType:1;
  220. __le32 bFlashBIOSWriteEnable:1;
  221. __le32 bFlashUpperBankSelect:1;
  222. __le32 bWriteBurst:2;
  223. __le32 bReserved1:3;
  224. __le32 bMask:16;
  225. };
  226. uint32_t Asuint32_t;
  227. };
  228. /* 82XX Support start */
  229. /* 82xx Default FLT Addresses */
  230. #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
  231. #define FA_FLASH_DESCR_ADDR_82 0xFC000
  232. #define FA_BOOT_LOAD_ADDR_82 0x04000
  233. #define FA_BOOT_CODE_ADDR_82 0x20000
  234. #define FA_RISC_CODE_ADDR_82 0x40000
  235. #define FA_GOLD_RISC_CODE_ADDR_82 0x80000
  236. #define FA_FLASH_ISCSI_CHAP 0x540000
  237. #define FA_FLASH_CHAP_SIZE 0xC0000
  238. #define FA_FLASH_ISCSI_DDB 0x420000
  239. #define FA_FLASH_DDB_SIZE 0x080000
  240. /* Flash Description Table */
  241. struct qla_fdt_layout {
  242. uint8_t sig[4];
  243. uint16_t version;
  244. uint16_t len;
  245. uint16_t checksum;
  246. uint8_t unused1[2];
  247. uint8_t model[16];
  248. uint16_t man_id;
  249. uint16_t id;
  250. uint8_t flags;
  251. uint8_t erase_cmd;
  252. uint8_t alt_erase_cmd;
  253. uint8_t wrt_enable_cmd;
  254. uint8_t wrt_enable_bits;
  255. uint8_t wrt_sts_reg_cmd;
  256. uint8_t unprotect_sec_cmd;
  257. uint8_t read_man_id_cmd;
  258. uint32_t block_size;
  259. uint32_t alt_block_size;
  260. uint32_t flash_size;
  261. uint32_t wrt_enable_data;
  262. uint8_t read_id_addr_len;
  263. uint8_t wrt_disable_bits;
  264. uint8_t read_dev_id_len;
  265. uint8_t chip_erase_cmd;
  266. uint16_t read_timeout;
  267. uint8_t protect_sec_cmd;
  268. uint8_t unused2[65];
  269. };
  270. /* Flash Layout Table */
  271. struct qla_flt_location {
  272. uint8_t sig[4];
  273. uint16_t start_lo;
  274. uint16_t start_hi;
  275. uint8_t version;
  276. uint8_t unused[5];
  277. uint16_t checksum;
  278. };
  279. struct qla_flt_header {
  280. uint16_t version;
  281. uint16_t length;
  282. uint16_t checksum;
  283. uint16_t unused;
  284. };
  285. /* 82xx FLT Regions */
  286. #define FLT_REG_FDT 0x1a
  287. #define FLT_REG_FLT 0x1c
  288. #define FLT_REG_BOOTLOAD_82 0x72
  289. #define FLT_REG_FW_82 0x74
  290. #define FLT_REG_FW_82_1 0x97
  291. #define FLT_REG_GOLD_FW_82 0x75
  292. #define FLT_REG_BOOT_CODE_82 0x78
  293. #define FLT_REG_ISCSI_PARAM 0x65
  294. #define FLT_REG_ISCSI_CHAP 0x63
  295. #define FLT_REG_ISCSI_DDB 0x6A
  296. struct qla_flt_region {
  297. uint32_t code;
  298. uint32_t size;
  299. uint32_t start;
  300. uint32_t end;
  301. };
  302. /*************************************************************************
  303. *
  304. * Mailbox Commands Structures and Definitions
  305. *
  306. *************************************************************************/
  307. /* Mailbox command definitions */
  308. #define MBOX_CMD_ABOUT_FW 0x0009
  309. #define MBOX_CMD_PING 0x000B
  310. #define PING_IPV6_PROTOCOL_ENABLE 0x1
  311. #define PING_IPV6_LINKLOCAL_ADDR 0x4
  312. #define PING_IPV6_ADDR0 0x8
  313. #define PING_IPV6_ADDR1 0xC
  314. #define MBOX_CMD_ENABLE_INTRS 0x0010
  315. #define INTR_DISABLE 0
  316. #define INTR_ENABLE 1
  317. #define MBOX_CMD_STOP_FW 0x0014
  318. #define MBOX_CMD_ABORT_TASK 0x0015
  319. #define MBOX_CMD_LUN_RESET 0x0016
  320. #define MBOX_CMD_TARGET_WARM_RESET 0x0017
  321. #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E
  322. #define MBOX_CMD_GET_FW_STATUS 0x001F
  323. #define MBOX_CMD_SET_ISNS_SERVICE 0x0021
  324. #define ISNS_DISABLE 0
  325. #define ISNS_ENABLE 1
  326. #define MBOX_CMD_COPY_FLASH 0x0024
  327. #define MBOX_CMD_WRITE_FLASH 0x0025
  328. #define MBOX_CMD_READ_FLASH 0x0026
  329. #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031
  330. #define MBOX_CMD_CONN_OPEN 0x0074
  331. #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056
  332. #define DDB_NOT_LOGGED_IN 0x09
  333. #define LOGOUT_OPTION_CLOSE_SESSION 0x0002
  334. #define LOGOUT_OPTION_RELOGIN 0x0004
  335. #define LOGOUT_OPTION_FREE_DDB 0x0008
  336. #define MBOX_CMD_SET_PARAM 0x0059
  337. #define SET_DRVR_VERSION 0x200
  338. #define MAX_DRVR_VER_LEN 24
  339. #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A
  340. #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060
  341. #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061
  342. #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062
  343. #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063
  344. #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064
  345. #define DDB_DS_UNASSIGNED 0x00
  346. #define DDB_DS_NO_CONNECTION_ACTIVE 0x01
  347. #define DDB_DS_DISCOVERY 0x02
  348. #define DDB_DS_SESSION_ACTIVE 0x04
  349. #define DDB_DS_SESSION_FAILED 0x06
  350. #define DDB_DS_LOGIN_IN_PROCESS 0x07
  351. #define MBOX_CMD_GET_FW_STATE 0x0069
  352. #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
  353. #define MBOX_CMD_DIAG_TEST 0x0075
  354. #define MBOX_CMD_GET_SYS_INFO 0x0078
  355. #define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */
  356. #define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */
  357. #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087
  358. #define MBOX_CMD_SET_ACB 0x0088
  359. #define MBOX_CMD_GET_ACB 0x0089
  360. #define MBOX_CMD_DISABLE_ACB 0x008A
  361. #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B
  362. #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C
  363. #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D
  364. #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E
  365. #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090
  366. #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091
  367. #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092
  368. #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093
  369. #define MBOX_CMD_SET_PORT_CONFIG 0x0122
  370. #define MBOX_CMD_GET_PORT_CONFIG 0x0123
  371. #define MBOX_CMD_SET_LED_CONFIG 0x0125
  372. #define MBOX_CMD_GET_LED_CONFIG 0x0126
  373. #define MBOX_CMD_MINIDUMP 0x0129
  374. /* Port Config */
  375. #define ENABLE_INTERNAL_LOOPBACK 0x04
  376. #define ENABLE_EXTERNAL_LOOPBACK 0x08
  377. #define ENABLE_DCBX 0x10
  378. /* Minidump subcommand */
  379. #define MINIDUMP_GET_SIZE_SUBCOMMAND 0x00
  380. #define MINIDUMP_GET_TMPLT_SUBCOMMAND 0x01
  381. /* Mailbox 1 */
  382. #define FW_STATE_READY 0x0000
  383. #define FW_STATE_CONFIG_WAIT 0x0001
  384. #define FW_STATE_WAIT_AUTOCONNECT 0x0002
  385. #define FW_STATE_ERROR 0x0004
  386. #define FW_STATE_CONFIGURING_IP 0x0008
  387. /* Mailbox 3 */
  388. #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001
  389. #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002
  390. #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004
  391. #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008
  392. #define FW_ADDSTATE_LINK_UP 0x0010
  393. #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020
  394. #define FW_ADDSTATE_LINK_SPEED_10MBPS 0x0100
  395. #define FW_ADDSTATE_LINK_SPEED_100MBPS 0x0200
  396. #define FW_ADDSTATE_LINK_SPEED_1GBPS 0x0400
  397. #define FW_ADDSTATE_LINK_SPEED_10GBPS 0x0800
  398. #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B
  399. #define IPV6_DEFAULT_DDB_ENTRY 0x0001
  400. #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074
  401. #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */
  402. #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077
  403. #define MBOX_CMD_IDC_ACK 0x0101
  404. #define MBOX_CMD_IDC_TIME_EXTEND 0x0102
  405. #define MBOX_CMD_PORT_RESET 0x0120
  406. #define MBOX_CMD_SET_PORT_CONFIG 0x0122
  407. /* Mailbox status definitions */
  408. #define MBOX_COMPLETION_STATUS 4
  409. #define MBOX_STS_BUSY 0x0007
  410. #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000
  411. #define MBOX_STS_COMMAND_COMPLETE 0x4000
  412. #define MBOX_STS_COMMAND_ERROR 0x4005
  413. #define MBOX_ASYNC_EVENT_STATUS 8
  414. #define MBOX_ASTS_SYSTEM_ERROR 0x8002
  415. #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
  416. #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
  417. #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005
  418. #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006
  419. #define MBOX_ASTS_LINK_UP 0x8010
  420. #define MBOX_ASTS_LINK_DOWN 0x8011
  421. #define MBOX_ASTS_DATABASE_CHANGED 0x8014
  422. #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015
  423. #define MBOX_ASTS_SELF_TEST_FAILED 0x8016
  424. #define MBOX_ASTS_LOGIN_FAILED 0x8017
  425. #define MBOX_ASTS_DNS 0x8018
  426. #define MBOX_ASTS_HEARTBEAT 0x8019
  427. #define MBOX_ASTS_NVRAM_INVALID 0x801A
  428. #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B
  429. #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C
  430. #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D
  431. #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F
  432. #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
  433. #define MBOX_ASTS_DUPLICATE_IP 0x8025
  434. #define MBOX_ASTS_ARP_COMPLETE 0x8026
  435. #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
  436. #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028
  437. #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029
  438. #define MBOX_ASTS_IPV6_DEFAULT_ROUTER_CHANGED 0x802A
  439. #define MBOX_ASTS_IPV6_LINK_MTU_CHANGE 0x802B
  440. #define MBOX_ASTS_IPV6_AUTO_PREFIX_IGNORED 0x802C
  441. #define MBOX_ASTS_IPV6_ND_LOCAL_PREFIX_IGNORED 0x802D
  442. #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E
  443. #define MBOX_ASTS_INITIALIZATION_FAILED 0x8031
  444. #define MBOX_ASTS_SYSTEM_WARNING_EVENT 0x8036
  445. #define MBOX_ASTS_IDC_COMPLETE 0x8100
  446. #define MBOX_ASTS_IDC_REQUEST_NOTIFICATION 0x8101
  447. #define MBOX_ASTS_IDC_TIME_EXTEND_NOTIFICATION 0x8102
  448. #define MBOX_ASTS_DCBX_CONF_CHANGE 0x8110
  449. #define MBOX_ASTS_TXSCVR_INSERTED 0x8130
  450. #define MBOX_ASTS_TXSCVR_REMOVED 0x8131
  451. #define ISNS_EVENT_DATA_RECEIVED 0x0000
  452. #define ISNS_EVENT_CONNECTION_OPENED 0x0001
  453. #define ISNS_EVENT_CONNECTION_FAILED 0x0002
  454. #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022
  455. #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
  456. /* ACB Configuration Defines */
  457. #define ACB_CONFIG_DISABLE 0x00
  458. #define ACB_CONFIG_SET 0x01
  459. /* ACB/IP Address State Defines */
  460. #define IP_ADDRSTATE_UNCONFIGURED 0
  461. #define IP_ADDRSTATE_INVALID 1
  462. #define IP_ADDRSTATE_ACQUIRING 2
  463. #define IP_ADDRSTATE_TENTATIVE 3
  464. #define IP_ADDRSTATE_DEPRICATED 4
  465. #define IP_ADDRSTATE_PREFERRED 5
  466. #define IP_ADDRSTATE_DISABLING 6
  467. /* FLASH offsets */
  468. #define FLASH_SEGMENT_IFCB 0x04000000
  469. #define FLASH_OPT_RMW_HOLD 0
  470. #define FLASH_OPT_RMW_INIT 1
  471. #define FLASH_OPT_COMMIT 2
  472. #define FLASH_OPT_RMW_COMMIT 3
  473. /* generic defines to enable/disable params */
  474. #define QL4_PARAM_DISABLE 0
  475. #define QL4_PARAM_ENABLE 1
  476. /*************************************************************************/
  477. /* Host Adapter Initialization Control Block (from host) */
  478. struct addr_ctrl_blk {
  479. uint8_t version; /* 00 */
  480. #define IFCB_VER_MIN 0x01
  481. #define IFCB_VER_MAX 0x02
  482. uint8_t control; /* 01 */
  483. #define CTRLOPT_NEW_CONN_DISABLE 0x0002
  484. uint16_t fw_options; /* 02-03 */
  485. #define FWOPT_HEARTBEAT_ENABLE 0x1000
  486. #define FWOPT_SESSION_MODE 0x0040
  487. #define FWOPT_INITIATOR_MODE 0x0020
  488. #define FWOPT_TARGET_MODE 0x0010
  489. #define FWOPT_ENABLE_CRBDB 0x8000
  490. uint16_t exec_throttle; /* 04-05 */
  491. uint8_t zio_count; /* 06 */
  492. uint8_t res0; /* 07 */
  493. uint16_t eth_mtu_size; /* 08-09 */
  494. uint16_t add_fw_options; /* 0A-0B */
  495. #define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400
  496. #define ADFWOPT_AUTOCONN_DISABLE 0x0002
  497. uint8_t hb_interval; /* 0C */
  498. uint8_t inst_num; /* 0D */
  499. uint16_t res1; /* 0E-0F */
  500. uint16_t rqq_consumer_idx; /* 10-11 */
  501. uint16_t compq_producer_idx; /* 12-13 */
  502. uint16_t rqq_len; /* 14-15 */
  503. uint16_t compq_len; /* 16-17 */
  504. uint32_t rqq_addr_lo; /* 18-1B */
  505. uint32_t rqq_addr_hi; /* 1C-1F */
  506. uint32_t compq_addr_lo; /* 20-23 */
  507. uint32_t compq_addr_hi; /* 24-27 */
  508. uint32_t shdwreg_addr_lo; /* 28-2B */
  509. uint32_t shdwreg_addr_hi; /* 2C-2F */
  510. uint16_t iscsi_opts; /* 30-31 */
  511. #define ISCSIOPTS_HEADER_DIGEST_EN 0x2000
  512. #define ISCSIOPTS_DATA_DIGEST_EN 0x1000
  513. #define ISCSIOPTS_IMMEDIATE_DATA_EN 0x0800
  514. #define ISCSIOPTS_INITIAL_R2T_EN 0x0400
  515. #define ISCSIOPTS_DATA_SEQ_INORDER_EN 0x0200
  516. #define ISCSIOPTS_DATA_PDU_INORDER_EN 0x0100
  517. #define ISCSIOPTS_CHAP_AUTH_EN 0x0080
  518. #define ISCSIOPTS_SNACK_EN 0x0040
  519. #define ISCSIOPTS_DISCOVERY_LOGOUT_EN 0x0020
  520. #define ISCSIOPTS_BIDI_CHAP_EN 0x0010
  521. #define ISCSIOPTS_DISCOVERY_AUTH_EN 0x0008
  522. #define ISCSIOPTS_STRICT_LOGIN_COMP_EN 0x0004
  523. #define ISCSIOPTS_ERL 0x0003
  524. uint16_t ipv4_tcp_opts; /* 32-33 */
  525. #define TCPOPT_DELAYED_ACK_DISABLE 0x8000
  526. #define TCPOPT_DHCP_ENABLE 0x0200
  527. #define TCPOPT_DNS_SERVER_IP_EN 0x0100
  528. #define TCPOPT_SLP_DA_INFO_EN 0x0080
  529. #define TCPOPT_NAGLE_ALGO_DISABLE 0x0020
  530. #define TCPOPT_WINDOW_SCALE_DISABLE 0x0010
  531. #define TCPOPT_TIMER_SCALE 0x000E
  532. #define TCPOPT_TIMESTAMP_ENABLE 0x0001
  533. uint16_t ipv4_ip_opts; /* 34-35 */
  534. #define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000
  535. #define IPOPT_IPV4_TOS_EN 0x4000
  536. #define IPOPT_VLAN_TAGGING_ENABLE 0x2000
  537. #define IPOPT_GRAT_ARP_EN 0x1000
  538. #define IPOPT_ALT_CID_EN 0x0800
  539. #define IPOPT_REQ_VID_EN 0x0400
  540. #define IPOPT_USE_VID_EN 0x0200
  541. #define IPOPT_LEARN_IQN_EN 0x0100
  542. #define IPOPT_FRAGMENTATION_DISABLE 0x0010
  543. #define IPOPT_IN_FORWARD_EN 0x0008
  544. #define IPOPT_ARP_REDIRECT_EN 0x0004
  545. uint16_t iscsi_max_pdu_size; /* 36-37 */
  546. uint8_t ipv4_tos; /* 38 */
  547. uint8_t ipv4_ttl; /* 39 */
  548. uint8_t acb_version; /* 3A */
  549. #define ACB_NOT_SUPPORTED 0x00
  550. #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2
  551. Features */
  552. uint8_t res2; /* 3B */
  553. uint16_t def_timeout; /* 3C-3D */
  554. uint16_t iscsi_fburst_len; /* 3E-3F */
  555. uint16_t iscsi_def_time2wait; /* 40-41 */
  556. uint16_t iscsi_def_time2retain; /* 42-43 */
  557. uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
  558. uint16_t conn_ka_timeout; /* 46-47 */
  559. uint16_t ipv4_port; /* 48-49 */
  560. uint16_t iscsi_max_burst_len; /* 4A-4B */
  561. uint32_t res5; /* 4C-4F */
  562. uint8_t ipv4_addr[4]; /* 50-53 */
  563. uint16_t ipv4_vlan_tag; /* 54-55 */
  564. uint8_t ipv4_addr_state; /* 56 */
  565. uint8_t ipv4_cacheid; /* 57 */
  566. uint8_t res6[8]; /* 58-5F */
  567. uint8_t ipv4_subnet[4]; /* 60-63 */
  568. uint8_t res7[12]; /* 64-6F */
  569. uint8_t ipv4_gw_addr[4]; /* 70-73 */
  570. uint8_t res8[0xc]; /* 74-7F */
  571. uint8_t pri_dns_srvr_ip[4];/* 80-83 */
  572. uint8_t sec_dns_srvr_ip[4];/* 84-87 */
  573. uint16_t min_eph_port; /* 88-89 */
  574. uint16_t max_eph_port; /* 8A-8B */
  575. uint8_t res9[4]; /* 8C-8F */
  576. uint8_t iscsi_alias[32];/* 90-AF */
  577. uint8_t res9_1[0x16]; /* B0-C5 */
  578. uint16_t tgt_portal_grp;/* C6-C7 */
  579. uint8_t abort_timer; /* C8 */
  580. uint8_t ipv4_tcp_wsf; /* C9 */
  581. uint8_t res10[6]; /* CA-CF */
  582. uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */
  583. uint8_t ipv4_dhcp_vid_len; /* D4 */
  584. uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
  585. uint8_t res11[20]; /* E0-F3 */
  586. uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
  587. uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
  588. uint8_t iscsi_name[224]; /* 100-1DF */
  589. uint8_t res12[32]; /* 1E0-1FF */
  590. uint32_t cookie; /* 200-203 */
  591. uint16_t ipv6_port; /* 204-205 */
  592. uint16_t ipv6_opts; /* 206-207 */
  593. #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000
  594. #define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000
  595. #define IPV6_OPT_GRAT_NEIGHBOR_ADV_EN 0x1000
  596. #define IPV6_OPT_REDIRECT_EN 0x0004
  597. uint16_t ipv6_addtl_opts; /* 208-209 */
  598. #define IPV6_ADDOPT_IGNORE_ICMP_ECHO_REQ 0x0040
  599. #define IPV6_ADDOPT_MLD_EN 0x0004
  600. #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB
  601. Only */
  602. #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001
  603. uint16_t ipv6_tcp_opts; /* 20A-20B */
  604. #define IPV6_TCPOPT_DELAYED_ACK_DISABLE 0x8000
  605. #define IPV6_TCPOPT_NAGLE_ALGO_DISABLE 0x0020
  606. #define IPV6_TCPOPT_WINDOW_SCALE_DISABLE 0x0010
  607. #define IPV6_TCPOPT_TIMER_SCALE 0x000E
  608. #define IPV6_TCPOPT_TIMESTAMP_EN 0x0001
  609. uint8_t ipv6_tcp_wsf; /* 20C */
  610. uint16_t ipv6_flow_lbl; /* 20D-20F */
  611. uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
  612. uint16_t ipv6_vlan_tag; /* 220-221 */
  613. uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
  614. uint8_t ipv6_addr0_state; /* 223 */
  615. uint8_t ipv6_addr1_state; /* 224 */
  616. uint8_t ipv6_dflt_rtr_state; /* 225 */
  617. #define IPV6_RTRSTATE_UNKNOWN 0
  618. #define IPV6_RTRSTATE_MANUAL 1
  619. #define IPV6_RTRSTATE_ADVERTISED 3
  620. #define IPV6_RTRSTATE_STALE 4
  621. uint8_t ipv6_traffic_class; /* 226 */
  622. uint8_t ipv6_hop_limit; /* 227 */
  623. uint8_t ipv6_if_id[8]; /* 228-22F */
  624. uint8_t ipv6_addr0[16]; /* 230-23F */
  625. uint8_t ipv6_addr1[16]; /* 240-24F */
  626. uint32_t ipv6_nd_reach_time; /* 250-253 */
  627. uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
  628. uint32_t ipv6_nd_stale_timeout; /* 258-25B */
  629. uint8_t ipv6_dup_addr_detect_count; /* 25C */
  630. uint8_t ipv6_cache_id; /* 25D */
  631. uint8_t res13[18]; /* 25E-26F */
  632. uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
  633. uint8_t res14[140]; /* 274-2FF */
  634. };
  635. #define IP_ADDR_COUNT 4 /* Total 4 IP address supported in one interface
  636. * One IPv4, one IPv6 link local and 2 IPv6
  637. */
  638. #define IP_STATE_MASK 0x0F000000
  639. #define IP_STATE_SHIFT 24
  640. struct init_fw_ctrl_blk {
  641. struct addr_ctrl_blk pri;
  642. /* struct addr_ctrl_blk sec;*/
  643. };
  644. #define PRIMARI_ACB 0
  645. #define SECONDARY_ACB 1
  646. struct addr_ctrl_blk_def {
  647. uint8_t reserved1[1]; /* 00 */
  648. uint8_t control; /* 01 */
  649. uint8_t reserved2[11]; /* 02-0C */
  650. uint8_t inst_num; /* 0D */
  651. uint8_t reserved3[34]; /* 0E-2F */
  652. uint16_t iscsi_opts; /* 30-31 */
  653. uint16_t ipv4_tcp_opts; /* 32-33 */
  654. uint16_t ipv4_ip_opts; /* 34-35 */
  655. uint16_t iscsi_max_pdu_size; /* 36-37 */
  656. uint8_t ipv4_tos; /* 38 */
  657. uint8_t ipv4_ttl; /* 39 */
  658. uint8_t reserved4[2]; /* 3A-3B */
  659. uint16_t def_timeout; /* 3C-3D */
  660. uint16_t iscsi_fburst_len; /* 3E-3F */
  661. uint8_t reserved5[4]; /* 40-43 */
  662. uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
  663. uint8_t reserved6[2]; /* 46-47 */
  664. uint16_t ipv4_port; /* 48-49 */
  665. uint16_t iscsi_max_burst_len; /* 4A-4B */
  666. uint8_t reserved7[4]; /* 4C-4F */
  667. uint8_t ipv4_addr[4]; /* 50-53 */
  668. uint16_t ipv4_vlan_tag; /* 54-55 */
  669. uint8_t ipv4_addr_state; /* 56 */
  670. uint8_t ipv4_cacheid; /* 57 */
  671. uint8_t reserved8[8]; /* 58-5F */
  672. uint8_t ipv4_subnet[4]; /* 60-63 */
  673. uint8_t reserved9[12]; /* 64-6F */
  674. uint8_t ipv4_gw_addr[4]; /* 70-73 */
  675. uint8_t reserved10[84]; /* 74-C7 */
  676. uint8_t abort_timer; /* C8 */
  677. uint8_t ipv4_tcp_wsf; /* C9 */
  678. uint8_t reserved11[10]; /* CA-D3 */
  679. uint8_t ipv4_dhcp_vid_len; /* D4 */
  680. uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
  681. uint8_t reserved12[20]; /* E0-F3 */
  682. uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
  683. uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
  684. uint8_t iscsi_name[224]; /* 100-1DF */
  685. uint8_t reserved13[32]; /* 1E0-1FF */
  686. uint32_t cookie; /* 200-203 */
  687. uint16_t ipv6_port; /* 204-205 */
  688. uint16_t ipv6_opts; /* 206-207 */
  689. uint16_t ipv6_addtl_opts; /* 208-209 */
  690. uint16_t ipv6_tcp_opts; /* 20A-20B */
  691. uint8_t ipv6_tcp_wsf; /* 20C */
  692. uint16_t ipv6_flow_lbl; /* 20D-20F */
  693. uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
  694. uint16_t ipv6_vlan_tag; /* 220-221 */
  695. uint8_t ipv6_lnk_lcl_addr_state; /* 222 */
  696. uint8_t ipv6_addr0_state; /* 223 */
  697. uint8_t ipv6_addr1_state; /* 224 */
  698. uint8_t ipv6_dflt_rtr_state; /* 225 */
  699. uint8_t ipv6_traffic_class; /* 226 */
  700. uint8_t ipv6_hop_limit; /* 227 */
  701. uint8_t ipv6_if_id[8]; /* 228-22F */
  702. uint8_t ipv6_addr0[16]; /* 230-23F */
  703. uint8_t ipv6_addr1[16]; /* 240-24F */
  704. uint32_t ipv6_nd_reach_time; /* 250-253 */
  705. uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
  706. uint32_t ipv6_nd_stale_timeout; /* 258-25B */
  707. uint8_t ipv6_dup_addr_detect_count; /* 25C */
  708. uint8_t ipv6_cache_id; /* 25D */
  709. uint8_t reserved14[18]; /* 25E-26F */
  710. uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
  711. uint8_t reserved15[140]; /* 274-2FF */
  712. };
  713. /*************************************************************************/
  714. #define MAX_CHAP_ENTRIES_40XX 128
  715. #define MAX_CHAP_ENTRIES_82XX 1024
  716. #define MAX_RESRV_CHAP_IDX 3
  717. #define FLASH_CHAP_OFFSET 0x06000000
  718. struct ql4_chap_table {
  719. uint16_t link;
  720. uint8_t flags;
  721. uint8_t secret_len;
  722. #define MIN_CHAP_SECRET_LEN 12
  723. #define MAX_CHAP_SECRET_LEN 100
  724. uint8_t secret[MAX_CHAP_SECRET_LEN];
  725. #define MAX_CHAP_NAME_LEN 256
  726. uint8_t name[MAX_CHAP_NAME_LEN];
  727. uint16_t reserved;
  728. #define CHAP_VALID_COOKIE 0x4092
  729. #define CHAP_INVALID_COOKIE 0xFFEE
  730. uint16_t cookie;
  731. };
  732. struct dev_db_entry {
  733. uint16_t options; /* 00-01 */
  734. #define DDB_OPT_DISC_SESSION 0x10
  735. #define DDB_OPT_TARGET 0x02 /* device is a target */
  736. #define DDB_OPT_IPV6_DEVICE 0x100
  737. #define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40
  738. #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */
  739. #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */
  740. #define OPT_IS_FW_ASSIGNED_IPV6 11
  741. #define OPT_IPV6_DEVICE 8
  742. #define OPT_AUTO_SENDTGTS_DISABLE 6
  743. #define OPT_DISC_SESSION 4
  744. #define OPT_ENTRY_STATE 3
  745. uint16_t exec_throttle; /* 02-03 */
  746. uint16_t exec_count; /* 04-05 */
  747. uint16_t res0; /* 06-07 */
  748. uint16_t iscsi_options; /* 08-09 */
  749. #define ISCSIOPT_HEADER_DIGEST_EN 13
  750. #define ISCSIOPT_DATA_DIGEST_EN 12
  751. #define ISCSIOPT_IMMEDIATE_DATA_EN 11
  752. #define ISCSIOPT_INITIAL_R2T_EN 10
  753. #define ISCSIOPT_DATA_SEQ_IN_ORDER 9
  754. #define ISCSIOPT_DATA_PDU_IN_ORDER 8
  755. #define ISCSIOPT_CHAP_AUTH_EN 7
  756. #define ISCSIOPT_SNACK_REQ_EN 6
  757. #define ISCSIOPT_DISCOVERY_LOGOUT_EN 5
  758. #define ISCSIOPT_BIDI_CHAP_EN 4
  759. #define ISCSIOPT_DISCOVERY_AUTH_OPTIONAL 3
  760. #define ISCSIOPT_ERL1 1
  761. #define ISCSIOPT_ERL0 0
  762. uint16_t tcp_options; /* 0A-0B */
  763. #define TCPOPT_TIMESTAMP_STAT 6
  764. #define TCPOPT_NAGLE_DISABLE 5
  765. #define TCPOPT_WSF_DISABLE 4
  766. #define TCPOPT_TIMER_SCALE3 3
  767. #define TCPOPT_TIMER_SCALE2 2
  768. #define TCPOPT_TIMER_SCALE1 1
  769. #define TCPOPT_TIMESTAMP_EN 0
  770. uint16_t ip_options; /* 0C-0D */
  771. #define IPOPT_FRAGMENT_DISABLE 4
  772. uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */
  773. #define BYTE_UNITS 512
  774. uint32_t res1; /* 10-13 */
  775. uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */
  776. uint16_t iscsi_first_burst_len; /* 16-17 */
  777. uint16_t iscsi_def_time2wait; /* 18-19 */
  778. uint16_t iscsi_def_time2retain; /* 1A-1B */
  779. uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */
  780. uint16_t ka_timeout; /* 1E-1F */
  781. uint8_t isid[6]; /* 20-25 big-endian, must be converted
  782. * to little-endian */
  783. uint16_t tsid; /* 26-27 */
  784. uint16_t port; /* 28-29 */
  785. uint16_t iscsi_max_burst_len; /* 2A-2B */
  786. uint16_t def_timeout; /* 2C-2D */
  787. uint16_t res2; /* 2E-2F */
  788. uint8_t ip_addr[0x10]; /* 30-3F */
  789. uint8_t iscsi_alias[0x20]; /* 40-5F */
  790. uint8_t tgt_addr[0x20]; /* 60-7F */
  791. uint16_t mss; /* 80-81 */
  792. uint16_t res3; /* 82-83 */
  793. uint16_t lcl_port; /* 84-85 */
  794. uint8_t ipv4_tos; /* 86 */
  795. uint16_t ipv6_flow_lbl; /* 87-89 */
  796. uint8_t res4[0x36]; /* 8A-BF */
  797. uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a
  798. * pointer to a string so we
  799. * don't have to reserve so
  800. * much RAM */
  801. uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
  802. uint8_t res5[0x10]; /* 1B0-1BF */
  803. #define DDB_NO_LINK 0xFFFF
  804. #define DDB_ISNS 0xFFFD
  805. uint16_t ddb_link; /* 1C0-1C1 */
  806. uint16_t chap_tbl_idx; /* 1C2-1C3 */
  807. uint16_t tgt_portal_grp; /* 1C4-1C5 */
  808. uint8_t tcp_xmt_wsf; /* 1C6 */
  809. uint8_t tcp_rcv_wsf; /* 1C7 */
  810. uint32_t stat_sn; /* 1C8-1CB */
  811. uint32_t exp_stat_sn; /* 1CC-1CF */
  812. uint8_t res6[0x2b]; /* 1D0-1FB */
  813. #define DDB_VALID_COOKIE 0x9034
  814. uint16_t cookie; /* 1FC-1FD */
  815. uint16_t len; /* 1FE-1FF */
  816. };
  817. /*************************************************************************/
  818. /* Flash definitions */
  819. #define FLASH_OFFSET_SYS_INFO 0x02000000
  820. #define FLASH_DEFAULTBLOCKSIZE 0x20000
  821. #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
  822. * for EOF
  823. * signature */
  824. #define FLASH_RAW_ACCESS_ADDR 0x8e000000
  825. #define BOOT_PARAM_OFFSET_PORT0 0x3b0
  826. #define BOOT_PARAM_OFFSET_PORT1 0x7b0
  827. #define FLASH_OFFSET_DB_INFO 0x05000000
  828. #define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff)
  829. struct sys_info_phys_addr {
  830. uint8_t address[6]; /* 00-05 */
  831. uint8_t filler[2]; /* 06-07 */
  832. };
  833. struct flash_sys_info {
  834. uint32_t cookie; /* 00-03 */
  835. uint32_t physAddrCount; /* 04-07 */
  836. struct sys_info_phys_addr physAddr[4]; /* 08-27 */
  837. uint8_t vendorId[128]; /* 28-A7 */
  838. uint8_t productId[128]; /* A8-127 */
  839. uint32_t serialNumber; /* 128-12B */
  840. /* PCI Configuration values */
  841. uint32_t pciDeviceVendor; /* 12C-12F */
  842. uint32_t pciDeviceId; /* 130-133 */
  843. uint32_t pciSubsysVendor; /* 134-137 */
  844. uint32_t pciSubsysId; /* 138-13B */
  845. /* This validates version 1. */
  846. uint32_t crumbs; /* 13C-13F */
  847. uint32_t enterpriseNumber; /* 140-143 */
  848. uint32_t mtu; /* 144-147 */
  849. uint32_t reserved0; /* 148-14b */
  850. uint32_t crumbs2; /* 14c-14f */
  851. uint8_t acSerialNumber[16]; /* 150-15f */
  852. uint32_t crumbs3; /* 160-16f */
  853. /* Leave this last in the struct so it is declared invalid if
  854. * any new items are added.
  855. */
  856. uint32_t reserved1[39]; /* 170-1ff */
  857. }; /* 200 */
  858. struct mbx_sys_info {
  859. uint8_t board_id_str[16]; /* 0-f Keep board ID string first */
  860. /* in this structure for GUI. */
  861. uint16_t board_id; /* 10-11 board ID code */
  862. uint16_t phys_port_cnt; /* 12-13 number of physical network ports */
  863. uint16_t port_num; /* 14-15 network port for this PCI function */
  864. /* (port 0 is first port) */
  865. uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */
  866. uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */
  867. uint32_t pci_func; /* 20-23 this PCI function */
  868. unsigned char serial_number[16]; /* 24-33 serial number string */
  869. uint8_t reserved[12]; /* 34-3f */
  870. };
  871. struct about_fw_info {
  872. uint16_t fw_major; /* 00 - 01 */
  873. uint16_t fw_minor; /* 02 - 03 */
  874. uint16_t fw_patch; /* 04 - 05 */
  875. uint16_t fw_build; /* 06 - 07 */
  876. uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */
  877. uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */
  878. uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */
  879. uint16_t fw_load_source; /* 38 - 39 */
  880. /* 1 = Flash Primary,
  881. 2 = Flash Secondary,
  882. 3 = Host Download
  883. */
  884. uint8_t reserved1[6]; /* 3A - 3F */
  885. uint16_t iscsi_major; /* 40 - 41 */
  886. uint16_t iscsi_minor; /* 42 - 43 */
  887. uint16_t bootload_major; /* 44 - 45 */
  888. uint16_t bootload_minor; /* 46 - 47 */
  889. uint16_t bootload_patch; /* 48 - 49 */
  890. uint16_t bootload_build; /* 4A - 4B */
  891. uint8_t extended_timestamp[180];/* 4C - FF */
  892. };
  893. struct crash_record {
  894. uint16_t fw_major_version; /* 00 - 01 */
  895. uint16_t fw_minor_version; /* 02 - 03 */
  896. uint16_t fw_patch_version; /* 04 - 05 */
  897. uint16_t fw_build_version; /* 06 - 07 */
  898. uint8_t build_date[16]; /* 08 - 17 */
  899. uint8_t build_time[16]; /* 18 - 27 */
  900. uint8_t build_user[16]; /* 28 - 37 */
  901. uint8_t card_serial_num[16]; /* 38 - 47 */
  902. uint32_t time_of_crash_in_secs; /* 48 - 4B */
  903. uint32_t time_of_crash_in_ms; /* 4C - 4F */
  904. uint16_t out_RISC_sd_num_frames; /* 50 - 51 */
  905. uint16_t OAP_sd_num_words; /* 52 - 53 */
  906. uint16_t IAP_sd_num_frames; /* 54 - 55 */
  907. uint16_t in_RISC_sd_num_words; /* 56 - 57 */
  908. uint8_t reserved1[28]; /* 58 - 7F */
  909. uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
  910. uint8_t in_RISC_reg_dump[256]; /*180 -27F */
  911. uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */
  912. };
  913. struct conn_event_log_entry {
  914. #define MAX_CONN_EVENT_LOG_ENTRIES 100
  915. uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
  916. uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */
  917. uint16_t device_index; /* 08 - 09 */
  918. uint16_t fw_conn_state; /* 0A - 0B */
  919. uint8_t event_type; /* 0C - 0C */
  920. uint8_t error_code; /* 0D - 0D */
  921. uint16_t error_code_detail; /* 0E - 0F */
  922. uint8_t num_consecutive_events; /* 10 - 10 */
  923. uint8_t rsvd[3]; /* 11 - 13 */
  924. };
  925. /*************************************************************************
  926. *
  927. * IOCB Commands Structures and Definitions
  928. *
  929. *************************************************************************/
  930. #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */
  931. #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */
  932. #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */
  933. /* IOCB header structure */
  934. struct qla4_header {
  935. uint8_t entryType;
  936. #define ET_STATUS 0x03
  937. #define ET_MARKER 0x04
  938. #define ET_CONT_T1 0x0A
  939. #define ET_STATUS_CONTINUATION 0x10
  940. #define ET_CMND_T3 0x19
  941. #define ET_PASSTHRU0 0x3A
  942. #define ET_PASSTHRU_STATUS 0x3C
  943. #define ET_MBOX_CMD 0x38
  944. #define ET_MBOX_STATUS 0x39
  945. uint8_t entryStatus;
  946. uint8_t systemDefined;
  947. #define SD_ISCSI_PDU 0x01
  948. uint8_t entryCount;
  949. /* SyetemDefined definition */
  950. };
  951. /* Generic queue entry structure*/
  952. struct queue_entry {
  953. uint8_t data[60];
  954. uint32_t signature;
  955. };
  956. /* 64 bit addressing segment counts*/
  957. #define COMMAND_SEG_A64 1
  958. #define CONTINUE_SEG_A64 5
  959. /* 64 bit addressing segment definition*/
  960. struct data_seg_a64 {
  961. struct {
  962. uint32_t addrLow;
  963. uint32_t addrHigh;
  964. } base;
  965. uint32_t count;
  966. };
  967. /* Command Type 3 entry structure*/
  968. struct command_t3_entry {
  969. struct qla4_header hdr; /* 00-03 */
  970. uint32_t handle; /* 04-07 */
  971. uint16_t target; /* 08-09 */
  972. uint16_t connection_id; /* 0A-0B */
  973. uint8_t control_flags; /* 0C */
  974. /* data direction (bits 5-6) */
  975. #define CF_WRITE 0x20
  976. #define CF_READ 0x40
  977. #define CF_NO_DATA 0x00
  978. /* task attributes (bits 2-0) */
  979. #define CF_HEAD_TAG 0x03
  980. #define CF_ORDERED_TAG 0x02
  981. #define CF_SIMPLE_TAG 0x01
  982. /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
  983. * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
  984. * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
  985. * PROPERLY.
  986. */
  987. uint8_t state_flags; /* 0D */
  988. uint8_t cmdRefNum; /* 0E */
  989. uint8_t reserved1; /* 0F */
  990. uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */
  991. struct scsi_lun lun; /* FCP LUN (BE). */
  992. uint32_t cmdSeqNum; /* 28-2B */
  993. uint16_t timeout; /* 2C-2D */
  994. uint16_t dataSegCnt; /* 2E-2F */
  995. uint32_t ttlByteCnt; /* 30-33 */
  996. struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */
  997. };
  998. /* Continuation Type 1 entry structure*/
  999. struct continuation_t1_entry {
  1000. struct qla4_header hdr;
  1001. struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
  1002. };
  1003. /* Parameterize for 64 or 32 bits */
  1004. #define COMMAND_SEG COMMAND_SEG_A64
  1005. #define CONTINUE_SEG CONTINUE_SEG_A64
  1006. #define ET_COMMAND ET_CMND_T3
  1007. #define ET_CONTINUE ET_CONT_T1
  1008. /* Marker entry structure*/
  1009. struct qla4_marker_entry {
  1010. struct qla4_header hdr; /* 00-03 */
  1011. uint32_t system_defined; /* 04-07 */
  1012. uint16_t target; /* 08-09 */
  1013. uint16_t modifier; /* 0A-0B */
  1014. #define MM_LUN_RESET 0
  1015. #define MM_TGT_WARM_RESET 1
  1016. uint16_t flags; /* 0C-0D */
  1017. uint16_t reserved1; /* 0E-0F */
  1018. struct scsi_lun lun; /* FCP LUN (BE). */
  1019. uint64_t reserved2; /* 18-1F */
  1020. uint64_t reserved3; /* 20-27 */
  1021. uint64_t reserved4; /* 28-2F */
  1022. uint64_t reserved5; /* 30-37 */
  1023. uint64_t reserved6; /* 38-3F */
  1024. };
  1025. /* Status entry structure*/
  1026. struct status_entry {
  1027. struct qla4_header hdr; /* 00-03 */
  1028. uint32_t handle; /* 04-07 */
  1029. uint8_t scsiStatus; /* 08 */
  1030. #define SCSI_CHECK_CONDITION 0x02
  1031. uint8_t iscsiFlags; /* 09 */
  1032. #define ISCSI_FLAG_RESIDUAL_UNDER 0x02
  1033. #define ISCSI_FLAG_RESIDUAL_OVER 0x04
  1034. uint8_t iscsiResponse; /* 0A */
  1035. uint8_t completionStatus; /* 0B */
  1036. #define SCS_COMPLETE 0x00
  1037. #define SCS_INCOMPLETE 0x01
  1038. #define SCS_RESET_OCCURRED 0x04
  1039. #define SCS_ABORTED 0x05
  1040. #define SCS_TIMEOUT 0x06
  1041. #define SCS_DATA_OVERRUN 0x07
  1042. #define SCS_DATA_UNDERRUN 0x15
  1043. #define SCS_QUEUE_FULL 0x1C
  1044. #define SCS_DEVICE_UNAVAILABLE 0x28
  1045. #define SCS_DEVICE_LOGGED_OUT 0x29
  1046. uint8_t reserved1; /* 0C */
  1047. /* state_flags MUST be at the same location as state_flags in
  1048. * the Command_T3/4_Entry */
  1049. uint8_t state_flags; /* 0D */
  1050. uint16_t senseDataByteCnt; /* 0E-0F */
  1051. uint32_t residualByteCnt; /* 10-13 */
  1052. uint32_t bidiResidualByteCnt; /* 14-17 */
  1053. uint32_t expSeqNum; /* 18-1B */
  1054. uint32_t maxCmdSeqNum; /* 1C-1F */
  1055. uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */
  1056. };
  1057. /* Status Continuation entry */
  1058. struct status_cont_entry {
  1059. struct qla4_header hdr; /* 00-03 */
  1060. uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
  1061. };
  1062. struct passthru0 {
  1063. struct qla4_header hdr; /* 00-03 */
  1064. uint32_t handle; /* 04-07 */
  1065. uint16_t target; /* 08-09 */
  1066. uint16_t connection_id; /* 0A-0B */
  1067. #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000)
  1068. uint16_t control_flags; /* 0C-0D */
  1069. #define PT_FLAG_ETHERNET_FRAME 0x8000
  1070. #define PT_FLAG_ISNS_PDU 0x8000
  1071. #define PT_FLAG_SEND_BUFFER 0x0200
  1072. #define PT_FLAG_WAIT_4_RESPONSE 0x0100
  1073. #define PT_FLAG_ISCSI_PDU 0x1000
  1074. uint16_t timeout; /* 0E-0F */
  1075. #define PT_DEFAULT_TIMEOUT 30 /* seconds */
  1076. struct data_seg_a64 out_dsd; /* 10-1B */
  1077. uint32_t res1; /* 1C-1F */
  1078. struct data_seg_a64 in_dsd; /* 20-2B */
  1079. uint8_t res2[20]; /* 2C-3F */
  1080. };
  1081. struct passthru_status {
  1082. struct qla4_header hdr; /* 00-03 */
  1083. uint32_t handle; /* 04-07 */
  1084. uint16_t target; /* 08-09 */
  1085. uint16_t connectionID; /* 0A-0B */
  1086. uint8_t completionStatus; /* 0C */
  1087. #define PASSTHRU_STATUS_COMPLETE 0x01
  1088. uint8_t residualFlags; /* 0D */
  1089. uint16_t timeout; /* 0E-0F */
  1090. uint16_t portNumber; /* 10-11 */
  1091. uint8_t res1[10]; /* 12-1B */
  1092. uint32_t outResidual; /* 1C-1F */
  1093. uint8_t res2[12]; /* 20-2B */
  1094. uint32_t inResidual; /* 2C-2F */
  1095. uint8_t res4[16]; /* 30-3F */
  1096. };
  1097. struct mbox_cmd_iocb {
  1098. struct qla4_header hdr; /* 00-03 */
  1099. uint32_t handle; /* 04-07 */
  1100. uint32_t in_mbox[8]; /* 08-25 */
  1101. uint32_t res1[6]; /* 26-3F */
  1102. };
  1103. struct mbox_status_iocb {
  1104. struct qla4_header hdr; /* 00-03 */
  1105. uint32_t handle; /* 04-07 */
  1106. uint32_t out_mbox[8]; /* 08-25 */
  1107. uint32_t res1[6]; /* 26-3F */
  1108. };
  1109. /*
  1110. * ISP queue - response queue entry definition.
  1111. */
  1112. struct response {
  1113. uint8_t data[60];
  1114. uint32_t signature;
  1115. #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
  1116. };
  1117. struct ql_iscsi_stats {
  1118. uint64_t mac_tx_frames; /* 0000–0007 */
  1119. uint64_t mac_tx_bytes; /* 0008–000F */
  1120. uint64_t mac_tx_multicast_frames; /* 0010–0017 */
  1121. uint64_t mac_tx_broadcast_frames; /* 0018–001F */
  1122. uint64_t mac_tx_pause_frames; /* 0020–0027 */
  1123. uint64_t mac_tx_control_frames; /* 0028–002F */
  1124. uint64_t mac_tx_deferral; /* 0030–0037 */
  1125. uint64_t mac_tx_excess_deferral; /* 0038–003F */
  1126. uint64_t mac_tx_late_collision; /* 0040–0047 */
  1127. uint64_t mac_tx_abort; /* 0048–004F */
  1128. uint64_t mac_tx_single_collision; /* 0050–0057 */
  1129. uint64_t mac_tx_multiple_collision; /* 0058–005F */
  1130. uint64_t mac_tx_collision; /* 0060–0067 */
  1131. uint64_t mac_tx_frames_dropped; /* 0068–006F */
  1132. uint64_t mac_tx_jumbo_frames; /* 0070–0077 */
  1133. uint64_t mac_rx_frames; /* 0078–007F */
  1134. uint64_t mac_rx_bytes; /* 0080–0087 */
  1135. uint64_t mac_rx_unknown_control_frames; /* 0088–008F */
  1136. uint64_t mac_rx_pause_frames; /* 0090–0097 */
  1137. uint64_t mac_rx_control_frames; /* 0098–009F */
  1138. uint64_t mac_rx_dribble; /* 00A0–00A7 */
  1139. uint64_t mac_rx_frame_length_error; /* 00A8–00AF */
  1140. uint64_t mac_rx_jabber; /* 00B0–00B7 */
  1141. uint64_t mac_rx_carrier_sense_error; /* 00B8–00BF */
  1142. uint64_t mac_rx_frame_discarded; /* 00C0–00C7 */
  1143. uint64_t mac_rx_frames_dropped; /* 00C8–00CF */
  1144. uint64_t mac_crc_error; /* 00D0–00D7 */
  1145. uint64_t mac_encoding_error; /* 00D8–00DF */
  1146. uint64_t mac_rx_length_error_large; /* 00E0–00E7 */
  1147. uint64_t mac_rx_length_error_small; /* 00E8–00EF */
  1148. uint64_t mac_rx_multicast_frames; /* 00F0–00F7 */
  1149. uint64_t mac_rx_broadcast_frames; /* 00F8–00FF */
  1150. uint64_t ip_tx_packets; /* 0100–0107 */
  1151. uint64_t ip_tx_bytes; /* 0108–010F */
  1152. uint64_t ip_tx_fragments; /* 0110–0117 */
  1153. uint64_t ip_rx_packets; /* 0118–011F */
  1154. uint64_t ip_rx_bytes; /* 0120–0127 */
  1155. uint64_t ip_rx_fragments; /* 0128–012F */
  1156. uint64_t ip_datagram_reassembly; /* 0130–0137 */
  1157. uint64_t ip_invalid_address_error; /* 0138–013F */
  1158. uint64_t ip_error_packets; /* 0140–0147 */
  1159. uint64_t ip_fragrx_overlap; /* 0148–014F */
  1160. uint64_t ip_fragrx_outoforder; /* 0150–0157 */
  1161. uint64_t ip_datagram_reassembly_timeout; /* 0158–015F */
  1162. uint64_t ipv6_tx_packets; /* 0160–0167 */
  1163. uint64_t ipv6_tx_bytes; /* 0168–016F */
  1164. uint64_t ipv6_tx_fragments; /* 0170–0177 */
  1165. uint64_t ipv6_rx_packets; /* 0178–017F */
  1166. uint64_t ipv6_rx_bytes; /* 0180–0187 */
  1167. uint64_t ipv6_rx_fragments; /* 0188–018F */
  1168. uint64_t ipv6_datagram_reassembly; /* 0190–0197 */
  1169. uint64_t ipv6_invalid_address_error; /* 0198–019F */
  1170. uint64_t ipv6_error_packets; /* 01A0–01A7 */
  1171. uint64_t ipv6_fragrx_overlap; /* 01A8–01AF */
  1172. uint64_t ipv6_fragrx_outoforder; /* 01B0–01B7 */
  1173. uint64_t ipv6_datagram_reassembly_timeout; /* 01B8–01BF */
  1174. uint64_t tcp_tx_segments; /* 01C0–01C7 */
  1175. uint64_t tcp_tx_bytes; /* 01C8–01CF */
  1176. uint64_t tcp_rx_segments; /* 01D0–01D7 */
  1177. uint64_t tcp_rx_byte; /* 01D8–01DF */
  1178. uint64_t tcp_duplicate_ack_retx; /* 01E0–01E7 */
  1179. uint64_t tcp_retx_timer_expired; /* 01E8–01EF */
  1180. uint64_t tcp_rx_duplicate_ack; /* 01F0–01F7 */
  1181. uint64_t tcp_rx_pure_ackr; /* 01F8–01FF */
  1182. uint64_t tcp_tx_delayed_ack; /* 0200–0207 */
  1183. uint64_t tcp_tx_pure_ack; /* 0208–020F */
  1184. uint64_t tcp_rx_segment_error; /* 0210–0217 */
  1185. uint64_t tcp_rx_segment_outoforder; /* 0218–021F */
  1186. uint64_t tcp_rx_window_probe; /* 0220–0227 */
  1187. uint64_t tcp_rx_window_update; /* 0228–022F */
  1188. uint64_t tcp_tx_window_probe_persist; /* 0230–0237 */
  1189. uint64_t ecc_error_correction; /* 0238–023F */
  1190. uint64_t iscsi_pdu_tx; /* 0240-0247 */
  1191. uint64_t iscsi_data_bytes_tx; /* 0248-024F */
  1192. uint64_t iscsi_pdu_rx; /* 0250-0257 */
  1193. uint64_t iscsi_data_bytes_rx; /* 0258-025F */
  1194. uint64_t iscsi_io_completed; /* 0260-0267 */
  1195. uint64_t iscsi_unexpected_io_rx; /* 0268-026F */
  1196. uint64_t iscsi_format_error; /* 0270-0277 */
  1197. uint64_t iscsi_hdr_digest_error; /* 0278-027F */
  1198. uint64_t iscsi_data_digest_error; /* 0280-0287 */
  1199. uint64_t iscsi_sequence_error; /* 0288-028F */
  1200. uint32_t tx_cmd_pdu; /* 0290-0293 */
  1201. uint32_t tx_resp_pdu; /* 0294-0297 */
  1202. uint32_t rx_cmd_pdu; /* 0298-029B */
  1203. uint32_t rx_resp_pdu; /* 029C-029F */
  1204. uint64_t tx_data_octets; /* 02A0-02A7 */
  1205. uint64_t rx_data_octets; /* 02A8-02AF */
  1206. uint32_t hdr_digest_err; /* 02B0–02B3 */
  1207. uint32_t data_digest_err; /* 02B4–02B7 */
  1208. uint32_t conn_timeout_err; /* 02B8–02BB */
  1209. uint32_t framing_err; /* 02BC–02BF */
  1210. uint32_t tx_nopout_pdus; /* 02C0–02C3 */
  1211. uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */
  1212. uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */
  1213. uint32_t tx_login_cmd_pdus; /* 02CC–02CF */
  1214. uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */
  1215. uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */
  1216. uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */
  1217. uint32_t tx_snack_req_pdus; /* 02DC–02DF */
  1218. uint32_t rx_nopin_pdus; /* 02E0–02E3 */
  1219. uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */
  1220. uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */
  1221. uint32_t rx_login_resp_pdus; /* 02EC–02EF */
  1222. uint32_t rx_text_resp_pdus; /* 02F0–02F3 */
  1223. uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */
  1224. uint32_t rx_logout_resp_pdus; /* 02F8–02FB */
  1225. uint32_t rx_r2t_pdus; /* 02FC–02FF */
  1226. uint32_t rx_async_pdus; /* 0300–0303 */
  1227. uint32_t rx_reject_pdus; /* 0304–0307 */
  1228. uint8_t reserved2[264]; /* 0x0308 - 0x040F */
  1229. };
  1230. #define QLA8XXX_DBG_STATE_ARRAY_LEN 16
  1231. #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8
  1232. #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8
  1233. #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN 16
  1234. #define QLA83XX_SS_OCM_WNDREG_INDEX 3
  1235. #define QLA83XX_SS_PCI_INDEX 0
  1236. #define QLA8022_TEMPLATE_CAP_OFFSET 172
  1237. #define QLA83XX_TEMPLATE_CAP_OFFSET 268
  1238. #define QLA80XX_TEMPLATE_RESERVED_BITS 16
  1239. struct qla4_8xxx_minidump_template_hdr {
  1240. uint32_t entry_type;
  1241. uint32_t first_entry_offset;
  1242. uint32_t size_of_template;
  1243. uint32_t capture_debug_level;
  1244. uint32_t num_of_entries;
  1245. uint32_t version;
  1246. uint32_t driver_timestamp;
  1247. uint32_t checksum;
  1248. uint32_t driver_capture_mask;
  1249. uint32_t driver_info_word2;
  1250. uint32_t driver_info_word3;
  1251. uint32_t driver_info_word4;
  1252. uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN];
  1253. uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN];
  1254. uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN];
  1255. uint32_t capabilities[QLA80XX_TEMPLATE_RESERVED_BITS];
  1256. };
  1257. #endif /* _QLA4X_FW_H */