ql4_dbg.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QLogic iSCSI HBA Driver
  4. * Copyright (c) 2003-2012 QLogic Corporation
  5. */
  6. #include "ql4_def.h"
  7. #include "ql4_glbl.h"
  8. #include "ql4_dbg.h"
  9. #include "ql4_inline.h"
  10. void qla4xxx_dump_buffer(void *b, uint32_t size)
  11. {
  12. uint32_t cnt;
  13. uint8_t *c = b;
  14. printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh "
  15. "Fh\n");
  16. printk("------------------------------------------------------------"
  17. "--\n");
  18. for (cnt = 0; cnt < size; c++) {
  19. printk("%02x", *c);
  20. if (!(++cnt % 16))
  21. printk("\n");
  22. else
  23. printk(" ");
  24. }
  25. printk(KERN_INFO "\n");
  26. }
  27. void qla4xxx_dump_registers(struct scsi_qla_host *ha)
  28. {
  29. uint8_t i;
  30. if (is_qla8022(ha)) {
  31. for (i = 1; i < MBOX_REG_COUNT; i++)
  32. printk(KERN_INFO "mailbox[%d] = 0x%08X\n",
  33. i, readl(&ha->qla4_82xx_reg->mailbox_in[i]));
  34. return;
  35. }
  36. for (i = 0; i < MBOX_REG_COUNT; i++) {
  37. printk(KERN_INFO "0x%02X mailbox[%d] = 0x%08X\n",
  38. (uint8_t) offsetof(struct isp_reg, mailbox[i]), i,
  39. readw(&ha->reg->mailbox[i]));
  40. }
  41. printk(KERN_INFO "0x%02X flash_address = 0x%08X\n",
  42. (uint8_t) offsetof(struct isp_reg, flash_address),
  43. readw(&ha->reg->flash_address));
  44. printk(KERN_INFO "0x%02X flash_data = 0x%08X\n",
  45. (uint8_t) offsetof(struct isp_reg, flash_data),
  46. readw(&ha->reg->flash_data));
  47. printk(KERN_INFO "0x%02X ctrl_status = 0x%08X\n",
  48. (uint8_t) offsetof(struct isp_reg, ctrl_status),
  49. readw(&ha->reg->ctrl_status));
  50. if (is_qla4010(ha)) {
  51. printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
  52. (uint8_t) offsetof(struct isp_reg, u1.isp4010.nvram),
  53. readw(&ha->reg->u1.isp4010.nvram));
  54. } else if (is_qla4022(ha) | is_qla4032(ha)) {
  55. printk(KERN_INFO "0x%02X intr_mask = 0x%08X\n",
  56. (uint8_t) offsetof(struct isp_reg, u1.isp4022.intr_mask),
  57. readw(&ha->reg->u1.isp4022.intr_mask));
  58. printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
  59. (uint8_t) offsetof(struct isp_reg, u1.isp4022.nvram),
  60. readw(&ha->reg->u1.isp4022.nvram));
  61. printk(KERN_INFO "0x%02X semaphore = 0x%08X\n",
  62. (uint8_t) offsetof(struct isp_reg, u1.isp4022.semaphore),
  63. readw(&ha->reg->u1.isp4022.semaphore));
  64. }
  65. printk(KERN_INFO "0x%02X req_q_in = 0x%08X\n",
  66. (uint8_t) offsetof(struct isp_reg, req_q_in),
  67. readw(&ha->reg->req_q_in));
  68. printk(KERN_INFO "0x%02X rsp_q_out = 0x%08X\n",
  69. (uint8_t) offsetof(struct isp_reg, rsp_q_out),
  70. readw(&ha->reg->rsp_q_out));
  71. if (is_qla4010(ha)) {
  72. printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n",
  73. (uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf),
  74. readw(&ha->reg->u2.isp4010.ext_hw_conf));
  75. printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n",
  76. (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl),
  77. readw(&ha->reg->u2.isp4010.port_ctrl));
  78. printk(KERN_INFO "0x%02X port_status = 0x%08X\n",
  79. (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status),
  80. readw(&ha->reg->u2.isp4010.port_status));
  81. printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
  82. (uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out),
  83. readw(&ha->reg->u2.isp4010.req_q_out));
  84. printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
  85. (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out),
  86. readw(&ha->reg->u2.isp4010.gp_out));
  87. printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
  88. (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_in),
  89. readw(&ha->reg->u2.isp4010.gp_in));
  90. printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)
  91. offsetof(struct isp_reg, u2.isp4010.port_err_status),
  92. readw(&ha->reg->u2.isp4010.port_err_status));
  93. } else if (is_qla4022(ha) | is_qla4032(ha)) {
  94. printk(KERN_INFO "Page 0 Registers:\n");
  95. printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n", (uint8_t)
  96. offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf),
  97. readw(&ha->reg->u2.isp4022.p0.ext_hw_conf));
  98. printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n", (uint8_t)
  99. offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl),
  100. readw(&ha->reg->u2.isp4022.p0.port_ctrl));
  101. printk(KERN_INFO "0x%02X port_status = 0x%08X\n", (uint8_t)
  102. offsetof(struct isp_reg, u2.isp4022.p0.port_status),
  103. readw(&ha->reg->u2.isp4022.p0.port_status));
  104. printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
  105. (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out),
  106. readw(&ha->reg->u2.isp4022.p0.gp_out));
  107. printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
  108. (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in),
  109. readw(&ha->reg->u2.isp4022.p0.gp_in));
  110. printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)
  111. offsetof(struct isp_reg, u2.isp4022.p0.port_err_status),
  112. readw(&ha->reg->u2.isp4022.p0.port_err_status));
  113. printk(KERN_INFO "Page 1 Registers:\n");
  114. writel(HOST_MEM_CFG_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
  115. &ha->reg->ctrl_status);
  116. printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
  117. (uint8_t) offsetof(struct isp_reg, u2.isp4022.p1.req_q_out),
  118. readw(&ha->reg->u2.isp4022.p1.req_q_out));
  119. writel(PORT_CTRL_STAT_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
  120. &ha->reg->ctrl_status);
  121. }
  122. }
  123. void qla4_8xxx_dump_peg_reg(struct scsi_qla_host *ha)
  124. {
  125. uint32_t halt_status1, halt_status2;
  126. halt_status1 = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_HALT_STATUS1);
  127. halt_status2 = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_HALT_STATUS2);
  128. if (is_qla8022(ha)) {
  129. ql4_printk(KERN_INFO, ha,
  130. "scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n"
  131. " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
  132. " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
  133. " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
  134. " PEG_NET_4_PC: 0x%x\n", ha->host_no, __func__,
  135. ha->pdev->device, halt_status1, halt_status2,
  136. qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c),
  137. qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c),
  138. qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c),
  139. qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c),
  140. qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c));
  141. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  142. ql4_printk(KERN_INFO, ha,
  143. "scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n"
  144. " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n",
  145. ha->host_no, __func__, ha->pdev->device,
  146. halt_status1, halt_status2);
  147. }
  148. }