ql4_83xx.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QLogic iSCSI HBA Driver
  4. * Copyright (c) 2003-2013 QLogic Corporation
  5. */
  6. #include <linux/ratelimit.h>
  7. #include "ql4_def.h"
  8. #include "ql4_version.h"
  9. #include "ql4_glbl.h"
  10. #include "ql4_dbg.h"
  11. #include "ql4_inline.h"
  12. uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr)
  13. {
  14. return readl((void __iomem *)(ha->nx_pcibase + addr));
  15. }
  16. void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val)
  17. {
  18. writel(val, (void __iomem *)(ha->nx_pcibase + addr));
  19. }
  20. static int qla4_83xx_set_win_base(struct scsi_qla_host *ha, uint32_t addr)
  21. {
  22. uint32_t val;
  23. int ret_val = QLA_SUCCESS;
  24. qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr);
  25. val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num));
  26. if (val != addr) {
  27. ql4_printk(KERN_ERR, ha, "%s: Failed to set register window : addr written 0x%x, read 0x%x!\n",
  28. __func__, addr, val);
  29. ret_val = QLA_ERROR;
  30. }
  31. return ret_val;
  32. }
  33. int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,
  34. uint32_t *data)
  35. {
  36. int ret_val;
  37. ret_val = qla4_83xx_set_win_base(ha, addr);
  38. if (ret_val == QLA_SUCCESS) {
  39. *data = qla4_83xx_rd_reg(ha, QLA83XX_WILDCARD);
  40. } else {
  41. *data = 0xffffffff;
  42. ql4_printk(KERN_ERR, ha, "%s: failed read of addr 0x%x!\n",
  43. __func__, addr);
  44. }
  45. return ret_val;
  46. }
  47. int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,
  48. uint32_t data)
  49. {
  50. int ret_val;
  51. ret_val = qla4_83xx_set_win_base(ha, addr);
  52. if (ret_val == QLA_SUCCESS)
  53. qla4_83xx_wr_reg(ha, QLA83XX_WILDCARD, data);
  54. else
  55. ql4_printk(KERN_ERR, ha, "%s: failed wrt to addr 0x%x, data 0x%x\n",
  56. __func__, addr, data);
  57. return ret_val;
  58. }
  59. static int qla4_83xx_flash_lock(struct scsi_qla_host *ha)
  60. {
  61. int lock_owner;
  62. int timeout = 0;
  63. uint32_t lock_status = 0;
  64. int ret_val = QLA_SUCCESS;
  65. while (lock_status == 0) {
  66. lock_status = qla4_83xx_rd_reg(ha, QLA83XX_FLASH_LOCK);
  67. if (lock_status)
  68. break;
  69. if (++timeout >= QLA83XX_FLASH_LOCK_TIMEOUT / 20) {
  70. lock_owner = qla4_83xx_rd_reg(ha,
  71. QLA83XX_FLASH_LOCK_ID);
  72. ql4_printk(KERN_ERR, ha, "%s: flash lock by func %d failed, held by func %d\n",
  73. __func__, ha->func_num, lock_owner);
  74. ret_val = QLA_ERROR;
  75. break;
  76. }
  77. msleep(20);
  78. }
  79. qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num);
  80. return ret_val;
  81. }
  82. static void qla4_83xx_flash_unlock(struct scsi_qla_host *ha)
  83. {
  84. /* Reading FLASH_UNLOCK register unlocks the Flash */
  85. qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, 0xFF);
  86. qla4_83xx_rd_reg(ha, QLA83XX_FLASH_UNLOCK);
  87. }
  88. int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr,
  89. uint8_t *p_data, int u32_word_count)
  90. {
  91. int i;
  92. uint32_t u32_word;
  93. uint32_t addr = flash_addr;
  94. int ret_val = QLA_SUCCESS;
  95. ret_val = qla4_83xx_flash_lock(ha);
  96. if (ret_val == QLA_ERROR)
  97. goto exit_lock_error;
  98. if (addr & 0x03) {
  99. ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n",
  100. __func__, addr);
  101. ret_val = QLA_ERROR;
  102. goto exit_flash_read;
  103. }
  104. for (i = 0; i < u32_word_count; i++) {
  105. ret_val = qla4_83xx_wr_reg_indirect(ha,
  106. QLA83XX_FLASH_DIRECT_WINDOW,
  107. (addr & 0xFFFF0000));
  108. if (ret_val == QLA_ERROR) {
  109. ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW\n!",
  110. __func__, addr);
  111. goto exit_flash_read;
  112. }
  113. ret_val = qla4_83xx_rd_reg_indirect(ha,
  114. QLA83XX_FLASH_DIRECT_DATA(addr),
  115. &u32_word);
  116. if (ret_val == QLA_ERROR) {
  117. ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
  118. __func__, addr);
  119. goto exit_flash_read;
  120. }
  121. *(__le32 *)p_data = le32_to_cpu(u32_word);
  122. p_data = p_data + 4;
  123. addr = addr + 4;
  124. }
  125. exit_flash_read:
  126. qla4_83xx_flash_unlock(ha);
  127. exit_lock_error:
  128. return ret_val;
  129. }
  130. int qla4_83xx_lockless_flash_read_u32(struct scsi_qla_host *ha,
  131. uint32_t flash_addr, uint8_t *p_data,
  132. int u32_word_count)
  133. {
  134. uint32_t i;
  135. uint32_t u32_word;
  136. uint32_t flash_offset;
  137. uint32_t addr = flash_addr;
  138. int ret_val = QLA_SUCCESS;
  139. flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1);
  140. if (addr & 0x3) {
  141. ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n",
  142. __func__, addr);
  143. ret_val = QLA_ERROR;
  144. goto exit_lockless_read;
  145. }
  146. ret_val = qla4_83xx_wr_reg_indirect(ha, QLA83XX_FLASH_DIRECT_WINDOW,
  147. addr);
  148. if (ret_val == QLA_ERROR) {
  149. ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
  150. __func__, addr);
  151. goto exit_lockless_read;
  152. }
  153. /* Check if data is spread across multiple sectors */
  154. if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
  155. (QLA83XX_FLASH_SECTOR_SIZE - 1)) {
  156. /* Multi sector read */
  157. for (i = 0; i < u32_word_count; i++) {
  158. ret_val = qla4_83xx_rd_reg_indirect(ha,
  159. QLA83XX_FLASH_DIRECT_DATA(addr),
  160. &u32_word);
  161. if (ret_val == QLA_ERROR) {
  162. ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
  163. __func__, addr);
  164. goto exit_lockless_read;
  165. }
  166. *(__le32 *)p_data = le32_to_cpu(u32_word);
  167. p_data = p_data + 4;
  168. addr = addr + 4;
  169. flash_offset = flash_offset + 4;
  170. if (flash_offset > (QLA83XX_FLASH_SECTOR_SIZE - 1)) {
  171. /* This write is needed once for each sector */
  172. ret_val = qla4_83xx_wr_reg_indirect(ha,
  173. QLA83XX_FLASH_DIRECT_WINDOW,
  174. addr);
  175. if (ret_val == QLA_ERROR) {
  176. ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
  177. __func__, addr);
  178. goto exit_lockless_read;
  179. }
  180. flash_offset = 0;
  181. }
  182. }
  183. } else {
  184. /* Single sector read */
  185. for (i = 0; i < u32_word_count; i++) {
  186. ret_val = qla4_83xx_rd_reg_indirect(ha,
  187. QLA83XX_FLASH_DIRECT_DATA(addr),
  188. &u32_word);
  189. if (ret_val == QLA_ERROR) {
  190. ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
  191. __func__, addr);
  192. goto exit_lockless_read;
  193. }
  194. *(__le32 *)p_data = le32_to_cpu(u32_word);
  195. p_data = p_data + 4;
  196. addr = addr + 4;
  197. }
  198. }
  199. exit_lockless_read:
  200. return ret_val;
  201. }
  202. void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
  203. {
  204. if (qla4_83xx_flash_lock(ha))
  205. ql4_printk(KERN_INFO, ha, "%s: Resetting rom lock\n", __func__);
  206. /*
  207. * We got the lock, or someone else is holding the lock
  208. * since we are restting, forcefully unlock
  209. */
  210. qla4_83xx_flash_unlock(ha);
  211. }
  212. #define INTENT_TO_RECOVER 0x01
  213. #define PROCEED_TO_RECOVER 0x02
  214. static int qla4_83xx_lock_recovery(struct scsi_qla_host *ha)
  215. {
  216. uint32_t lock = 0, lockid;
  217. int ret_val = QLA_ERROR;
  218. lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY);
  219. /* Check for other Recovery in progress, go wait */
  220. if ((lockid & 0x3) != 0)
  221. goto exit_lock_recovery;
  222. /* Intent to Recover */
  223. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY,
  224. (ha->func_num << 2) | INTENT_TO_RECOVER);
  225. msleep(200);
  226. /* Check Intent to Recover is advertised */
  227. lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY);
  228. if ((lockid & 0x3C) != (ha->func_num << 2))
  229. goto exit_lock_recovery;
  230. ql4_printk(KERN_INFO, ha, "%s: IDC Lock recovery initiated for func %d\n",
  231. __func__, ha->func_num);
  232. /* Proceed to Recover */
  233. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY,
  234. (ha->func_num << 2) | PROCEED_TO_RECOVER);
  235. /* Force Unlock */
  236. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, 0xFF);
  237. ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_UNLOCK);
  238. /* Clear bits 0-5 in IDC_RECOVERY register*/
  239. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, 0);
  240. /* Get lock */
  241. lock = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK);
  242. if (lock) {
  243. lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK_ID);
  244. lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->func_num;
  245. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, lockid);
  246. ret_val = QLA_SUCCESS;
  247. }
  248. exit_lock_recovery:
  249. return ret_val;
  250. }
  251. #define QLA83XX_DRV_LOCK_MSLEEP 200
  252. int qla4_83xx_drv_lock(struct scsi_qla_host *ha)
  253. {
  254. int timeout = 0;
  255. uint32_t status = 0;
  256. int ret_val = QLA_SUCCESS;
  257. uint32_t first_owner = 0;
  258. uint32_t tmo_owner = 0;
  259. uint32_t lock_id;
  260. uint32_t func_num;
  261. uint32_t lock_cnt;
  262. while (status == 0) {
  263. status = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK);
  264. if (status) {
  265. /* Increment Counter (8-31) and update func_num (0-7) on
  266. * getting a successful lock */
  267. lock_id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
  268. lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->func_num;
  269. qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, lock_id);
  270. break;
  271. }
  272. if (timeout == 0)
  273. /* Save counter + ID of function holding the lock for
  274. * first failure */
  275. first_owner = ha->isp_ops->rd_reg_direct(ha,
  276. QLA83XX_DRV_LOCK_ID);
  277. if (++timeout >=
  278. (QLA83XX_DRV_LOCK_TIMEOUT / QLA83XX_DRV_LOCK_MSLEEP)) {
  279. tmo_owner = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
  280. func_num = tmo_owner & 0xFF;
  281. lock_cnt = tmo_owner >> 8;
  282. ql4_printk(KERN_INFO, ha, "%s: Lock by func %d failed after 2s, lock held by func %d, lock count %d, first_owner %d\n",
  283. __func__, ha->func_num, func_num, lock_cnt,
  284. (first_owner & 0xFF));
  285. if (first_owner != tmo_owner) {
  286. /* Some other driver got lock, OR same driver
  287. * got lock again (counter value changed), when
  288. * we were waiting for lock.
  289. * Retry for another 2 sec */
  290. ql4_printk(KERN_INFO, ha, "%s: IDC lock failed for func %d\n",
  291. __func__, ha->func_num);
  292. timeout = 0;
  293. } else {
  294. /* Same driver holding lock > 2sec.
  295. * Force Recovery */
  296. ret_val = qla4_83xx_lock_recovery(ha);
  297. if (ret_val == QLA_SUCCESS) {
  298. /* Recovered and got lock */
  299. ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d successful\n",
  300. __func__, ha->func_num);
  301. break;
  302. }
  303. /* Recovery Failed, some other function
  304. * has the lock, wait for 2secs and retry */
  305. ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d failed, Retrying timeout\n",
  306. __func__, ha->func_num);
  307. timeout = 0;
  308. }
  309. }
  310. msleep(QLA83XX_DRV_LOCK_MSLEEP);
  311. }
  312. return ret_val;
  313. }
  314. void qla4_83xx_drv_unlock(struct scsi_qla_host *ha)
  315. {
  316. int id;
  317. id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
  318. if ((id & 0xFF) != ha->func_num) {
  319. ql4_printk(KERN_ERR, ha, "%s: IDC Unlock by %d failed, lock owner is %d\n",
  320. __func__, ha->func_num, (id & 0xFF));
  321. return;
  322. }
  323. /* Keep lock counter value, update the ha->func_num to 0xFF */
  324. qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, (id | 0xFF));
  325. qla4_83xx_rd_reg(ha, QLA83XX_DRV_UNLOCK);
  326. }
  327. void qla4_83xx_set_idc_dontreset(struct scsi_qla_host *ha)
  328. {
  329. uint32_t idc_ctrl;
  330. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  331. idc_ctrl |= DONTRESET_BIT0;
  332. qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl);
  333. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__,
  334. idc_ctrl));
  335. }
  336. void qla4_83xx_clear_idc_dontreset(struct scsi_qla_host *ha)
  337. {
  338. uint32_t idc_ctrl;
  339. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  340. idc_ctrl &= ~DONTRESET_BIT0;
  341. qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl);
  342. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__,
  343. idc_ctrl));
  344. }
  345. int qla4_83xx_idc_dontreset(struct scsi_qla_host *ha)
  346. {
  347. uint32_t idc_ctrl;
  348. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  349. return idc_ctrl & DONTRESET_BIT0;
  350. }
  351. /*-------------------------IDC State Machine ---------------------*/
  352. enum {
  353. UNKNOWN_CLASS = 0,
  354. NIC_CLASS,
  355. FCOE_CLASS,
  356. ISCSI_CLASS
  357. };
  358. struct device_info {
  359. int func_num;
  360. int device_type;
  361. int port_num;
  362. };
  363. int qla4_83xx_can_perform_reset(struct scsi_qla_host *ha)
  364. {
  365. uint32_t drv_active;
  366. uint32_t dev_part, dev_part1, dev_part2;
  367. int i;
  368. struct device_info device_map[16];
  369. int func_nibble;
  370. int nibble;
  371. int nic_present = 0;
  372. int iscsi_present = 0;
  373. int iscsi_func_low = 0;
  374. /* Use the dev_partition register to determine the PCI function number
  375. * and then check drv_active register to see which driver is loaded */
  376. dev_part1 = qla4_83xx_rd_reg(ha,
  377. ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]);
  378. dev_part2 = qla4_83xx_rd_reg(ha, QLA83XX_CRB_DEV_PART_INFO2);
  379. drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]);
  380. /* Each function has 4 bits in dev_partition Info register,
  381. * Lower 2 bits - device type, Upper 2 bits - physical port number */
  382. dev_part = dev_part1;
  383. for (i = nibble = 0; i <= 15; i++, nibble++) {
  384. func_nibble = dev_part & (0xF << (nibble * 4));
  385. func_nibble >>= (nibble * 4);
  386. device_map[i].func_num = i;
  387. device_map[i].device_type = func_nibble & 0x3;
  388. device_map[i].port_num = func_nibble & 0xC;
  389. if (device_map[i].device_type == NIC_CLASS) {
  390. if (drv_active & (1 << device_map[i].func_num)) {
  391. nic_present++;
  392. break;
  393. }
  394. } else if (device_map[i].device_type == ISCSI_CLASS) {
  395. if (drv_active & (1 << device_map[i].func_num)) {
  396. if (!iscsi_present ||
  397. (iscsi_present &&
  398. (iscsi_func_low > device_map[i].func_num)))
  399. iscsi_func_low = device_map[i].func_num;
  400. iscsi_present++;
  401. }
  402. }
  403. /* For function_num[8..15] get info from dev_part2 register */
  404. if (nibble == 7) {
  405. nibble = 0;
  406. dev_part = dev_part2;
  407. }
  408. }
  409. /* NIC, iSCSI and FCOE are the Reset owners based on order, NIC gets
  410. * precedence over iSCSI and FCOE and iSCSI over FCOE, based on drivers
  411. * present. */
  412. if (!nic_present && (ha->func_num == iscsi_func_low)) {
  413. DEBUG2(ql4_printk(KERN_INFO, ha,
  414. "%s: can reset - NIC not present and lower iSCSI function is %d\n",
  415. __func__, ha->func_num));
  416. return 1;
  417. }
  418. return 0;
  419. }
  420. /**
  421. * qla4_83xx_need_reset_handler - Code to start reset sequence
  422. * @ha: pointer to adapter structure
  423. *
  424. * Note: IDC lock must be held upon entry
  425. **/
  426. void qla4_83xx_need_reset_handler(struct scsi_qla_host *ha)
  427. {
  428. uint32_t dev_state, drv_state, drv_active;
  429. unsigned long reset_timeout, dev_init_timeout;
  430. ql4_printk(KERN_INFO, ha, "%s: Performing ISP error recovery\n",
  431. __func__);
  432. if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
  433. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: reset acknowledged\n",
  434. __func__));
  435. qla4_8xxx_set_rst_ready(ha);
  436. /* Non-reset owners ACK Reset and wait for device INIT state
  437. * as part of Reset Recovery by Reset Owner */
  438. dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
  439. do {
  440. if (time_after_eq(jiffies, dev_init_timeout)) {
  441. ql4_printk(KERN_INFO, ha, "%s: Non Reset owner dev init timeout\n",
  442. __func__);
  443. break;
  444. }
  445. ha->isp_ops->idc_unlock(ha);
  446. msleep(1000);
  447. ha->isp_ops->idc_lock(ha);
  448. dev_state = qla4_8xxx_rd_direct(ha,
  449. QLA8XXX_CRB_DEV_STATE);
  450. } while (dev_state == QLA8XXX_DEV_NEED_RESET);
  451. } else {
  452. qla4_8xxx_set_rst_ready(ha);
  453. reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
  454. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  455. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  456. ql4_printk(KERN_INFO, ha, "%s: drv_state = 0x%x, drv_active = 0x%x\n",
  457. __func__, drv_state, drv_active);
  458. while (drv_state != drv_active) {
  459. if (time_after_eq(jiffies, reset_timeout)) {
  460. ql4_printk(KERN_INFO, ha, "%s: %s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
  461. __func__, DRIVER_NAME, drv_state,
  462. drv_active);
  463. break;
  464. }
  465. ha->isp_ops->idc_unlock(ha);
  466. msleep(1000);
  467. ha->isp_ops->idc_lock(ha);
  468. drv_state = qla4_8xxx_rd_direct(ha,
  469. QLA8XXX_CRB_DRV_STATE);
  470. drv_active = qla4_8xxx_rd_direct(ha,
  471. QLA8XXX_CRB_DRV_ACTIVE);
  472. }
  473. if (drv_state != drv_active) {
  474. ql4_printk(KERN_INFO, ha, "%s: Reset_owner turning off drv_active of non-acking function 0x%x\n",
  475. __func__, (drv_active ^ drv_state));
  476. drv_active = drv_active & drv_state;
  477. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE,
  478. drv_active);
  479. }
  480. clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
  481. /* Start Reset Recovery */
  482. qla4_8xxx_device_bootstrap(ha);
  483. }
  484. }
  485. void qla4_83xx_get_idc_param(struct scsi_qla_host *ha)
  486. {
  487. uint32_t idc_params, ret_val;
  488. ret_val = qla4_83xx_flash_read_u32(ha, QLA83XX_IDC_PARAM_ADDR,
  489. (uint8_t *)&idc_params, 1);
  490. if (ret_val == QLA_SUCCESS) {
  491. ha->nx_dev_init_timeout = idc_params & 0xFFFF;
  492. ha->nx_reset_timeout = (idc_params >> 16) & 0xFFFF;
  493. } else {
  494. ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
  495. ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
  496. }
  497. DEBUG2(ql4_printk(KERN_DEBUG, ha,
  498. "%s: ha->nx_dev_init_timeout = %d, ha->nx_reset_timeout = %d\n",
  499. __func__, ha->nx_dev_init_timeout,
  500. ha->nx_reset_timeout));
  501. }
  502. /*-------------------------Reset Sequence Functions-----------------------*/
  503. static void qla4_83xx_dump_reset_seq_hdr(struct scsi_qla_host *ha)
  504. {
  505. uint8_t *phdr;
  506. if (!ha->reset_tmplt.buff) {
  507. ql4_printk(KERN_ERR, ha, "%s: Error: Invalid reset_seq_template\n",
  508. __func__);
  509. return;
  510. }
  511. phdr = ha->reset_tmplt.buff;
  512. DEBUG2(ql4_printk(KERN_INFO, ha,
  513. "Reset Template: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
  514. *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
  515. *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
  516. *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
  517. *(phdr+13), *(phdr+14), *(phdr+15)));
  518. }
  519. static int qla4_83xx_copy_bootloader(struct scsi_qla_host *ha)
  520. {
  521. uint8_t *p_cache;
  522. uint32_t src, count, size;
  523. uint64_t dest;
  524. int ret_val = QLA_SUCCESS;
  525. src = QLA83XX_BOOTLOADER_FLASH_ADDR;
  526. dest = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_ADDR);
  527. size = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_SIZE);
  528. /* 128 bit alignment check */
  529. if (size & 0xF)
  530. size = (size + 16) & ~0xF;
  531. /* 16 byte count */
  532. count = size/16;
  533. p_cache = vmalloc(size);
  534. if (p_cache == NULL) {
  535. ql4_printk(KERN_ERR, ha, "%s: Failed to allocate memory for boot loader cache\n",
  536. __func__);
  537. ret_val = QLA_ERROR;
  538. goto exit_copy_bootloader;
  539. }
  540. ret_val = qla4_83xx_lockless_flash_read_u32(ha, src, p_cache,
  541. size / sizeof(uint32_t));
  542. if (ret_val == QLA_ERROR) {
  543. ql4_printk(KERN_ERR, ha, "%s: Error reading firmware from flash\n",
  544. __func__);
  545. goto exit_copy_error;
  546. }
  547. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Read firmware from flash\n",
  548. __func__));
  549. /* 128 bit/16 byte write to MS memory */
  550. ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache,
  551. count);
  552. if (ret_val == QLA_ERROR) {
  553. ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n",
  554. __func__);
  555. goto exit_copy_error;
  556. }
  557. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Wrote firmware size %d to MS\n",
  558. __func__, size));
  559. exit_copy_error:
  560. vfree(p_cache);
  561. exit_copy_bootloader:
  562. return ret_val;
  563. }
  564. static int qla4_83xx_check_cmd_peg_status(struct scsi_qla_host *ha)
  565. {
  566. uint32_t val, ret_val = QLA_ERROR;
  567. int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
  568. do {
  569. val = qla4_83xx_rd_reg(ha, QLA83XX_CMDPEG_STATE);
  570. if (val == PHAN_INITIALIZE_COMPLETE) {
  571. DEBUG2(ql4_printk(KERN_INFO, ha,
  572. "%s: Command Peg initialization complete. State=0x%x\n",
  573. __func__, val));
  574. ret_val = QLA_SUCCESS;
  575. break;
  576. }
  577. msleep(CRB_CMDPEG_CHECK_DELAY);
  578. } while (--retries);
  579. return ret_val;
  580. }
  581. /**
  582. * qla4_83xx_poll_reg - Poll the given CRB addr for duration msecs till
  583. * value read ANDed with test_mask is equal to test_result.
  584. *
  585. * @ha : Pointer to adapter structure
  586. * @addr : CRB register address
  587. * @duration : Poll for total of "duration" msecs
  588. * @test_mask : Mask value read with "test_mask"
  589. * @test_result : Compare (value&test_mask) with test_result.
  590. **/
  591. static int qla4_83xx_poll_reg(struct scsi_qla_host *ha, uint32_t addr,
  592. int duration, uint32_t test_mask,
  593. uint32_t test_result)
  594. {
  595. uint32_t value;
  596. uint8_t retries;
  597. int ret_val = QLA_SUCCESS;
  598. ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value);
  599. if (ret_val == QLA_ERROR)
  600. goto exit_poll_reg;
  601. retries = duration / 10;
  602. do {
  603. if ((value & test_mask) != test_result) {
  604. msleep(duration / 10);
  605. ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value);
  606. if (ret_val == QLA_ERROR)
  607. goto exit_poll_reg;
  608. ret_val = QLA_ERROR;
  609. } else {
  610. ret_val = QLA_SUCCESS;
  611. break;
  612. }
  613. } while (retries--);
  614. exit_poll_reg:
  615. if (ret_val == QLA_ERROR) {
  616. ha->reset_tmplt.seq_error++;
  617. ql4_printk(KERN_ERR, ha, "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
  618. __func__, value, test_mask, test_result);
  619. }
  620. return ret_val;
  621. }
  622. static int qla4_83xx_reset_seq_checksum_test(struct scsi_qla_host *ha)
  623. {
  624. uint32_t sum = 0;
  625. uint16_t *buff = (uint16_t *)ha->reset_tmplt.buff;
  626. int u16_count = ha->reset_tmplt.hdr->size / sizeof(uint16_t);
  627. int ret_val;
  628. while (u16_count-- > 0)
  629. sum += *buff++;
  630. while (sum >> 16)
  631. sum = (sum & 0xFFFF) + (sum >> 16);
  632. /* checksum of 0 indicates a valid template */
  633. if (~sum) {
  634. ret_val = QLA_SUCCESS;
  635. } else {
  636. ql4_printk(KERN_ERR, ha, "%s: Reset seq checksum failed\n",
  637. __func__);
  638. ret_val = QLA_ERROR;
  639. }
  640. return ret_val;
  641. }
  642. /**
  643. * qla4_83xx_read_reset_template - Read Reset Template from Flash
  644. * @ha: Pointer to adapter structure
  645. **/
  646. void qla4_83xx_read_reset_template(struct scsi_qla_host *ha)
  647. {
  648. uint8_t *p_buff;
  649. uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
  650. uint32_t ret_val;
  651. ha->reset_tmplt.seq_error = 0;
  652. ha->reset_tmplt.buff = vmalloc(QLA83XX_RESTART_TEMPLATE_SIZE);
  653. if (ha->reset_tmplt.buff == NULL) {
  654. ql4_printk(KERN_ERR, ha, "%s: Failed to allocate reset template resources\n",
  655. __func__);
  656. goto exit_read_reset_template;
  657. }
  658. p_buff = ha->reset_tmplt.buff;
  659. addr = QLA83XX_RESET_TEMPLATE_ADDR;
  660. tmplt_hdr_def_size = sizeof(struct qla4_83xx_reset_template_hdr) /
  661. sizeof(uint32_t);
  662. DEBUG2(ql4_printk(KERN_INFO, ha,
  663. "%s: Read template hdr size %d from Flash\n",
  664. __func__, tmplt_hdr_def_size));
  665. /* Copy template header from flash */
  666. ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff,
  667. tmplt_hdr_def_size);
  668. if (ret_val != QLA_SUCCESS) {
  669. ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n",
  670. __func__);
  671. goto exit_read_template_error;
  672. }
  673. ha->reset_tmplt.hdr =
  674. (struct qla4_83xx_reset_template_hdr *)ha->reset_tmplt.buff;
  675. /* Validate the template header size and signature */
  676. tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
  677. if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
  678. (ha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
  679. ql4_printk(KERN_ERR, ha, "%s: Template Header size %d is invalid, tmplt_hdr_def_size %d\n",
  680. __func__, tmplt_hdr_size, tmplt_hdr_def_size);
  681. goto exit_read_template_error;
  682. }
  683. addr = QLA83XX_RESET_TEMPLATE_ADDR + ha->reset_tmplt.hdr->hdr_size;
  684. p_buff = ha->reset_tmplt.buff + ha->reset_tmplt.hdr->hdr_size;
  685. tmplt_hdr_def_size = (ha->reset_tmplt.hdr->size -
  686. ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t);
  687. DEBUG2(ql4_printk(KERN_INFO, ha,
  688. "%s: Read rest of the template size %d\n",
  689. __func__, ha->reset_tmplt.hdr->size));
  690. /* Copy rest of the template */
  691. ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff,
  692. tmplt_hdr_def_size);
  693. if (ret_val != QLA_SUCCESS) {
  694. ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n",
  695. __func__);
  696. goto exit_read_template_error;
  697. }
  698. /* Integrity check */
  699. if (qla4_83xx_reset_seq_checksum_test(ha)) {
  700. ql4_printk(KERN_ERR, ha, "%s: Reset Seq checksum failed!\n",
  701. __func__);
  702. goto exit_read_template_error;
  703. }
  704. DEBUG2(ql4_printk(KERN_INFO, ha,
  705. "%s: Reset Seq checksum passed, Get stop, start and init seq offsets\n",
  706. __func__));
  707. /* Get STOP, START, INIT sequence offsets */
  708. ha->reset_tmplt.init_offset = ha->reset_tmplt.buff +
  709. ha->reset_tmplt.hdr->init_seq_offset;
  710. ha->reset_tmplt.start_offset = ha->reset_tmplt.buff +
  711. ha->reset_tmplt.hdr->start_seq_offset;
  712. ha->reset_tmplt.stop_offset = ha->reset_tmplt.buff +
  713. ha->reset_tmplt.hdr->hdr_size;
  714. qla4_83xx_dump_reset_seq_hdr(ha);
  715. goto exit_read_reset_template;
  716. exit_read_template_error:
  717. vfree(ha->reset_tmplt.buff);
  718. exit_read_reset_template:
  719. return;
  720. }
  721. /**
  722. * qla4_83xx_read_write_crb_reg - Read from raddr and write value to waddr.
  723. *
  724. * @ha : Pointer to adapter structure
  725. * @raddr : CRB address to read from
  726. * @waddr : CRB address to write to
  727. **/
  728. static void qla4_83xx_read_write_crb_reg(struct scsi_qla_host *ha,
  729. uint32_t raddr, uint32_t waddr)
  730. {
  731. uint32_t value;
  732. qla4_83xx_rd_reg_indirect(ha, raddr, &value);
  733. qla4_83xx_wr_reg_indirect(ha, waddr, value);
  734. }
  735. /**
  736. * qla4_83xx_rmw_crb_reg - Read Modify Write crb register
  737. *
  738. * This function read value from raddr, AND with test_mask,
  739. * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
  740. *
  741. * @ha : Pointer to adapter structure
  742. * @raddr : CRB address to read from
  743. * @waddr : CRB address to write to
  744. * @p_rmw_hdr : header with shift/or/xor values.
  745. **/
  746. static void qla4_83xx_rmw_crb_reg(struct scsi_qla_host *ha, uint32_t raddr,
  747. uint32_t waddr,
  748. struct qla4_83xx_rmw *p_rmw_hdr)
  749. {
  750. uint32_t value;
  751. if (p_rmw_hdr->index_a)
  752. value = ha->reset_tmplt.array[p_rmw_hdr->index_a];
  753. else
  754. qla4_83xx_rd_reg_indirect(ha, raddr, &value);
  755. value &= p_rmw_hdr->test_mask;
  756. value <<= p_rmw_hdr->shl;
  757. value >>= p_rmw_hdr->shr;
  758. value |= p_rmw_hdr->or_value;
  759. value ^= p_rmw_hdr->xor_value;
  760. qla4_83xx_wr_reg_indirect(ha, waddr, value);
  761. return;
  762. }
  763. static void qla4_83xx_write_list(struct scsi_qla_host *ha,
  764. struct qla4_83xx_reset_entry_hdr *p_hdr)
  765. {
  766. struct qla4_83xx_entry *p_entry;
  767. uint32_t i;
  768. p_entry = (struct qla4_83xx_entry *)
  769. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  770. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  771. qla4_83xx_wr_reg_indirect(ha, p_entry->arg1, p_entry->arg2);
  772. if (p_hdr->delay)
  773. udelay((uint32_t)(p_hdr->delay));
  774. }
  775. }
  776. static void qla4_83xx_read_write_list(struct scsi_qla_host *ha,
  777. struct qla4_83xx_reset_entry_hdr *p_hdr)
  778. {
  779. struct qla4_83xx_entry *p_entry;
  780. uint32_t i;
  781. p_entry = (struct qla4_83xx_entry *)
  782. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  783. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  784. qla4_83xx_read_write_crb_reg(ha, p_entry->arg1, p_entry->arg2);
  785. if (p_hdr->delay)
  786. udelay((uint32_t)(p_hdr->delay));
  787. }
  788. }
  789. static void qla4_83xx_poll_list(struct scsi_qla_host *ha,
  790. struct qla4_83xx_reset_entry_hdr *p_hdr)
  791. {
  792. long delay;
  793. struct qla4_83xx_entry *p_entry;
  794. struct qla4_83xx_poll *p_poll;
  795. uint32_t i;
  796. uint32_t value;
  797. p_poll = (struct qla4_83xx_poll *)
  798. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  799. /* Entries start after 8 byte qla4_83xx_poll, poll header contains
  800. * the test_mask, test_value. */
  801. p_entry = (struct qla4_83xx_entry *)((char *)p_poll +
  802. sizeof(struct qla4_83xx_poll));
  803. delay = (long)p_hdr->delay;
  804. if (!delay) {
  805. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  806. qla4_83xx_poll_reg(ha, p_entry->arg1, delay,
  807. p_poll->test_mask,
  808. p_poll->test_value);
  809. }
  810. } else {
  811. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  812. if (qla4_83xx_poll_reg(ha, p_entry->arg1, delay,
  813. p_poll->test_mask,
  814. p_poll->test_value)) {
  815. qla4_83xx_rd_reg_indirect(ha, p_entry->arg1,
  816. &value);
  817. qla4_83xx_rd_reg_indirect(ha, p_entry->arg2,
  818. &value);
  819. }
  820. }
  821. }
  822. }
  823. static void qla4_83xx_poll_write_list(struct scsi_qla_host *ha,
  824. struct qla4_83xx_reset_entry_hdr *p_hdr)
  825. {
  826. long delay;
  827. struct qla4_83xx_quad_entry *p_entry;
  828. struct qla4_83xx_poll *p_poll;
  829. uint32_t i;
  830. p_poll = (struct qla4_83xx_poll *)
  831. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  832. p_entry = (struct qla4_83xx_quad_entry *)
  833. ((char *)p_poll + sizeof(struct qla4_83xx_poll));
  834. delay = (long)p_hdr->delay;
  835. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  836. qla4_83xx_wr_reg_indirect(ha, p_entry->dr_addr,
  837. p_entry->dr_value);
  838. qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr,
  839. p_entry->ar_value);
  840. if (delay) {
  841. if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay,
  842. p_poll->test_mask,
  843. p_poll->test_value)) {
  844. DEBUG2(ql4_printk(KERN_INFO, ha,
  845. "%s: Timeout Error: poll list, item_num %d, entry_num %d\n",
  846. __func__, i,
  847. ha->reset_tmplt.seq_index));
  848. }
  849. }
  850. }
  851. }
  852. static void qla4_83xx_read_modify_write(struct scsi_qla_host *ha,
  853. struct qla4_83xx_reset_entry_hdr *p_hdr)
  854. {
  855. struct qla4_83xx_entry *p_entry;
  856. struct qla4_83xx_rmw *p_rmw_hdr;
  857. uint32_t i;
  858. p_rmw_hdr = (struct qla4_83xx_rmw *)
  859. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  860. p_entry = (struct qla4_83xx_entry *)
  861. ((char *)p_rmw_hdr + sizeof(struct qla4_83xx_rmw));
  862. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  863. qla4_83xx_rmw_crb_reg(ha, p_entry->arg1, p_entry->arg2,
  864. p_rmw_hdr);
  865. if (p_hdr->delay)
  866. udelay((uint32_t)(p_hdr->delay));
  867. }
  868. }
  869. static void qla4_83xx_pause(struct scsi_qla_host *ha,
  870. struct qla4_83xx_reset_entry_hdr *p_hdr)
  871. {
  872. if (p_hdr->delay)
  873. mdelay((uint32_t)((long)p_hdr->delay));
  874. }
  875. static void qla4_83xx_poll_read_list(struct scsi_qla_host *ha,
  876. struct qla4_83xx_reset_entry_hdr *p_hdr)
  877. {
  878. long delay;
  879. int index;
  880. struct qla4_83xx_quad_entry *p_entry;
  881. struct qla4_83xx_poll *p_poll;
  882. uint32_t i;
  883. uint32_t value;
  884. p_poll = (struct qla4_83xx_poll *)
  885. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  886. p_entry = (struct qla4_83xx_quad_entry *)
  887. ((char *)p_poll + sizeof(struct qla4_83xx_poll));
  888. delay = (long)p_hdr->delay;
  889. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  890. qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr,
  891. p_entry->ar_value);
  892. if (delay) {
  893. if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay,
  894. p_poll->test_mask,
  895. p_poll->test_value)) {
  896. DEBUG2(ql4_printk(KERN_INFO, ha,
  897. "%s: Timeout Error: poll list, Item_num %d, entry_num %d\n",
  898. __func__, i,
  899. ha->reset_tmplt.seq_index));
  900. } else {
  901. index = ha->reset_tmplt.array_index;
  902. qla4_83xx_rd_reg_indirect(ha, p_entry->dr_addr,
  903. &value);
  904. ha->reset_tmplt.array[index++] = value;
  905. if (index == QLA83XX_MAX_RESET_SEQ_ENTRIES)
  906. ha->reset_tmplt.array_index = 1;
  907. }
  908. }
  909. }
  910. }
  911. static void qla4_83xx_seq_end(struct scsi_qla_host *ha,
  912. struct qla4_83xx_reset_entry_hdr *p_hdr)
  913. {
  914. ha->reset_tmplt.seq_end = 1;
  915. }
  916. static void qla4_83xx_template_end(struct scsi_qla_host *ha,
  917. struct qla4_83xx_reset_entry_hdr *p_hdr)
  918. {
  919. ha->reset_tmplt.template_end = 1;
  920. if (ha->reset_tmplt.seq_error == 0) {
  921. DEBUG2(ql4_printk(KERN_INFO, ha,
  922. "%s: Reset sequence completed SUCCESSFULLY.\n",
  923. __func__));
  924. } else {
  925. ql4_printk(KERN_ERR, ha, "%s: Reset sequence completed with some timeout errors.\n",
  926. __func__);
  927. }
  928. }
  929. /**
  930. * qla4_83xx_process_reset_template - Process reset template.
  931. *
  932. * Process all entries in reset template till entry with SEQ_END opcode,
  933. * which indicates end of the reset template processing. Each entry has a
  934. * Reset Entry header, entry opcode/command, with size of the entry, number
  935. * of entries in sub-sequence and delay in microsecs or timeout in millisecs.
  936. *
  937. * @ha : Pointer to adapter structure
  938. * @p_buff : Common reset entry header.
  939. **/
  940. static void qla4_83xx_process_reset_template(struct scsi_qla_host *ha,
  941. char *p_buff)
  942. {
  943. int index, entries;
  944. struct qla4_83xx_reset_entry_hdr *p_hdr;
  945. char *p_entry = p_buff;
  946. ha->reset_tmplt.seq_end = 0;
  947. ha->reset_tmplt.template_end = 0;
  948. entries = ha->reset_tmplt.hdr->entries;
  949. index = ha->reset_tmplt.seq_index;
  950. for (; (!ha->reset_tmplt.seq_end) && (index < entries); index++) {
  951. p_hdr = (struct qla4_83xx_reset_entry_hdr *)p_entry;
  952. switch (p_hdr->cmd) {
  953. case OPCODE_NOP:
  954. break;
  955. case OPCODE_WRITE_LIST:
  956. qla4_83xx_write_list(ha, p_hdr);
  957. break;
  958. case OPCODE_READ_WRITE_LIST:
  959. qla4_83xx_read_write_list(ha, p_hdr);
  960. break;
  961. case OPCODE_POLL_LIST:
  962. qla4_83xx_poll_list(ha, p_hdr);
  963. break;
  964. case OPCODE_POLL_WRITE_LIST:
  965. qla4_83xx_poll_write_list(ha, p_hdr);
  966. break;
  967. case OPCODE_READ_MODIFY_WRITE:
  968. qla4_83xx_read_modify_write(ha, p_hdr);
  969. break;
  970. case OPCODE_SEQ_PAUSE:
  971. qla4_83xx_pause(ha, p_hdr);
  972. break;
  973. case OPCODE_SEQ_END:
  974. qla4_83xx_seq_end(ha, p_hdr);
  975. break;
  976. case OPCODE_TMPL_END:
  977. qla4_83xx_template_end(ha, p_hdr);
  978. break;
  979. case OPCODE_POLL_READ_LIST:
  980. qla4_83xx_poll_read_list(ha, p_hdr);
  981. break;
  982. default:
  983. ql4_printk(KERN_ERR, ha, "%s: Unknown command ==> 0x%04x on entry = %d\n",
  984. __func__, p_hdr->cmd, index);
  985. break;
  986. }
  987. /* Set pointer to next entry in the sequence. */
  988. p_entry += p_hdr->size;
  989. }
  990. ha->reset_tmplt.seq_index = index;
  991. }
  992. static void qla4_83xx_process_stop_seq(struct scsi_qla_host *ha)
  993. {
  994. ha->reset_tmplt.seq_index = 0;
  995. qla4_83xx_process_reset_template(ha, ha->reset_tmplt.stop_offset);
  996. if (ha->reset_tmplt.seq_end != 1)
  997. ql4_printk(KERN_ERR, ha, "%s: Abrupt STOP Sub-Sequence end.\n",
  998. __func__);
  999. }
  1000. static void qla4_83xx_process_start_seq(struct scsi_qla_host *ha)
  1001. {
  1002. qla4_83xx_process_reset_template(ha, ha->reset_tmplt.start_offset);
  1003. if (ha->reset_tmplt.template_end != 1)
  1004. ql4_printk(KERN_ERR, ha, "%s: Abrupt START Sub-Sequence end.\n",
  1005. __func__);
  1006. }
  1007. static void qla4_83xx_process_init_seq(struct scsi_qla_host *ha)
  1008. {
  1009. qla4_83xx_process_reset_template(ha, ha->reset_tmplt.init_offset);
  1010. if (ha->reset_tmplt.seq_end != 1)
  1011. ql4_printk(KERN_ERR, ha, "%s: Abrupt INIT Sub-Sequence end.\n",
  1012. __func__);
  1013. }
  1014. static int qla4_83xx_restart(struct scsi_qla_host *ha)
  1015. {
  1016. int ret_val = QLA_SUCCESS;
  1017. uint32_t idc_ctrl;
  1018. qla4_83xx_process_stop_seq(ha);
  1019. /*
  1020. * Collect minidump.
  1021. * If IDC_CTRL BIT1 is set, clear it on going to INIT state and
  1022. * don't collect minidump
  1023. */
  1024. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  1025. if (idc_ctrl & GRACEFUL_RESET_BIT1) {
  1026. qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL,
  1027. (idc_ctrl & ~GRACEFUL_RESET_BIT1));
  1028. ql4_printk(KERN_INFO, ha, "%s: Graceful RESET: Not collecting minidump\n",
  1029. __func__);
  1030. } else {
  1031. qla4_8xxx_get_minidump(ha);
  1032. }
  1033. qla4_83xx_process_init_seq(ha);
  1034. if (qla4_83xx_copy_bootloader(ha)) {
  1035. ql4_printk(KERN_ERR, ha, "%s: Copy bootloader, firmware restart failed!\n",
  1036. __func__);
  1037. ret_val = QLA_ERROR;
  1038. goto exit_restart;
  1039. }
  1040. qla4_83xx_wr_reg(ha, QLA83XX_FW_IMAGE_VALID, QLA83XX_BOOT_FROM_FLASH);
  1041. qla4_83xx_process_start_seq(ha);
  1042. exit_restart:
  1043. return ret_val;
  1044. }
  1045. int qla4_83xx_start_firmware(struct scsi_qla_host *ha)
  1046. {
  1047. int ret_val = QLA_SUCCESS;
  1048. ret_val = qla4_83xx_restart(ha);
  1049. if (ret_val == QLA_ERROR) {
  1050. ql4_printk(KERN_ERR, ha, "%s: Restart error\n", __func__);
  1051. goto exit_start_fw;
  1052. } else {
  1053. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Restart done\n",
  1054. __func__));
  1055. }
  1056. ret_val = qla4_83xx_check_cmd_peg_status(ha);
  1057. if (ret_val == QLA_ERROR)
  1058. ql4_printk(KERN_ERR, ha, "%s: Peg not initialized\n",
  1059. __func__);
  1060. exit_start_fw:
  1061. return ret_val;
  1062. }
  1063. /*----------------------Interrupt Related functions ---------------------*/
  1064. static void qla4_83xx_disable_iocb_intrs(struct scsi_qla_host *ha)
  1065. {
  1066. if (test_and_clear_bit(AF_83XX_IOCB_INTR_ON, &ha->flags))
  1067. qla4_8xxx_intr_disable(ha);
  1068. }
  1069. static void qla4_83xx_disable_mbox_intrs(struct scsi_qla_host *ha)
  1070. {
  1071. uint32_t mb_int, ret;
  1072. if (test_and_clear_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
  1073. ret = readl(&ha->qla4_83xx_reg->mbox_int);
  1074. mb_int = ret & ~INT_ENABLE_FW_MB;
  1075. writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
  1076. writel(1, &ha->qla4_83xx_reg->leg_int_mask);
  1077. }
  1078. }
  1079. void qla4_83xx_disable_intrs(struct scsi_qla_host *ha)
  1080. {
  1081. qla4_83xx_disable_mbox_intrs(ha);
  1082. qla4_83xx_disable_iocb_intrs(ha);
  1083. }
  1084. static void qla4_83xx_enable_iocb_intrs(struct scsi_qla_host *ha)
  1085. {
  1086. if (!test_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) {
  1087. qla4_8xxx_intr_enable(ha);
  1088. set_bit(AF_83XX_IOCB_INTR_ON, &ha->flags);
  1089. }
  1090. }
  1091. void qla4_83xx_enable_mbox_intrs(struct scsi_qla_host *ha)
  1092. {
  1093. uint32_t mb_int;
  1094. if (!test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
  1095. mb_int = INT_ENABLE_FW_MB;
  1096. writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
  1097. writel(0, &ha->qla4_83xx_reg->leg_int_mask);
  1098. set_bit(AF_83XX_MBOX_INTR_ON, &ha->flags);
  1099. }
  1100. }
  1101. void qla4_83xx_enable_intrs(struct scsi_qla_host *ha)
  1102. {
  1103. qla4_83xx_enable_mbox_intrs(ha);
  1104. qla4_83xx_enable_iocb_intrs(ha);
  1105. }
  1106. void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  1107. int incount)
  1108. {
  1109. int i;
  1110. /* Load all mailbox registers, except mailbox 0. */
  1111. for (i = 1; i < incount; i++)
  1112. writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]);
  1113. writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]);
  1114. /* Set Host Interrupt register to 1, to tell the firmware that
  1115. * a mailbox command is pending. Firmware after reading the
  1116. * mailbox command, clears the host interrupt register */
  1117. writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr);
  1118. }
  1119. void qla4_83xx_process_mbox_intr(struct scsi_qla_host *ha, int outcount)
  1120. {
  1121. int intr_status;
  1122. intr_status = readl(&ha->qla4_83xx_reg->risc_intr);
  1123. if (intr_status) {
  1124. ha->mbox_status_count = outcount;
  1125. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  1126. }
  1127. }
  1128. /**
  1129. * qla4_83xx_isp_reset - Resets ISP and aborts all outstanding commands.
  1130. * @ha: pointer to host adapter structure.
  1131. **/
  1132. int qla4_83xx_isp_reset(struct scsi_qla_host *ha)
  1133. {
  1134. int rval;
  1135. uint32_t dev_state;
  1136. ha->isp_ops->idc_lock(ha);
  1137. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  1138. if (ql4xdontresethba)
  1139. qla4_83xx_set_idc_dontreset(ha);
  1140. if (dev_state == QLA8XXX_DEV_READY) {
  1141. /* If IDC_CTRL DONTRESETHBA_BIT0 is set dont do reset
  1142. * recovery */
  1143. if (qla4_83xx_idc_dontreset(ha) == DONTRESET_BIT0) {
  1144. ql4_printk(KERN_ERR, ha, "%s: Reset recovery disabled\n",
  1145. __func__);
  1146. rval = QLA_ERROR;
  1147. goto exit_isp_reset;
  1148. }
  1149. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: HW State: NEED RESET\n",
  1150. __func__));
  1151. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  1152. QLA8XXX_DEV_NEED_RESET);
  1153. } else {
  1154. /* If device_state is NEED_RESET, go ahead with
  1155. * Reset,irrespective of ql4xdontresethba. This is to allow a
  1156. * non-reset-owner to force a reset. Non-reset-owner sets
  1157. * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
  1158. * and then forces a Reset by setting device_state to
  1159. * NEED_RESET. */
  1160. DEBUG2(ql4_printk(KERN_INFO, ha,
  1161. "%s: HW state already set to NEED_RESET\n",
  1162. __func__));
  1163. }
  1164. /* For ISP8324 and ISP8042, Reset owner is NIC, iSCSI or FCOE based on
  1165. * priority and which drivers are present. Unlike ISP8022, the function
  1166. * setting NEED_RESET, may not be the Reset owner. */
  1167. if (qla4_83xx_can_perform_reset(ha))
  1168. set_bit(AF_8XXX_RST_OWNER, &ha->flags);
  1169. ha->isp_ops->idc_unlock(ha);
  1170. rval = qla4_8xxx_device_state_handler(ha);
  1171. ha->isp_ops->idc_lock(ha);
  1172. qla4_8xxx_clear_rst_ready(ha);
  1173. exit_isp_reset:
  1174. ha->isp_ops->idc_unlock(ha);
  1175. if (rval == QLA_SUCCESS)
  1176. clear_bit(AF_FW_RECOVERY, &ha->flags);
  1177. return rval;
  1178. }
  1179. static void qla4_83xx_dump_pause_control_regs(struct scsi_qla_host *ha)
  1180. {
  1181. u32 val = 0, val1 = 0;
  1182. int i;
  1183. qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val);
  1184. DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val));
  1185. /* Port 0 Rx Buffer Pause Threshold Registers. */
  1186. DEBUG2(ql4_printk(KERN_INFO, ha,
  1187. "Port 0 Rx Buffer Pause Threshold Registers[TC7..TC0]:"));
  1188. for (i = 0; i < 8; i++) {
  1189. qla4_83xx_rd_reg_indirect(ha,
  1190. QLA83XX_PORT0_RXB_PAUSE_THRS + (i * 0x4), &val);
  1191. DEBUG2(pr_info("0x%x ", val));
  1192. }
  1193. DEBUG2(pr_info("\n"));
  1194. /* Port 1 Rx Buffer Pause Threshold Registers. */
  1195. DEBUG2(ql4_printk(KERN_INFO, ha,
  1196. "Port 1 Rx Buffer Pause Threshold Registers[TC7..TC0]:"));
  1197. for (i = 0; i < 8; i++) {
  1198. qla4_83xx_rd_reg_indirect(ha,
  1199. QLA83XX_PORT1_RXB_PAUSE_THRS + (i * 0x4), &val);
  1200. DEBUG2(pr_info("0x%x ", val));
  1201. }
  1202. DEBUG2(pr_info("\n"));
  1203. /* Port 0 RxB Traffic Class Max Cell Registers. */
  1204. DEBUG2(ql4_printk(KERN_INFO, ha,
  1205. "Port 0 RxB Traffic Class Max Cell Registers[3..0]:"));
  1206. for (i = 0; i < 4; i++) {
  1207. qla4_83xx_rd_reg_indirect(ha,
  1208. QLA83XX_PORT0_RXB_TC_MAX_CELL + (i * 0x4), &val);
  1209. DEBUG2(pr_info("0x%x ", val));
  1210. }
  1211. DEBUG2(pr_info("\n"));
  1212. /* Port 1 RxB Traffic Class Max Cell Registers. */
  1213. DEBUG2(ql4_printk(KERN_INFO, ha,
  1214. "Port 1 RxB Traffic Class Max Cell Registers[3..0]:"));
  1215. for (i = 0; i < 4; i++) {
  1216. qla4_83xx_rd_reg_indirect(ha,
  1217. QLA83XX_PORT1_RXB_TC_MAX_CELL + (i * 0x4), &val);
  1218. DEBUG2(pr_info("0x%x ", val));
  1219. }
  1220. DEBUG2(pr_info("\n"));
  1221. /* Port 0 RxB Rx Traffic Class Stats. */
  1222. DEBUG2(ql4_printk(KERN_INFO, ha,
  1223. "Port 0 RxB Rx Traffic Class Stats [TC7..TC0]"));
  1224. for (i = 7; i >= 0; i--) {
  1225. qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val);
  1226. val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
  1227. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS,
  1228. (val | (i << 29)));
  1229. qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val);
  1230. DEBUG2(pr_info("0x%x ", val));
  1231. }
  1232. DEBUG2(pr_info("\n"));
  1233. /* Port 1 RxB Rx Traffic Class Stats. */
  1234. DEBUG2(ql4_printk(KERN_INFO, ha,
  1235. "Port 1 RxB Rx Traffic Class Stats [TC7..TC0]"));
  1236. for (i = 7; i >= 0; i--) {
  1237. qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val);
  1238. val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
  1239. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS,
  1240. (val | (i << 29)));
  1241. qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val);
  1242. DEBUG2(pr_info("0x%x ", val));
  1243. }
  1244. DEBUG2(pr_info("\n"));
  1245. qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS, &val);
  1246. qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS, &val1);
  1247. DEBUG2(ql4_printk(KERN_INFO, ha,
  1248. "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
  1249. val, val1));
  1250. }
  1251. static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha)
  1252. {
  1253. int i;
  1254. /* set SRE-Shim Control Register */
  1255. qla4_83xx_wr_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL,
  1256. QLA83XX_SET_PAUSE_VAL);
  1257. for (i = 0; i < 8; i++) {
  1258. /* Port 0 Rx Buffer Pause Threshold Registers. */
  1259. qla4_83xx_wr_reg_indirect(ha,
  1260. QLA83XX_PORT0_RXB_PAUSE_THRS + (i * 0x4),
  1261. QLA83XX_SET_PAUSE_VAL);
  1262. /* Port 1 Rx Buffer Pause Threshold Registers. */
  1263. qla4_83xx_wr_reg_indirect(ha,
  1264. QLA83XX_PORT1_RXB_PAUSE_THRS + (i * 0x4),
  1265. QLA83XX_SET_PAUSE_VAL);
  1266. }
  1267. for (i = 0; i < 4; i++) {
  1268. /* Port 0 RxB Traffic Class Max Cell Registers. */
  1269. qla4_83xx_wr_reg_indirect(ha,
  1270. QLA83XX_PORT0_RXB_TC_MAX_CELL + (i * 0x4),
  1271. QLA83XX_SET_TC_MAX_CELL_VAL);
  1272. /* Port 1 RxB Traffic Class Max Cell Registers. */
  1273. qla4_83xx_wr_reg_indirect(ha,
  1274. QLA83XX_PORT1_RXB_TC_MAX_CELL + (i * 0x4),
  1275. QLA83XX_SET_TC_MAX_CELL_VAL);
  1276. }
  1277. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS,
  1278. QLA83XX_SET_PAUSE_VAL);
  1279. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS,
  1280. QLA83XX_SET_PAUSE_VAL);
  1281. ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n");
  1282. }
  1283. /**
  1284. * qla4_83xx_eport_init - Initialize EPort.
  1285. * @ha: Pointer to host adapter structure.
  1286. *
  1287. * If EPort hardware is in reset state before disabling pause, there would be
  1288. * serious hardware wedging issues. To prevent this perform eport init everytime
  1289. * before disabling pause frames.
  1290. **/
  1291. static void qla4_83xx_eport_init(struct scsi_qla_host *ha)
  1292. {
  1293. /* Clear the 8 registers */
  1294. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0);
  1295. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0);
  1296. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0);
  1297. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0);
  1298. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0);
  1299. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0);
  1300. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0);
  1301. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0);
  1302. /* Write any value to Reset Control register */
  1303. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF);
  1304. ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n");
  1305. }
  1306. void qla4_83xx_disable_pause(struct scsi_qla_host *ha)
  1307. {
  1308. ha->isp_ops->idc_lock(ha);
  1309. /* Before disabling pause frames, ensure that eport is not in reset */
  1310. qla4_83xx_eport_init(ha);
  1311. qla4_83xx_dump_pause_control_regs(ha);
  1312. __qla4_83xx_disable_pause(ha);
  1313. ha->isp_ops->idc_unlock(ha);
  1314. }
  1315. /**
  1316. * qla4_83xx_is_detached - Check if we are marked invisible.
  1317. * @ha: Pointer to host adapter structure.
  1318. **/
  1319. int qla4_83xx_is_detached(struct scsi_qla_host *ha)
  1320. {
  1321. uint32_t drv_active;
  1322. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1323. if (test_bit(AF_INIT_DONE, &ha->flags) &&
  1324. !(drv_active & (1 << ha->func_num))) {
  1325. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: drv_active = 0x%X\n",
  1326. __func__, drv_active));
  1327. return QLA_SUCCESS;
  1328. }
  1329. return QLA_ERROR;
  1330. }