qla1280.h 34 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /******************************************************************************
  3. * QLOGIC LINUX SOFTWARE
  4. *
  5. * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
  6. * Copyright (C) 2000 Qlogic Corporation
  7. * (www.qlogic.com)
  8. *
  9. ******************************************************************************/
  10. #ifndef _QLA1280_H
  11. #define _QLA1280_H
  12. /*
  13. * Data bit definitions.
  14. */
  15. #define BIT_0 0x1
  16. #define BIT_1 0x2
  17. #define BIT_2 0x4
  18. #define BIT_3 0x8
  19. #define BIT_4 0x10
  20. #define BIT_5 0x20
  21. #define BIT_6 0x40
  22. #define BIT_7 0x80
  23. #define BIT_8 0x100
  24. #define BIT_9 0x200
  25. #define BIT_10 0x400
  26. #define BIT_11 0x800
  27. #define BIT_12 0x1000
  28. #define BIT_13 0x2000
  29. #define BIT_14 0x4000
  30. #define BIT_15 0x8000
  31. #define BIT_16 0x10000
  32. #define BIT_17 0x20000
  33. #define BIT_18 0x40000
  34. #define BIT_19 0x80000
  35. #define BIT_20 0x100000
  36. #define BIT_21 0x200000
  37. #define BIT_22 0x400000
  38. #define BIT_23 0x800000
  39. #define BIT_24 0x1000000
  40. #define BIT_25 0x2000000
  41. #define BIT_26 0x4000000
  42. #define BIT_27 0x8000000
  43. #define BIT_28 0x10000000
  44. #define BIT_29 0x20000000
  45. #define BIT_30 0x40000000
  46. #define BIT_31 0x80000000
  47. #if MEMORY_MAPPED_IO
  48. #define RD_REG_WORD(addr) readw_relaxed(addr)
  49. #define RD_REG_WORD_dmasync(addr) readw(addr)
  50. #define WRT_REG_WORD(addr, data) writew(data, addr)
  51. #else /* MEMORY_MAPPED_IO */
  52. #define RD_REG_WORD(addr) inw((unsigned long)addr)
  53. #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr)
  54. #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr)
  55. #endif /* MEMORY_MAPPED_IO */
  56. /*
  57. * Host adapter default definitions.
  58. */
  59. #define MAX_BUSES 2 /* 2 */
  60. #define MAX_B_BITS 1
  61. #define MAX_TARGETS 16 /* 16 */
  62. #define MAX_T_BITS 4 /* 4 */
  63. #define MAX_LUNS 8 /* 32 */
  64. #define MAX_L_BITS 3 /* 5 */
  65. /*
  66. * Watchdog time quantum
  67. */
  68. #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */
  69. /* Command retry count (0-65535) */
  70. #define COMMAND_RETRY_COUNT 255
  71. /* Maximum outstanding commands in ISP queues */
  72. #define MAX_OUTSTANDING_COMMANDS 512
  73. #define COMPLETED_HANDLE ((unsigned char *) \
  74. (MAX_OUTSTANDING_COMMANDS + 2))
  75. /* ISP request and response entry counts (37-65535) */
  76. #define REQUEST_ENTRY_CNT 255 /* Number of request entries. */
  77. #define RESPONSE_ENTRY_CNT 63 /* Number of response entries. */
  78. /*
  79. * SCSI Request Block structure (sp) that is placed
  80. * on cmd->SCp location of every I/O
  81. */
  82. struct srb {
  83. struct list_head list; /* (8/16) LU queue */
  84. struct scsi_cmnd *cmd; /* (4/8) SCSI command block */
  85. /* NOTE: the sp->cmd will be NULL when this completion is
  86. * called, so you should know the scsi_cmnd when using this */
  87. struct completion *wait;
  88. dma_addr_t saved_dma_handle; /* for unmap of single transfers */
  89. uint8_t flags; /* (1) Status flags. */
  90. uint8_t dir; /* direction of transfer */
  91. };
  92. /*
  93. * SRB flag definitions
  94. */
  95. #define SRB_TIMEOUT (1 << 0) /* Command timed out */
  96. #define SRB_SENT (1 << 1) /* Command sent to ISP */
  97. #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */
  98. #define SRB_ABORTED (1 << 3) /* Command aborted command already */
  99. /*
  100. * ISP I/O Register Set structure definitions.
  101. */
  102. struct device_reg {
  103. uint16_t id_l; /* ID low */
  104. uint16_t id_h; /* ID high */
  105. uint16_t cfg_0; /* Configuration 0 */
  106. #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
  107. #define ISP_CFG0_1020 BIT_0 /* ISP1020 */
  108. #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
  109. #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
  110. #define ISP_CFG0_1040A BIT_3 /* ISP1040A */
  111. #define ISP_CFG0_1040B BIT_4 /* ISP1040B */
  112. #define ISP_CFG0_1040C BIT_5 /* ISP1040C */
  113. uint16_t cfg_1; /* Configuration 1 */
  114. #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */
  115. #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */
  116. #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */
  117. #define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */
  118. #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
  119. #define ISP_CFG1_SXP BIT_0 /* SXP register select */
  120. uint16_t ictrl; /* Interface control */
  121. #define ISP_RESET BIT_0 /* ISP soft reset */
  122. #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
  123. #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
  124. #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */
  125. #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
  126. uint16_t istatus; /* Interface status */
  127. #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */
  128. #define RISC_INT BIT_2 /* RISC interrupt */
  129. #define PCI_INT BIT_1 /* PCI interrupt */
  130. uint16_t semaphore; /* Semaphore */
  131. uint16_t nvram; /* NVRAM register. */
  132. #define NV_DESELECT 0
  133. #define NV_CLOCK BIT_0
  134. #define NV_SELECT BIT_1
  135. #define NV_DATA_OUT BIT_2
  136. #define NV_DATA_IN BIT_3
  137. uint16_t flash_data; /* Flash BIOS data */
  138. uint16_t flash_address; /* Flash BIOS address */
  139. uint16_t unused_1[0x06];
  140. /* cdma_* and ddma_* are 1040 only */
  141. uint16_t cdma_cfg;
  142. #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
  143. #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
  144. #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
  145. #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
  146. uint16_t cdma_ctrl;
  147. uint16_t cdma_status;
  148. uint16_t cdma_fifo_status;
  149. uint16_t cdma_count;
  150. uint16_t cdma_reserved;
  151. uint16_t cdma_address_count_0;
  152. uint16_t cdma_address_count_1;
  153. uint16_t cdma_address_count_2;
  154. uint16_t cdma_address_count_3;
  155. uint16_t unused_2[0x06];
  156. uint16_t ddma_cfg;
  157. #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
  158. #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
  159. #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
  160. #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
  161. uint16_t ddma_ctrl;
  162. uint16_t ddma_status;
  163. uint16_t ddma_fifo_status;
  164. uint16_t ddma_xfer_count_low;
  165. uint16_t ddma_xfer_count_high;
  166. uint16_t ddma_addr_count_0;
  167. uint16_t ddma_addr_count_1;
  168. uint16_t ddma_addr_count_2;
  169. uint16_t ddma_addr_count_3;
  170. uint16_t unused_3[0x0e];
  171. uint16_t mailbox0; /* Mailbox 0 */
  172. uint16_t mailbox1; /* Mailbox 1 */
  173. uint16_t mailbox2; /* Mailbox 2 */
  174. uint16_t mailbox3; /* Mailbox 3 */
  175. uint16_t mailbox4; /* Mailbox 4 */
  176. uint16_t mailbox5; /* Mailbox 5 */
  177. uint16_t mailbox6; /* Mailbox 6 */
  178. uint16_t mailbox7; /* Mailbox 7 */
  179. uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
  180. uint16_t host_cmd; /* Host command and control */
  181. #define HOST_INT BIT_7 /* host interrupt bit */
  182. #define BIOS_ENABLE BIT_0
  183. uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
  184. uint16_t gpio_data;
  185. uint16_t gpio_enable;
  186. uint16_t unused_6[0x11]; /* d0-f0 */
  187. uint16_t scsiControlPins; /* f2 */
  188. };
  189. #define MAILBOX_REGISTER_COUNT 8
  190. /*
  191. * ISP product identification definitions in mailboxes after reset.
  192. */
  193. #define PROD_ID_1 0x4953
  194. #define PROD_ID_2 0x0000
  195. #define PROD_ID_2a 0x5020
  196. #define PROD_ID_3 0x2020
  197. #define PROD_ID_4 0x1
  198. /*
  199. * ISP host command and control register command definitions
  200. */
  201. #define HC_RESET_RISC 0x1000 /* Reset RISC */
  202. #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
  203. #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
  204. #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
  205. #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
  206. #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
  207. #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */
  208. /*
  209. * ISP mailbox Self-Test status codes
  210. */
  211. #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
  212. #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
  213. #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */
  214. #define MBS_BUSY 4 /* Busy. */
  215. /*
  216. * ISP mailbox command complete status codes
  217. */
  218. #define MBS_CMD_CMP 0x4000 /* Command Complete. */
  219. #define MBS_INV_CMD 0x4001 /* Invalid Command. */
  220. #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */
  221. #define MBS_TEST_FAILED 0x4003 /* Test Failed. */
  222. #define MBS_CMD_ERR 0x4005 /* Command Error. */
  223. #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */
  224. /*
  225. * ISP mailbox asynchronous event status codes
  226. */
  227. #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
  228. #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */
  229. #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
  230. #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
  231. #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
  232. #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
  233. #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */
  234. #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */
  235. #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */
  236. #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */
  237. /*
  238. * ISP mailbox commands
  239. */
  240. #define MBC_NOP 0 /* No Operation */
  241. #define MBC_LOAD_RAM 1 /* Load RAM */
  242. #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */
  243. #define MBC_DUMP_RAM 3 /* Dump RAM contents */
  244. #define MBC_WRITE_RAM_WORD 4 /* Write ram word */
  245. #define MBC_READ_RAM_WORD 5 /* Read ram word */
  246. #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
  247. #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */
  248. #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */
  249. #define MBC_LOAD_RAM_A64_ROM 9 /* Load RAM 64bit ROM version */
  250. #define MBC_DUMP_RAM_A64_ROM 0x0a /* Dump RAM 64bit ROM version */
  251. #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */
  252. #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */
  253. #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */
  254. #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */
  255. #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */
  256. #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */
  257. #define MBC_BUS_RESET 0x18 /* SCSI bus reset */
  258. #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */
  259. #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */
  260. #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */
  261. #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */
  262. #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */
  263. #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */
  264. #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */
  265. #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */
  266. #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */
  267. #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */
  268. #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */
  269. #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */
  270. #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */
  271. #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */
  272. #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */
  273. #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */
  274. #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */
  275. #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */
  276. #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */
  277. /*
  278. * ISP Get/Set Target Parameters mailbox command control flags.
  279. */
  280. #define TP_PPR BIT_5 /* PPR */
  281. #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */
  282. #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
  283. #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */
  284. #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */
  285. #define TP_SYNC BIT_12 /* Synchronous data transfers. */
  286. #define TP_WIDE BIT_13 /* Wide data transfers. */
  287. #define TP_PARITY BIT_14 /* Parity checking. */
  288. #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
  289. /*
  290. * NVRAM Command values.
  291. */
  292. #define NV_START_BIT BIT_2
  293. #define NV_WRITE_OP (BIT_26 | BIT_24)
  294. #define NV_READ_OP (BIT_26 | BIT_25)
  295. #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24)
  296. #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24)
  297. #define NV_DELAY_COUNT 10
  298. /*
  299. * QLogic ISP1280/ISP12160 NVRAM structure definition.
  300. */
  301. struct nvram {
  302. uint8_t id0; /* 0 */
  303. uint8_t id1; /* 1 */
  304. uint8_t id2; /* 2 */
  305. uint8_t id3; /* 3 */
  306. uint8_t version; /* 4 */
  307. struct {
  308. uint8_t bios_configuration_mode:2;
  309. uint8_t bios_disable:1;
  310. uint8_t selectable_scsi_boot_enable:1;
  311. uint8_t cd_rom_boot_enable:1;
  312. uint8_t disable_loading_risc_code:1;
  313. uint8_t enable_64bit_addressing:1;
  314. uint8_t unused_7:1;
  315. } cntr_flags_1; /* 5 */
  316. struct {
  317. uint8_t boot_lun_number:5;
  318. uint8_t scsi_bus_number:1;
  319. uint8_t unused_6:1;
  320. uint8_t unused_7:1;
  321. } cntr_flags_2l; /* 7 */
  322. struct {
  323. uint8_t boot_target_number:4;
  324. uint8_t unused_12:1;
  325. uint8_t unused_13:1;
  326. uint8_t unused_14:1;
  327. uint8_t unused_15:1;
  328. } cntr_flags_2h; /* 8 */
  329. uint16_t unused_8; /* 8, 9 */
  330. uint16_t unused_10; /* 10, 11 */
  331. uint16_t unused_12; /* 12, 13 */
  332. uint16_t unused_14; /* 14, 15 */
  333. struct {
  334. uint8_t reserved:2;
  335. uint8_t burst_enable:1;
  336. uint8_t reserved_1:1;
  337. uint8_t fifo_threshold:4;
  338. } isp_config; /* 16 */
  339. /* Termination
  340. * 0 = Disable, 1 = high only, 3 = Auto term
  341. */
  342. struct {
  343. uint8_t scsi_bus_1_control:2;
  344. uint8_t scsi_bus_0_control:2;
  345. uint8_t unused_0:1;
  346. uint8_t unused_1:1;
  347. uint8_t unused_2:1;
  348. uint8_t auto_term_support:1;
  349. } termination; /* 17 */
  350. uint16_t isp_parameter; /* 18, 19 */
  351. union {
  352. uint16_t w;
  353. struct {
  354. uint16_t enable_fast_posting:1;
  355. uint16_t report_lvd_bus_transition:1;
  356. uint16_t unused_2:1;
  357. uint16_t unused_3:1;
  358. uint16_t disable_iosbs_with_bus_reset_status:1;
  359. uint16_t disable_synchronous_backoff:1;
  360. uint16_t unused_6:1;
  361. uint16_t synchronous_backoff_reporting:1;
  362. uint16_t disable_reselection_fairness:1;
  363. uint16_t unused_9:1;
  364. uint16_t unused_10:1;
  365. uint16_t unused_11:1;
  366. uint16_t unused_12:1;
  367. uint16_t unused_13:1;
  368. uint16_t unused_14:1;
  369. uint16_t unused_15:1;
  370. } f;
  371. } firmware_feature; /* 20, 21 */
  372. uint16_t unused_22; /* 22, 23 */
  373. struct {
  374. struct {
  375. uint8_t initiator_id:4;
  376. uint8_t scsi_reset_disable:1;
  377. uint8_t scsi_bus_size:1;
  378. uint8_t scsi_bus_type:1;
  379. uint8_t unused_7:1;
  380. } config_1; /* 24 */
  381. uint8_t bus_reset_delay; /* 25 */
  382. uint8_t retry_count; /* 26 */
  383. uint8_t retry_delay; /* 27 */
  384. struct {
  385. uint8_t async_data_setup_time:4;
  386. uint8_t req_ack_active_negation:1;
  387. uint8_t data_line_active_negation:1;
  388. uint8_t unused_6:1;
  389. uint8_t unused_7:1;
  390. } config_2; /* 28 */
  391. uint8_t unused_29; /* 29 */
  392. uint16_t selection_timeout; /* 30, 31 */
  393. uint16_t max_queue_depth; /* 32, 33 */
  394. uint16_t unused_34; /* 34, 35 */
  395. uint16_t unused_36; /* 36, 37 */
  396. uint16_t unused_38; /* 38, 39 */
  397. struct {
  398. struct {
  399. uint8_t renegotiate_on_error:1;
  400. uint8_t stop_queue_on_check:1;
  401. uint8_t auto_request_sense:1;
  402. uint8_t tag_queuing:1;
  403. uint8_t enable_sync:1;
  404. uint8_t enable_wide:1;
  405. uint8_t parity_checking:1;
  406. uint8_t disconnect_allowed:1;
  407. } parameter; /* 40 */
  408. uint8_t execution_throttle; /* 41 */
  409. uint8_t sync_period; /* 42 */
  410. union { /* 43 */
  411. uint8_t flags_43;
  412. struct {
  413. uint8_t sync_offset:4;
  414. uint8_t device_enable:1;
  415. uint8_t lun_disable:1;
  416. uint8_t unused_6:1;
  417. uint8_t unused_7:1;
  418. } flags1x80;
  419. struct {
  420. uint8_t sync_offset:5;
  421. uint8_t device_enable:1;
  422. uint8_t unused_6:1;
  423. uint8_t unused_7:1;
  424. } flags1x160;
  425. } flags;
  426. union { /* PPR flags for the 1x160 controllers */
  427. uint8_t unused_44;
  428. struct {
  429. uint8_t ppr_options:4;
  430. uint8_t ppr_bus_width:2;
  431. uint8_t unused_8:1;
  432. uint8_t enable_ppr:1;
  433. } flags; /* 44 */
  434. } ppr_1x160;
  435. uint8_t unused_45; /* 45 */
  436. } target[MAX_TARGETS];
  437. } bus[MAX_BUSES];
  438. uint16_t unused_248; /* 248, 249 */
  439. uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
  440. union { /* 254 */
  441. uint8_t unused_254;
  442. uint8_t system_id_pointer;
  443. } sysid_1x160;
  444. uint8_t chksum; /* 255 */
  445. };
  446. /*
  447. * ISP queue - command entry structure definition.
  448. */
  449. #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */
  450. struct cmd_entry {
  451. uint8_t entry_type; /* Entry type. */
  452. #define COMMAND_TYPE 1 /* Command entry */
  453. uint8_t entry_count; /* Entry count. */
  454. uint8_t sys_define; /* System defined. */
  455. uint8_t entry_status; /* Entry Status. */
  456. __le32 handle; /* System handle. */
  457. uint8_t lun; /* SCSI LUN */
  458. uint8_t target; /* SCSI ID */
  459. __le16 cdb_len; /* SCSI command length. */
  460. __le16 control_flags; /* Control flags. */
  461. __le16 reserved;
  462. __le16 timeout; /* Command timeout. */
  463. __le16 dseg_count; /* Data segment count. */
  464. uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
  465. __le32 dseg_0_address; /* Data segment 0 address. */
  466. __le32 dseg_0_length; /* Data segment 0 length. */
  467. __le32 dseg_1_address; /* Data segment 1 address. */
  468. __le32 dseg_1_length; /* Data segment 1 length. */
  469. __le32 dseg_2_address; /* Data segment 2 address. */
  470. __le32 dseg_2_length; /* Data segment 2 length. */
  471. __le32 dseg_3_address; /* Data segment 3 address. */
  472. __le32 dseg_3_length; /* Data segment 3 length. */
  473. };
  474. /*
  475. * ISP queue - continuation entry structure definition.
  476. */
  477. struct cont_entry {
  478. uint8_t entry_type; /* Entry type. */
  479. #define CONTINUE_TYPE 2 /* Continuation entry. */
  480. uint8_t entry_count; /* Entry count. */
  481. uint8_t sys_define; /* System defined. */
  482. uint8_t entry_status; /* Entry Status. */
  483. __le32 reserved; /* Reserved */
  484. __le32 dseg_0_address; /* Data segment 0 address. */
  485. __le32 dseg_0_length; /* Data segment 0 length. */
  486. __le32 dseg_1_address; /* Data segment 1 address. */
  487. __le32 dseg_1_length; /* Data segment 1 length. */
  488. __le32 dseg_2_address; /* Data segment 2 address. */
  489. __le32 dseg_2_length; /* Data segment 2 length. */
  490. __le32 dseg_3_address; /* Data segment 3 address. */
  491. __le32 dseg_3_length; /* Data segment 3 length. */
  492. __le32 dseg_4_address; /* Data segment 4 address. */
  493. __le32 dseg_4_length; /* Data segment 4 length. */
  494. __le32 dseg_5_address; /* Data segment 5 address. */
  495. __le32 dseg_5_length; /* Data segment 5 length. */
  496. __le32 dseg_6_address; /* Data segment 6 address. */
  497. __le32 dseg_6_length; /* Data segment 6 length. */
  498. };
  499. /*
  500. * ISP queue - status entry structure definition.
  501. */
  502. struct response {
  503. uint8_t entry_type; /* Entry type. */
  504. #define STATUS_TYPE 3 /* Status entry. */
  505. uint8_t entry_count; /* Entry count. */
  506. uint8_t sys_define; /* System defined. */
  507. uint8_t entry_status; /* Entry Status. */
  508. #define RF_CONT BIT_0 /* Continuation. */
  509. #define RF_FULL BIT_1 /* Full */
  510. #define RF_BAD_HEADER BIT_2 /* Bad header. */
  511. #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
  512. __le32 handle; /* System handle. */
  513. __le16 scsi_status; /* SCSI status. */
  514. __le16 comp_status; /* Completion status. */
  515. __le16 state_flags; /* State flags. */
  516. #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
  517. #define SF_GOT_SENSE BIT_13 /* Got Sense */
  518. #define SF_GOT_STATUS BIT_12 /* Got Status */
  519. #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
  520. #define SF_SENT_CDB BIT_10 /* Send CDB */
  521. #define SF_GOT_TARGET BIT_9 /* */
  522. #define SF_GOT_BUS BIT_8 /* */
  523. __le16 status_flags; /* Status flags. */
  524. __le16 time; /* Time. */
  525. __le16 req_sense_length;/* Request sense data length. */
  526. __le32 residual_length; /* Residual transfer length. */
  527. __le16 reserved[4];
  528. uint8_t req_sense_data[32]; /* Request sense data. */
  529. };
  530. /*
  531. * ISP queue - marker entry structure definition.
  532. */
  533. struct mrk_entry {
  534. uint8_t entry_type; /* Entry type. */
  535. #define MARKER_TYPE 4 /* Marker entry. */
  536. uint8_t entry_count; /* Entry count. */
  537. uint8_t sys_define; /* System defined. */
  538. uint8_t entry_status; /* Entry Status. */
  539. __le32 reserved;
  540. uint8_t lun; /* SCSI LUN */
  541. uint8_t target; /* SCSI ID */
  542. uint8_t modifier; /* Modifier (7-0). */
  543. #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
  544. #define MK_SYNC_ID 1 /* Synchronize ID */
  545. #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
  546. uint8_t reserved_1[53];
  547. };
  548. /*
  549. * ISP queue - extended command entry structure definition.
  550. *
  551. * Unused by the driver!
  552. */
  553. struct ecmd_entry {
  554. uint8_t entry_type; /* Entry type. */
  555. #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */
  556. uint8_t entry_count; /* Entry count. */
  557. uint8_t sys_define; /* System defined. */
  558. uint8_t entry_status; /* Entry Status. */
  559. uint32_t handle; /* System handle. */
  560. uint8_t lun; /* SCSI LUN */
  561. uint8_t target; /* SCSI ID */
  562. __le16 cdb_len; /* SCSI command length. */
  563. __le16 control_flags; /* Control flags. */
  564. __le16 reserved;
  565. __le16 timeout; /* Command timeout. */
  566. __le16 dseg_count; /* Data segment count. */
  567. uint8_t scsi_cdb[88]; /* SCSI command words. */
  568. };
  569. /*
  570. * ISP queue - 64-Bit addressing, command entry structure definition.
  571. */
  572. typedef struct {
  573. uint8_t entry_type; /* Entry type. */
  574. #define COMMAND_A64_TYPE 9 /* Command A64 entry */
  575. uint8_t entry_count; /* Entry count. */
  576. uint8_t sys_define; /* System defined. */
  577. uint8_t entry_status; /* Entry Status. */
  578. __le32 handle; /* System handle. */
  579. uint8_t lun; /* SCSI LUN */
  580. uint8_t target; /* SCSI ID */
  581. __le16 cdb_len; /* SCSI command length. */
  582. __le16 control_flags; /* Control flags. */
  583. __le16 reserved;
  584. __le16 timeout; /* Command timeout. */
  585. __le16 dseg_count; /* Data segment count. */
  586. uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
  587. __le32 reserved_1[2]; /* unused */
  588. __le32 dseg_0_address[2]; /* Data segment 0 address. */
  589. __le32 dseg_0_length; /* Data segment 0 length. */
  590. __le32 dseg_1_address[2]; /* Data segment 1 address. */
  591. __le32 dseg_1_length; /* Data segment 1 length. */
  592. } cmd_a64_entry_t, request_t;
  593. /*
  594. * ISP queue - 64-Bit addressing, continuation entry structure definition.
  595. */
  596. struct cont_a64_entry {
  597. uint8_t entry_type; /* Entry type. */
  598. #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */
  599. uint8_t entry_count; /* Entry count. */
  600. uint8_t sys_define; /* System defined. */
  601. uint8_t entry_status; /* Entry Status. */
  602. __le32 dseg_0_address[2]; /* Data segment 0 address. */
  603. __le32 dseg_0_length; /* Data segment 0 length. */
  604. __le32 dseg_1_address[2]; /* Data segment 1 address. */
  605. __le32 dseg_1_length; /* Data segment 1 length. */
  606. __le32 dseg_2_address[2]; /* Data segment 2 address. */
  607. __le32 dseg_2_length; /* Data segment 2 length. */
  608. __le32 dseg_3_address[2]; /* Data segment 3 address. */
  609. __le32 dseg_3_length; /* Data segment 3 length. */
  610. __le32 dseg_4_address[2]; /* Data segment 4 address. */
  611. __le32 dseg_4_length; /* Data segment 4 length. */
  612. };
  613. /*
  614. * ISP queue - enable LUN entry structure definition.
  615. */
  616. struct elun_entry {
  617. uint8_t entry_type; /* Entry type. */
  618. #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
  619. uint8_t entry_count; /* Entry count. */
  620. uint8_t reserved_1;
  621. uint8_t entry_status; /* Entry Status not used. */
  622. __le32 reserved_2;
  623. __le16 lun; /* Bit 15 is bus number. */
  624. __le16 reserved_4;
  625. __le32 option_flags;
  626. uint8_t status;
  627. uint8_t reserved_5;
  628. uint8_t command_count; /* Number of ATIOs allocated. */
  629. uint8_t immed_notify_count; /* Number of Immediate Notify */
  630. /* entries allocated. */
  631. uint8_t group_6_length; /* SCSI CDB length for group 6 */
  632. /* commands (2-26). */
  633. uint8_t group_7_length; /* SCSI CDB length for group 7 */
  634. /* commands (2-26). */
  635. __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
  636. __le16 reserved_6[20];
  637. };
  638. /*
  639. * ISP queue - modify LUN entry structure definition.
  640. *
  641. * Unused by the driver!
  642. */
  643. struct modify_lun_entry {
  644. uint8_t entry_type; /* Entry type. */
  645. #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
  646. uint8_t entry_count; /* Entry count. */
  647. uint8_t reserved_1;
  648. uint8_t entry_status; /* Entry Status. */
  649. __le32 reserved_2;
  650. uint8_t lun; /* SCSI LUN */
  651. uint8_t reserved_3;
  652. uint8_t operators;
  653. uint8_t reserved_4;
  654. __le32 option_flags;
  655. uint8_t status;
  656. uint8_t reserved_5;
  657. uint8_t command_count; /* Number of ATIOs allocated. */
  658. uint8_t immed_notify_count; /* Number of Immediate Notify */
  659. /* entries allocated. */
  660. __le16 reserved_6;
  661. __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
  662. __le16 reserved_7[20];
  663. };
  664. /*
  665. * ISP queue - immediate notify entry structure definition.
  666. */
  667. struct notify_entry {
  668. uint8_t entry_type; /* Entry type. */
  669. #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */
  670. uint8_t entry_count; /* Entry count. */
  671. uint8_t reserved_1;
  672. uint8_t entry_status; /* Entry Status. */
  673. __le32 reserved_2;
  674. uint8_t lun;
  675. uint8_t initiator_id;
  676. uint8_t reserved_3;
  677. uint8_t target_id;
  678. __le32 option_flags;
  679. uint8_t status;
  680. uint8_t reserved_4;
  681. uint8_t tag_value; /* Received queue tag message value */
  682. uint8_t tag_type; /* Received queue tag message type */
  683. /* entries allocated. */
  684. __le16 seq_id;
  685. uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */
  686. __le16 reserved_5[8];
  687. uint8_t sense_data[18];
  688. };
  689. /*
  690. * ISP queue - notify acknowledge entry structure definition.
  691. */
  692. struct nack_entry {
  693. uint8_t entry_type; /* Entry type. */
  694. #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
  695. uint8_t entry_count; /* Entry count. */
  696. uint8_t reserved_1;
  697. uint8_t entry_status; /* Entry Status. */
  698. __le32 reserved_2;
  699. uint8_t lun;
  700. uint8_t initiator_id;
  701. uint8_t reserved_3;
  702. uint8_t target_id;
  703. __le32 option_flags;
  704. uint8_t status;
  705. uint8_t event;
  706. __le16 seq_id;
  707. __le16 reserved_4[22];
  708. };
  709. /*
  710. * ISP queue - Accept Target I/O (ATIO) entry structure definition.
  711. */
  712. struct atio_entry {
  713. uint8_t entry_type; /* Entry type. */
  714. #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */
  715. uint8_t entry_count; /* Entry count. */
  716. uint8_t reserved_1;
  717. uint8_t entry_status; /* Entry Status. */
  718. __le32 reserved_2;
  719. uint8_t lun;
  720. uint8_t initiator_id;
  721. uint8_t cdb_len;
  722. uint8_t target_id;
  723. __le32 option_flags;
  724. uint8_t status;
  725. uint8_t scsi_status;
  726. uint8_t tag_value; /* Received queue tag message value */
  727. uint8_t tag_type; /* Received queue tag message type */
  728. uint8_t cdb[26];
  729. uint8_t sense_data[18];
  730. };
  731. /*
  732. * ISP queue - Continue Target I/O (CTIO) entry structure definition.
  733. */
  734. struct ctio_entry {
  735. uint8_t entry_type; /* Entry type. */
  736. #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */
  737. uint8_t entry_count; /* Entry count. */
  738. uint8_t reserved_1;
  739. uint8_t entry_status; /* Entry Status. */
  740. __le32 reserved_2;
  741. uint8_t lun; /* SCSI LUN */
  742. uint8_t initiator_id;
  743. uint8_t reserved_3;
  744. uint8_t target_id;
  745. __le32 option_flags;
  746. uint8_t status;
  747. uint8_t scsi_status;
  748. uint8_t tag_value; /* Received queue tag message value */
  749. uint8_t tag_type; /* Received queue tag message type */
  750. __le32 transfer_length;
  751. __le32 residual;
  752. __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
  753. __le16 dseg_count; /* Data segment count. */
  754. __le32 dseg_0_address; /* Data segment 0 address. */
  755. __le32 dseg_0_length; /* Data segment 0 length. */
  756. __le32 dseg_1_address; /* Data segment 1 address. */
  757. __le32 dseg_1_length; /* Data segment 1 length. */
  758. __le32 dseg_2_address; /* Data segment 2 address. */
  759. __le32 dseg_2_length; /* Data segment 2 length. */
  760. __le32 dseg_3_address; /* Data segment 3 address. */
  761. __le32 dseg_3_length; /* Data segment 3 length. */
  762. };
  763. /*
  764. * ISP queue - CTIO returned entry structure definition.
  765. */
  766. struct ctio_ret_entry {
  767. uint8_t entry_type; /* Entry type. */
  768. #define CTIO_RET_TYPE 7 /* CTIO return entry */
  769. uint8_t entry_count; /* Entry count. */
  770. uint8_t reserved_1;
  771. uint8_t entry_status; /* Entry Status. */
  772. __le32 reserved_2;
  773. uint8_t lun; /* SCSI LUN */
  774. uint8_t initiator_id;
  775. uint8_t reserved_3;
  776. uint8_t target_id;
  777. __le32 option_flags;
  778. uint8_t status;
  779. uint8_t scsi_status;
  780. uint8_t tag_value; /* Received queue tag message value */
  781. uint8_t tag_type; /* Received queue tag message type */
  782. __le32 transfer_length;
  783. __le32 residual;
  784. __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
  785. __le16 dseg_count; /* Data segment count. */
  786. __le32 dseg_0_address; /* Data segment 0 address. */
  787. __le32 dseg_0_length; /* Data segment 0 length. */
  788. __le32 dseg_1_address; /* Data segment 1 address. */
  789. __le16 dseg_1_length; /* Data segment 1 length. */
  790. uint8_t sense_data[18];
  791. };
  792. /*
  793. * ISP queue - CTIO A64 entry structure definition.
  794. */
  795. struct ctio_a64_entry {
  796. uint8_t entry_type; /* Entry type. */
  797. #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */
  798. uint8_t entry_count; /* Entry count. */
  799. uint8_t reserved_1;
  800. uint8_t entry_status; /* Entry Status. */
  801. __le32 reserved_2;
  802. uint8_t lun; /* SCSI LUN */
  803. uint8_t initiator_id;
  804. uint8_t reserved_3;
  805. uint8_t target_id;
  806. __le32 option_flags;
  807. uint8_t status;
  808. uint8_t scsi_status;
  809. uint8_t tag_value; /* Received queue tag message value */
  810. uint8_t tag_type; /* Received queue tag message type */
  811. __le32 transfer_length;
  812. __le32 residual;
  813. __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
  814. __le16 dseg_count; /* Data segment count. */
  815. __le32 reserved_4[2];
  816. __le32 dseg_0_address[2];/* Data segment 0 address. */
  817. __le32 dseg_0_length; /* Data segment 0 length. */
  818. __le32 dseg_1_address[2];/* Data segment 1 address. */
  819. __le32 dseg_1_length; /* Data segment 1 length. */
  820. };
  821. /*
  822. * ISP queue - CTIO returned entry structure definition.
  823. */
  824. struct ctio_a64_ret_entry {
  825. uint8_t entry_type; /* Entry type. */
  826. #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */
  827. uint8_t entry_count; /* Entry count. */
  828. uint8_t reserved_1;
  829. uint8_t entry_status; /* Entry Status. */
  830. __le32 reserved_2;
  831. uint8_t lun; /* SCSI LUN */
  832. uint8_t initiator_id;
  833. uint8_t reserved_3;
  834. uint8_t target_id;
  835. __le32 option_flags;
  836. uint8_t status;
  837. uint8_t scsi_status;
  838. uint8_t tag_value; /* Received queue tag message value */
  839. uint8_t tag_type; /* Received queue tag message type */
  840. __le32 transfer_length;
  841. __le32 residual;
  842. __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
  843. __le16 dseg_count; /* Data segment count. */
  844. __le16 reserved_4[7];
  845. uint8_t sense_data[18];
  846. };
  847. /*
  848. * ISP request and response queue entry sizes
  849. */
  850. #define RESPONSE_ENTRY_SIZE (sizeof(struct response))
  851. #define REQUEST_ENTRY_SIZE (sizeof(request_t))
  852. /*
  853. * ISP status entry - completion status definitions.
  854. */
  855. #define CS_COMPLETE 0x0 /* No errors */
  856. #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
  857. #define CS_DMA 0x2 /* A DMA direction error. */
  858. #define CS_TRANSPORT 0x3 /* Transport error. */
  859. #define CS_RESET 0x4 /* SCSI bus reset occurred */
  860. #define CS_ABORTED 0x5 /* System aborted command. */
  861. #define CS_TIMEOUT 0x6 /* Timeout error. */
  862. #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
  863. #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */
  864. #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */
  865. #define CS_BAD_MSG 0xA /* Bad msg after status phase. */
  866. #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */
  867. #define CS_EXTENDED_ID 0xC /* Extended ID failed. */
  868. #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */
  869. #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */
  870. #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */
  871. #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */
  872. #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */
  873. #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */
  874. #define CS_ID_MSG 0x13 /* Target rejected ID msg. */
  875. #define CS_FREE 0x14 /* Unexpected bus free. */
  876. #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
  877. #define CS_TRANACTION_1 0x18 /* Transaction error 1 */
  878. #define CS_TRANACTION_2 0x19 /* Transaction error 2 */
  879. #define CS_TRANACTION_3 0x1a /* Transaction error 3 */
  880. #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */
  881. #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */
  882. #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */
  883. #define CS_ARS_FAILED 0x1e /* ARS failed */
  884. #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */
  885. #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
  886. #define CS_UNKNOWN 0x81 /* Driver defined */
  887. #define CS_RETRY 0x82 /* Driver defined */
  888. /*
  889. * ISP target entries - Option flags bit definitions.
  890. */
  891. #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
  892. #define OF_DATA_IN BIT_6 /* Data in to initiator */
  893. /* (data from target to initiator) */
  894. #define OF_DATA_OUT BIT_7 /* Data out from initiator */
  895. /* (data from initiator to target) */
  896. #define OF_NO_DATA (BIT_7 | BIT_6)
  897. #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
  898. #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */
  899. #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */
  900. #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */
  901. #define OF_SSTS BIT_31 /* Send SCSI status */
  902. /*
  903. * BUS parameters/settings structure - UNUSED
  904. */
  905. struct bus_param {
  906. uint8_t id; /* Host adapter SCSI id */
  907. uint8_t bus_reset_delay; /* SCSI bus reset delay. */
  908. uint8_t failed_reset_count; /* number of time reset failed */
  909. uint8_t unused;
  910. uint16_t device_enables; /* Device enable bits. */
  911. uint16_t lun_disables; /* LUN disable bits. */
  912. uint16_t qtag_enables; /* Tag queue enables. */
  913. uint16_t hiwat; /* High water mark per device. */
  914. uint8_t reset_marker:1;
  915. uint8_t disable_scsi_reset:1;
  916. uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */
  917. };
  918. struct qla_driver_setup {
  919. uint32_t no_sync:1;
  920. uint32_t no_wide:1;
  921. uint32_t no_ppr:1;
  922. uint32_t no_nvram:1;
  923. uint16_t sync_mask;
  924. uint16_t wide_mask;
  925. uint16_t ppr_mask;
  926. };
  927. /*
  928. * Linux Host Adapter structure
  929. */
  930. struct scsi_qla_host {
  931. /* Linux adapter configuration data */
  932. struct Scsi_Host *host; /* pointer to host data */
  933. struct scsi_qla_host *next;
  934. struct device_reg __iomem *iobase; /* Base Memory-mapped I/O address */
  935. unsigned char __iomem *mmpbase; /* memory mapped address */
  936. unsigned long host_no;
  937. struct pci_dev *pdev;
  938. uint8_t devnum;
  939. uint8_t revision;
  940. uint8_t ports;
  941. unsigned long actthreads;
  942. unsigned long isr_count; /* Interrupt count */
  943. unsigned long spurious_int;
  944. /* Outstandings ISP commands. */
  945. struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
  946. /* BUS configuration data */
  947. struct bus_param bus_settings[MAX_BUSES];
  948. /* Received ISP mailbox data. */
  949. volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
  950. dma_addr_t request_dma; /* Physical Address */
  951. request_t *request_ring; /* Base virtual address */
  952. request_t *request_ring_ptr; /* Current address. */
  953. uint16_t req_ring_index; /* Current index. */
  954. uint16_t req_q_cnt; /* Number of available entries. */
  955. dma_addr_t response_dma; /* Physical address. */
  956. struct response *response_ring; /* Base virtual address */
  957. struct response *response_ring_ptr; /* Current address. */
  958. uint16_t rsp_ring_index; /* Current index. */
  959. struct list_head done_q; /* Done queue */
  960. struct completion *mailbox_wait;
  961. struct timer_list mailbox_timer;
  962. volatile struct {
  963. uint32_t online:1; /* 0 */
  964. uint32_t reset_marker:1; /* 1 */
  965. uint32_t disable_host_adapter:1; /* 2 */
  966. uint32_t reset_active:1; /* 3 */
  967. uint32_t abort_isp_active:1; /* 4 */
  968. uint32_t disable_risc_code_load:1; /* 5 */
  969. } flags;
  970. struct nvram nvram;
  971. int nvram_valid;
  972. /* Firmware Info */
  973. unsigned short fwstart; /* start address for F/W */
  974. unsigned char fwver1; /* F/W version first char */
  975. unsigned char fwver2; /* F/W version second char */
  976. unsigned char fwver3; /* F/W version third char */
  977. };
  978. #endif /* _QLA1280_H */