pm80xx_hwi.c 162 KB

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  1. /*
  2. * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
  3. *
  4. * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. */
  40. #include <linux/slab.h>
  41. #include "pm8001_sas.h"
  42. #include "pm80xx_hwi.h"
  43. #include "pm8001_chips.h"
  44. #include "pm8001_ctl.h"
  45. #define SMP_DIRECT 1
  46. #define SMP_INDIRECT 2
  47. int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  48. {
  49. u32 reg_val;
  50. unsigned long start;
  51. pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  52. /* confirm the setting is written */
  53. start = jiffies + HZ; /* 1 sec */
  54. do {
  55. reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  56. } while ((reg_val != shift_value) && time_before(jiffies, start));
  57. if (reg_val != shift_value) {
  58. pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
  59. reg_val);
  60. return -1;
  61. }
  62. return 0;
  63. }
  64. static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
  65. __le32 *destination,
  66. u32 dw_count, u32 bus_base_number)
  67. {
  68. u32 index, value, offset;
  69. for (index = 0; index < dw_count; index += 4, destination++) {
  70. offset = (soffset + index);
  71. if (offset < (64 * 1024)) {
  72. value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  73. *destination = cpu_to_le32(value);
  74. }
  75. }
  76. return;
  77. }
  78. ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  79. struct device_attribute *attr, char *buf)
  80. {
  81. struct Scsi_Host *shost = class_to_shost(cdev);
  82. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  83. struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  84. void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  85. u32 accum_len , reg_val, index, *temp;
  86. u32 status = 1;
  87. unsigned long start;
  88. u8 *direct_data;
  89. char *fatal_error_data = buf;
  90. u32 length_to_read;
  91. u32 offset;
  92. pm8001_ha->forensic_info.data_buf.direct_data = buf;
  93. if (pm8001_ha->chip_id == chip_8001) {
  94. pm8001_ha->forensic_info.data_buf.direct_data +=
  95. sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
  96. "Not supported for SPC controller");
  97. return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
  98. (char *)buf;
  99. }
  100. /* initialize variables for very first call from host application */
  101. if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
  102. pm8001_dbg(pm8001_ha, IO,
  103. "forensic_info TYPE_NON_FATAL..............\n");
  104. direct_data = (u8 *)fatal_error_data;
  105. pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
  106. pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
  107. pm8001_ha->forensic_info.data_buf.direct_offset = 0;
  108. pm8001_ha->forensic_info.data_buf.read_len = 0;
  109. pm8001_ha->forensic_preserved_accumulated_transfer = 0;
  110. /* Write signature to fatal dump table */
  111. pm8001_mw32(fatal_table_address,
  112. MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
  113. pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
  114. pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
  115. pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
  116. pm8001_ha->forensic_info.data_buf.read_len);
  117. pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
  118. pm8001_ha->forensic_info.data_buf.direct_len);
  119. pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
  120. pm8001_ha->forensic_info.data_buf.direct_offset);
  121. }
  122. if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
  123. /* start to get data */
  124. /* Program the MEMBASE II Shifting Register with 0x00.*/
  125. pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
  126. pm8001_ha->fatal_forensic_shift_offset);
  127. pm8001_ha->forensic_last_offset = 0;
  128. pm8001_ha->forensic_fatal_step = 0;
  129. pm8001_ha->fatal_bar_loc = 0;
  130. }
  131. /* Read until accum_len is retrived */
  132. accum_len = pm8001_mr32(fatal_table_address,
  133. MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
  134. /* Determine length of data between previously stored transfer length
  135. * and current accumulated transfer length
  136. */
  137. length_to_read =
  138. accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
  139. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
  140. accum_len);
  141. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
  142. length_to_read);
  143. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
  144. pm8001_ha->forensic_last_offset);
  145. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
  146. pm8001_ha->forensic_info.data_buf.read_len);
  147. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
  148. pm8001_ha->forensic_info.data_buf.direct_len);
  149. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
  150. pm8001_ha->forensic_info.data_buf.direct_offset);
  151. /* If accumulated length failed to read correctly fail the attempt.*/
  152. if (accum_len == 0xFFFFFFFF) {
  153. pm8001_dbg(pm8001_ha, IO,
  154. "Possible PCI issue 0x%x not expected\n",
  155. accum_len);
  156. return status;
  157. }
  158. /* If accumulated length is zero fail the attempt */
  159. if (accum_len == 0) {
  160. pm8001_ha->forensic_info.data_buf.direct_data +=
  161. sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
  162. "%08x ", 0xFFFFFFFF);
  163. return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
  164. (char *)buf;
  165. }
  166. /* Accumulated length is good so start capturing the first data */
  167. temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
  168. if (pm8001_ha->forensic_fatal_step == 0) {
  169. moreData:
  170. /* If data to read is less than SYSFS_OFFSET then reduce the
  171. * length of dataLen
  172. */
  173. if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
  174. > length_to_read) {
  175. pm8001_ha->forensic_info.data_buf.direct_len =
  176. length_to_read -
  177. pm8001_ha->forensic_last_offset;
  178. } else {
  179. pm8001_ha->forensic_info.data_buf.direct_len =
  180. SYSFS_OFFSET;
  181. }
  182. if (pm8001_ha->forensic_info.data_buf.direct_data) {
  183. /* Data is in bar, copy to host memory */
  184. pm80xx_pci_mem_copy(pm8001_ha,
  185. pm8001_ha->fatal_bar_loc,
  186. pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
  187. pm8001_ha->forensic_info.data_buf.direct_len, 1);
  188. }
  189. pm8001_ha->fatal_bar_loc +=
  190. pm8001_ha->forensic_info.data_buf.direct_len;
  191. pm8001_ha->forensic_info.data_buf.direct_offset +=
  192. pm8001_ha->forensic_info.data_buf.direct_len;
  193. pm8001_ha->forensic_last_offset +=
  194. pm8001_ha->forensic_info.data_buf.direct_len;
  195. pm8001_ha->forensic_info.data_buf.read_len =
  196. pm8001_ha->forensic_info.data_buf.direct_len;
  197. if (pm8001_ha->forensic_last_offset >= length_to_read) {
  198. pm8001_ha->forensic_info.data_buf.direct_data +=
  199. sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
  200. "%08x ", 3);
  201. for (index = 0; index <
  202. (pm8001_ha->forensic_info.data_buf.direct_len
  203. / 4); index++) {
  204. pm8001_ha->forensic_info.data_buf.direct_data +=
  205. sprintf(
  206. pm8001_ha->forensic_info.data_buf.direct_data,
  207. "%08x ", *(temp + index));
  208. }
  209. pm8001_ha->fatal_bar_loc = 0;
  210. pm8001_ha->forensic_fatal_step = 1;
  211. pm8001_ha->fatal_forensic_shift_offset = 0;
  212. pm8001_ha->forensic_last_offset = 0;
  213. status = 0;
  214. offset = (int)
  215. ((char *)pm8001_ha->forensic_info.data_buf.direct_data
  216. - (char *)buf);
  217. pm8001_dbg(pm8001_ha, IO,
  218. "get_fatal_spcv:return1 0x%x\n", offset);
  219. return (char *)pm8001_ha->
  220. forensic_info.data_buf.direct_data -
  221. (char *)buf;
  222. }
  223. if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
  224. pm8001_ha->forensic_info.data_buf.direct_data +=
  225. sprintf(pm8001_ha->
  226. forensic_info.data_buf.direct_data,
  227. "%08x ", 2);
  228. for (index = 0; index <
  229. (pm8001_ha->forensic_info.data_buf.direct_len
  230. / 4); index++) {
  231. pm8001_ha->forensic_info.data_buf.direct_data
  232. += sprintf(pm8001_ha->
  233. forensic_info.data_buf.direct_data,
  234. "%08x ", *(temp + index));
  235. }
  236. status = 0;
  237. offset = (int)
  238. ((char *)pm8001_ha->forensic_info.data_buf.direct_data
  239. - (char *)buf);
  240. pm8001_dbg(pm8001_ha, IO,
  241. "get_fatal_spcv:return2 0x%x\n", offset);
  242. return (char *)pm8001_ha->
  243. forensic_info.data_buf.direct_data -
  244. (char *)buf;
  245. }
  246. /* Increment the MEMBASE II Shifting Register value by 0x100.*/
  247. pm8001_ha->forensic_info.data_buf.direct_data +=
  248. sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
  249. "%08x ", 2);
  250. for (index = 0; index <
  251. (pm8001_ha->forensic_info.data_buf.direct_len
  252. / 4) ; index++) {
  253. pm8001_ha->forensic_info.data_buf.direct_data +=
  254. sprintf(pm8001_ha->
  255. forensic_info.data_buf.direct_data,
  256. "%08x ", *(temp + index));
  257. }
  258. pm8001_ha->fatal_forensic_shift_offset += 0x100;
  259. pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
  260. pm8001_ha->fatal_forensic_shift_offset);
  261. pm8001_ha->fatal_bar_loc = 0;
  262. status = 0;
  263. offset = (int)
  264. ((char *)pm8001_ha->forensic_info.data_buf.direct_data
  265. - (char *)buf);
  266. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
  267. offset);
  268. return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
  269. (char *)buf;
  270. }
  271. if (pm8001_ha->forensic_fatal_step == 1) {
  272. /* store previous accumulated length before triggering next
  273. * accumulated length update
  274. */
  275. pm8001_ha->forensic_preserved_accumulated_transfer =
  276. pm8001_mr32(fatal_table_address,
  277. MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
  278. /* continue capturing the fatal log until Dump status is 0x3 */
  279. if (pm8001_mr32(fatal_table_address,
  280. MPI_FATAL_EDUMP_TABLE_STATUS) <
  281. MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
  282. /* reset fddstat bit by writing to zero*/
  283. pm8001_mw32(fatal_table_address,
  284. MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
  285. /* set dump control value to '1' so that new data will
  286. * be transferred to shared memory
  287. */
  288. pm8001_mw32(fatal_table_address,
  289. MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
  290. MPI_FATAL_EDUMP_HANDSHAKE_RDY);
  291. /*Poll FDDHSHK until clear */
  292. start = jiffies + (2 * HZ); /* 2 sec */
  293. do {
  294. reg_val = pm8001_mr32(fatal_table_address,
  295. MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
  296. } while ((reg_val) && time_before(jiffies, start));
  297. if (reg_val != 0) {
  298. pm8001_dbg(pm8001_ha, FAIL,
  299. "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
  300. reg_val);
  301. /* Fail the dump if a timeout occurs */
  302. pm8001_ha->forensic_info.data_buf.direct_data +=
  303. sprintf(
  304. pm8001_ha->forensic_info.data_buf.direct_data,
  305. "%08x ", 0xFFFFFFFF);
  306. return((char *)
  307. pm8001_ha->forensic_info.data_buf.direct_data
  308. - (char *)buf);
  309. }
  310. /* Poll status register until set to 2 or
  311. * 3 for up to 2 seconds
  312. */
  313. start = jiffies + (2 * HZ); /* 2 sec */
  314. do {
  315. reg_val = pm8001_mr32(fatal_table_address,
  316. MPI_FATAL_EDUMP_TABLE_STATUS);
  317. } while (((reg_val != 2) && (reg_val != 3)) &&
  318. time_before(jiffies, start));
  319. if (reg_val < 2) {
  320. pm8001_dbg(pm8001_ha, FAIL,
  321. "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
  322. reg_val);
  323. /* Fail the dump if a timeout occurs */
  324. pm8001_ha->forensic_info.data_buf.direct_data +=
  325. sprintf(
  326. pm8001_ha->forensic_info.data_buf.direct_data,
  327. "%08x ", 0xFFFFFFFF);
  328. pm8001_cw32(pm8001_ha, 0,
  329. MEMBASE_II_SHIFT_REGISTER,
  330. pm8001_ha->fatal_forensic_shift_offset);
  331. }
  332. /* Read the next block of the debug data.*/
  333. length_to_read = pm8001_mr32(fatal_table_address,
  334. MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
  335. pm8001_ha->forensic_preserved_accumulated_transfer;
  336. if (length_to_read != 0x0) {
  337. pm8001_ha->forensic_fatal_step = 0;
  338. goto moreData;
  339. } else {
  340. pm8001_ha->forensic_info.data_buf.direct_data +=
  341. sprintf(
  342. pm8001_ha->forensic_info.data_buf.direct_data,
  343. "%08x ", 4);
  344. pm8001_ha->forensic_info.data_buf.read_len
  345. = 0xFFFFFFFF;
  346. pm8001_ha->forensic_info.data_buf.direct_len
  347. = 0;
  348. pm8001_ha->forensic_info.data_buf.direct_offset
  349. = 0;
  350. pm8001_ha->forensic_info.data_buf.read_len = 0;
  351. }
  352. }
  353. }
  354. offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
  355. - (char *)buf);
  356. pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
  357. return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
  358. (char *)buf;
  359. }
  360. /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
  361. * location by the firmware.
  362. */
  363. ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
  364. struct device_attribute *attr, char *buf)
  365. {
  366. struct Scsi_Host *shost = class_to_shost(cdev);
  367. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  368. struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  369. void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
  370. u32 accum_len = 0;
  371. u32 total_len = 0;
  372. u32 reg_val = 0;
  373. u32 *temp = NULL;
  374. u32 index = 0;
  375. u32 output_length;
  376. unsigned long start = 0;
  377. char *buf_copy = buf;
  378. temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
  379. if (++pm8001_ha->non_fatal_count == 1) {
  380. if (pm8001_ha->chip_id == chip_8001) {
  381. snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
  382. PAGE_SIZE, "Not supported for SPC controller");
  383. return 0;
  384. }
  385. pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
  386. /*
  387. * Step 1: Write the host buffer parameters in the MPI Fatal and
  388. * Non-Fatal Error Dump Capture Table.This is the buffer
  389. * where debug data will be DMAed to.
  390. */
  391. pm8001_mw32(nonfatal_table_address,
  392. MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
  393. pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
  394. pm8001_mw32(nonfatal_table_address,
  395. MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
  396. pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
  397. pm8001_mw32(nonfatal_table_address,
  398. MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
  399. /* Optionally, set the DUMPCTRL bit to 1 if the host
  400. * keeps sending active I/Os while capturing the non-fatal
  401. * debug data. Otherwise, leave this bit set to zero
  402. */
  403. pm8001_mw32(nonfatal_table_address,
  404. MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
  405. /*
  406. * Step 2: Clear Accumulative Length of Debug Data Transferred
  407. * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
  408. * Capture Table to zero.
  409. */
  410. pm8001_mw32(nonfatal_table_address,
  411. MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
  412. /* initiallize previous accumulated length to 0 */
  413. pm8001_ha->forensic_preserved_accumulated_transfer = 0;
  414. pm8001_ha->non_fatal_read_length = 0;
  415. }
  416. total_len = pm8001_mr32(nonfatal_table_address,
  417. MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
  418. /*
  419. * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
  420. * field and then request that the SPCv controller transfer the debug
  421. * data by setting bit 7 of the Inbound Doorbell Set Register.
  422. */
  423. pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
  424. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
  425. SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
  426. /*
  427. * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
  428. * 2 seconds) until register bit 7 is cleared.
  429. * This step only indicates the request is accepted by the controller.
  430. */
  431. start = jiffies + (2 * HZ); /* 2 sec */
  432. do {
  433. reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
  434. SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
  435. } while ((reg_val != 0) && time_before(jiffies, start));
  436. /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
  437. * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
  438. * the MPI Fatal and Non-Fatal Error Dump Capture Table.
  439. */
  440. start = jiffies + (2 * HZ); /* 2 sec */
  441. do {
  442. reg_val = pm8001_mr32(nonfatal_table_address,
  443. MPI_FATAL_EDUMP_TABLE_STATUS);
  444. } while ((!reg_val) && time_before(jiffies, start));
  445. if ((reg_val == 0x00) ||
  446. (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
  447. (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
  448. pm8001_ha->non_fatal_read_length = 0;
  449. buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
  450. pm8001_ha->non_fatal_count = 0;
  451. return (buf_copy - buf);
  452. } else if (reg_val ==
  453. MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
  454. buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
  455. } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
  456. (pm8001_ha->non_fatal_read_length >= total_len)) {
  457. pm8001_ha->non_fatal_read_length = 0;
  458. buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
  459. pm8001_ha->non_fatal_count = 0;
  460. }
  461. accum_len = pm8001_mr32(nonfatal_table_address,
  462. MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
  463. output_length = accum_len -
  464. pm8001_ha->forensic_preserved_accumulated_transfer;
  465. for (index = 0; index < output_length/4; index++)
  466. buf_copy += snprintf(buf_copy, PAGE_SIZE,
  467. "%08x ", *(temp+index));
  468. pm8001_ha->non_fatal_read_length += output_length;
  469. /* store current accumulated length to use in next iteration as
  470. * the previous accumulated length
  471. */
  472. pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
  473. return (buf_copy - buf);
  474. }
  475. /**
  476. * read_main_config_table - read the configure table and save it.
  477. * @pm8001_ha: our hba card information
  478. */
  479. static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  480. {
  481. void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  482. pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
  483. pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
  484. pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
  485. pm8001_mr32(address, MAIN_INTERFACE_REVISION);
  486. pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
  487. pm8001_mr32(address, MAIN_FW_REVISION);
  488. pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
  489. pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
  490. pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
  491. pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
  492. pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
  493. pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
  494. pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
  495. pm8001_mr32(address, MAIN_GST_OFFSET);
  496. pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
  497. pm8001_mr32(address, MAIN_IBQ_OFFSET);
  498. pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
  499. pm8001_mr32(address, MAIN_OBQ_OFFSET);
  500. /* read Error Dump Offset and Length */
  501. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
  502. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  503. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
  504. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  505. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
  506. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  507. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
  508. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  509. /* read GPIO LED settings from the configuration table */
  510. pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
  511. pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
  512. /* read analog Setting offset from the configuration table */
  513. pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
  514. pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  515. pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
  516. pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
  517. pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
  518. pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
  519. /* read port recover and reset timeout */
  520. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
  521. pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
  522. /* read ILA and inactive firmware version */
  523. pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
  524. pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
  525. pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
  526. pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
  527. pm8001_dbg(pm8001_ha, DEV,
  528. "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
  529. pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
  530. pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
  531. pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
  532. pm8001_dbg(pm8001_ha, DEV,
  533. "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
  534. pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
  535. pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
  536. pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
  537. pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
  538. pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
  539. pm8001_dbg(pm8001_ha, DEV,
  540. "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
  541. pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
  542. pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
  543. }
  544. /**
  545. * read_general_status_table - read the general status table and save it.
  546. * @pm8001_ha: our hba card information
  547. */
  548. static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  549. {
  550. void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  551. pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
  552. pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
  553. pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
  554. pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
  555. pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
  556. pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
  557. pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
  558. pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
  559. pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
  560. pm8001_mr32(address, GST_IOPTCNT_OFFSET);
  561. pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
  562. pm8001_mr32(address, GST_GPIO_INPUT_VAL);
  563. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
  564. pm8001_mr32(address, GST_RERRINFO_OFFSET0);
  565. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
  566. pm8001_mr32(address, GST_RERRINFO_OFFSET1);
  567. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
  568. pm8001_mr32(address, GST_RERRINFO_OFFSET2);
  569. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
  570. pm8001_mr32(address, GST_RERRINFO_OFFSET3);
  571. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
  572. pm8001_mr32(address, GST_RERRINFO_OFFSET4);
  573. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
  574. pm8001_mr32(address, GST_RERRINFO_OFFSET5);
  575. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
  576. pm8001_mr32(address, GST_RERRINFO_OFFSET6);
  577. pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
  578. pm8001_mr32(address, GST_RERRINFO_OFFSET7);
  579. }
  580. /**
  581. * read_phy_attr_table - read the phy attribute table and save it.
  582. * @pm8001_ha: our hba card information
  583. */
  584. static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
  585. {
  586. void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
  587. pm8001_ha->phy_attr_table.phystart1_16[0] =
  588. pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
  589. pm8001_ha->phy_attr_table.phystart1_16[1] =
  590. pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
  591. pm8001_ha->phy_attr_table.phystart1_16[2] =
  592. pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
  593. pm8001_ha->phy_attr_table.phystart1_16[3] =
  594. pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
  595. pm8001_ha->phy_attr_table.phystart1_16[4] =
  596. pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
  597. pm8001_ha->phy_attr_table.phystart1_16[5] =
  598. pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
  599. pm8001_ha->phy_attr_table.phystart1_16[6] =
  600. pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
  601. pm8001_ha->phy_attr_table.phystart1_16[7] =
  602. pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
  603. pm8001_ha->phy_attr_table.phystart1_16[8] =
  604. pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
  605. pm8001_ha->phy_attr_table.phystart1_16[9] =
  606. pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
  607. pm8001_ha->phy_attr_table.phystart1_16[10] =
  608. pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
  609. pm8001_ha->phy_attr_table.phystart1_16[11] =
  610. pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
  611. pm8001_ha->phy_attr_table.phystart1_16[12] =
  612. pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
  613. pm8001_ha->phy_attr_table.phystart1_16[13] =
  614. pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
  615. pm8001_ha->phy_attr_table.phystart1_16[14] =
  616. pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
  617. pm8001_ha->phy_attr_table.phystart1_16[15] =
  618. pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
  619. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
  620. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
  621. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
  622. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
  623. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
  624. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
  625. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
  626. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
  627. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
  628. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
  629. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
  630. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
  631. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
  632. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
  633. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
  634. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
  635. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
  636. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
  637. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
  638. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
  639. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
  640. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
  641. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
  642. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
  643. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
  644. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
  645. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
  646. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
  647. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
  648. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
  649. pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
  650. pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
  651. }
  652. /**
  653. * read_inbnd_queue_table - read the inbound queue table and save it.
  654. * @pm8001_ha: our hba card information
  655. */
  656. static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
  657. {
  658. int i;
  659. void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
  660. for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
  661. u32 offset = i * 0x20;
  662. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
  663. get_pci_bar_index(pm8001_mr32(address,
  664. (offset + IB_PIPCI_BAR)));
  665. pm8001_ha->inbnd_q_tbl[i].pi_offset =
  666. pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
  667. }
  668. }
  669. /**
  670. * read_outbnd_queue_table - read the outbound queue table and save it.
  671. * @pm8001_ha: our hba card information
  672. */
  673. static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
  674. {
  675. int i;
  676. void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
  677. for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
  678. u32 offset = i * 0x24;
  679. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
  680. get_pci_bar_index(pm8001_mr32(address,
  681. (offset + OB_CIPCI_BAR)));
  682. pm8001_ha->outbnd_q_tbl[i].ci_offset =
  683. pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
  684. }
  685. }
  686. /**
  687. * init_default_table_values - init the default table.
  688. * @pm8001_ha: our hba card information
  689. */
  690. static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
  691. {
  692. int i;
  693. u32 offsetib, offsetob;
  694. void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
  695. void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
  696. u32 ib_offset = pm8001_ha->ib_offset;
  697. u32 ob_offset = pm8001_ha->ob_offset;
  698. u32 ci_offset = pm8001_ha->ci_offset;
  699. u32 pi_offset = pm8001_ha->pi_offset;
  700. pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
  701. pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
  702. pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
  703. pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
  704. pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
  705. PM8001_EVENT_LOG_SIZE;
  706. pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
  707. pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
  708. pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
  709. pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
  710. pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
  711. pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
  712. PM8001_EVENT_LOG_SIZE;
  713. pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
  714. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
  715. /* Enable higher IQs and OQs, 32 to 63, bit 16 */
  716. if (pm8001_ha->max_q_num > 32)
  717. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
  718. 1 << 16;
  719. /* Disable end to end CRC checking */
  720. pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
  721. for (i = 0; i < pm8001_ha->max_q_num; i++) {
  722. pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
  723. PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
  724. pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
  725. pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
  726. pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
  727. pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
  728. pm8001_ha->inbnd_q_tbl[i].base_virt =
  729. (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
  730. pm8001_ha->inbnd_q_tbl[i].total_length =
  731. pm8001_ha->memoryMap.region[ib_offset + i].total_len;
  732. pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
  733. pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
  734. pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
  735. pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
  736. pm8001_ha->inbnd_q_tbl[i].ci_virt =
  737. pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
  738. offsetib = i * 0x20;
  739. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
  740. get_pci_bar_index(pm8001_mr32(addressib,
  741. (offsetib + 0x14)));
  742. pm8001_ha->inbnd_q_tbl[i].pi_offset =
  743. pm8001_mr32(addressib, (offsetib + 0x18));
  744. pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
  745. pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
  746. pm8001_dbg(pm8001_ha, DEV,
  747. "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
  748. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
  749. pm8001_ha->inbnd_q_tbl[i].pi_offset);
  750. }
  751. for (i = 0; i < pm8001_ha->max_q_num; i++) {
  752. pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
  753. PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
  754. pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
  755. pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
  756. pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
  757. pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
  758. pm8001_ha->outbnd_q_tbl[i].base_virt =
  759. (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
  760. pm8001_ha->outbnd_q_tbl[i].total_length =
  761. pm8001_ha->memoryMap.region[ob_offset + i].total_len;
  762. pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
  763. pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
  764. pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
  765. pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
  766. /* interrupt vector based on oq */
  767. pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
  768. pm8001_ha->outbnd_q_tbl[i].pi_virt =
  769. pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
  770. offsetob = i * 0x24;
  771. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
  772. get_pci_bar_index(pm8001_mr32(addressob,
  773. offsetob + 0x14));
  774. pm8001_ha->outbnd_q_tbl[i].ci_offset =
  775. pm8001_mr32(addressob, (offsetob + 0x18));
  776. pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
  777. pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
  778. pm8001_dbg(pm8001_ha, DEV,
  779. "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
  780. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
  781. pm8001_ha->outbnd_q_tbl[i].ci_offset);
  782. }
  783. }
  784. /**
  785. * update_main_config_table - update the main default table to the HBA.
  786. * @pm8001_ha: our hba card information
  787. */
  788. static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
  789. {
  790. void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  791. pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
  792. pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
  793. pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
  794. pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
  795. pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
  796. pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
  797. pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
  798. pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
  799. pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
  800. pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
  801. pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
  802. pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
  803. pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
  804. pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
  805. pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
  806. pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
  807. pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
  808. pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
  809. /* Update Fatal error interrupt vector */
  810. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
  811. ((pm8001_ha->max_q_num - 1) << 8);
  812. pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
  813. pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
  814. pm8001_dbg(pm8001_ha, DEV,
  815. "Updated Fatal error interrupt vector 0x%x\n",
  816. pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
  817. pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
  818. pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
  819. /* SPCv specific */
  820. pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
  821. /* Set GPIOLED to 0x2 for LED indicator */
  822. pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
  823. pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
  824. pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
  825. pm8001_dbg(pm8001_ha, DEV,
  826. "Programming DW 0x21 in main cfg table with 0x%x\n",
  827. pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
  828. pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
  829. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
  830. pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
  831. pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
  832. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
  833. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
  834. PORT_RECOVERY_TIMEOUT;
  835. if (pm8001_ha->chip_id == chip_8006) {
  836. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
  837. 0x0000ffff;
  838. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
  839. CHIP_8006_PORT_RECOVERY_TIMEOUT;
  840. }
  841. pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
  842. pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
  843. }
  844. /**
  845. * update_inbnd_queue_table - update the inbound queue table to the HBA.
  846. * @pm8001_ha: our hba card information
  847. * @number: entry in the queue
  848. */
  849. static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
  850. int number)
  851. {
  852. void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
  853. u16 offset = number * 0x20;
  854. pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
  855. pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
  856. pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
  857. pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
  858. pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
  859. pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
  860. pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
  861. pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
  862. pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
  863. pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
  864. pm8001_dbg(pm8001_ha, DEV,
  865. "IQ %d: Element pri size 0x%x\n",
  866. number,
  867. pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
  868. pm8001_dbg(pm8001_ha, DEV,
  869. "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
  870. pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
  871. pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
  872. pm8001_dbg(pm8001_ha, DEV,
  873. "CI upper base addr 0x%x CI lower base addr 0x%x\n",
  874. pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
  875. pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
  876. }
  877. /**
  878. * update_outbnd_queue_table - update the outbound queue table to the HBA.
  879. * @pm8001_ha: our hba card information
  880. * @number: entry in the queue
  881. */
  882. static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
  883. int number)
  884. {
  885. void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
  886. u16 offset = number * 0x24;
  887. pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
  888. pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
  889. pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
  890. pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
  891. pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
  892. pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
  893. pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
  894. pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
  895. pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
  896. pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
  897. pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
  898. pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
  899. pm8001_dbg(pm8001_ha, DEV,
  900. "OQ %d: Element pri size 0x%x\n",
  901. number,
  902. pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
  903. pm8001_dbg(pm8001_ha, DEV,
  904. "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
  905. pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
  906. pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
  907. pm8001_dbg(pm8001_ha, DEV,
  908. "PI upper base addr 0x%x PI lower base addr 0x%x\n",
  909. pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
  910. pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
  911. }
  912. /**
  913. * mpi_init_check - check firmware initialization status.
  914. * @pm8001_ha: our hba card information
  915. */
  916. static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
  917. {
  918. u32 max_wait_count;
  919. u32 value;
  920. u32 gst_len_mpistate;
  921. /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
  922. table is updated */
  923. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
  924. /* wait until Inbound DoorBell Clear Register toggled */
  925. if (IS_SPCV_12G(pm8001_ha->pdev)) {
  926. max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
  927. } else {
  928. max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
  929. }
  930. do {
  931. udelay(1);
  932. value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
  933. value &= SPCv_MSGU_CFG_TABLE_UPDATE;
  934. } while ((value != 0) && (--max_wait_count));
  935. if (!max_wait_count) {
  936. /* additional check */
  937. pm8001_dbg(pm8001_ha, FAIL,
  938. "Inb doorbell clear not toggled[value:%x]\n",
  939. value);
  940. return -EBUSY;
  941. }
  942. /* check the MPI-State for initialization upto 100ms*/
  943. max_wait_count = 100 * 1000;/* 100 msec */
  944. do {
  945. udelay(1);
  946. gst_len_mpistate =
  947. pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
  948. GST_GSTLEN_MPIS_OFFSET);
  949. } while ((GST_MPI_STATE_INIT !=
  950. (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
  951. if (!max_wait_count)
  952. return -EBUSY;
  953. /* check MPI Initialization error */
  954. gst_len_mpistate = gst_len_mpistate >> 16;
  955. if (0x0000 != gst_len_mpistate)
  956. return -EBUSY;
  957. /*
  958. * As per controller datasheet, after successful MPI
  959. * initialization minimum 500ms delay is required before
  960. * issuing commands.
  961. */
  962. msleep(500);
  963. return 0;
  964. }
  965. /**
  966. * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
  967. * @pm8001_ha: our hba card information
  968. */
  969. static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
  970. {
  971. u32 value;
  972. u32 max_wait_count;
  973. u32 max_wait_time;
  974. int ret = 0;
  975. /* reset / PCIe ready */
  976. max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
  977. do {
  978. udelay(1);
  979. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  980. } while ((value == 0xFFFFFFFF) && (--max_wait_count));
  981. /* check ila status */
  982. max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
  983. do {
  984. udelay(1);
  985. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  986. } while (((value & SCRATCH_PAD_ILA_READY) !=
  987. SCRATCH_PAD_ILA_READY) && (--max_wait_count));
  988. if (!max_wait_count)
  989. ret = -1;
  990. else {
  991. pm8001_dbg(pm8001_ha, MSG,
  992. " ila ready status in %d millisec\n",
  993. (max_wait_time - max_wait_count));
  994. }
  995. /* check RAAE status */
  996. max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
  997. do {
  998. udelay(1);
  999. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  1000. } while (((value & SCRATCH_PAD_RAAE_READY) !=
  1001. SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
  1002. if (!max_wait_count)
  1003. ret = -1;
  1004. else {
  1005. pm8001_dbg(pm8001_ha, MSG,
  1006. " raae ready status in %d millisec\n",
  1007. (max_wait_time - max_wait_count));
  1008. }
  1009. /* check iop0 status */
  1010. max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
  1011. do {
  1012. udelay(1);
  1013. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  1014. } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
  1015. (--max_wait_count));
  1016. if (!max_wait_count)
  1017. ret = -1;
  1018. else {
  1019. pm8001_dbg(pm8001_ha, MSG,
  1020. " iop0 ready status in %d millisec\n",
  1021. (max_wait_time - max_wait_count));
  1022. }
  1023. /* check iop1 status only for 16 port controllers */
  1024. if ((pm8001_ha->chip_id != chip_8008) &&
  1025. (pm8001_ha->chip_id != chip_8009)) {
  1026. /* 200 milli sec */
  1027. max_wait_time = max_wait_count = 200 * 1000;
  1028. do {
  1029. udelay(1);
  1030. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  1031. } while (((value & SCRATCH_PAD_IOP1_READY) !=
  1032. SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
  1033. if (!max_wait_count)
  1034. ret = -1;
  1035. else {
  1036. pm8001_dbg(pm8001_ha, MSG,
  1037. "iop1 ready status in %d millisec\n",
  1038. (max_wait_time - max_wait_count));
  1039. }
  1040. }
  1041. return ret;
  1042. }
  1043. static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
  1044. {
  1045. void __iomem *base_addr;
  1046. u32 value;
  1047. u32 offset;
  1048. u32 pcibar;
  1049. u32 pcilogic;
  1050. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
  1051. offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
  1052. pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
  1053. offset, value);
  1054. pcilogic = (value & 0xFC000000) >> 26;
  1055. pcibar = get_pci_bar_index(pcilogic);
  1056. pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
  1057. pm8001_ha->main_cfg_tbl_addr = base_addr =
  1058. pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
  1059. pm8001_ha->general_stat_tbl_addr =
  1060. base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
  1061. 0xFFFFFF);
  1062. pm8001_ha->inbnd_q_tbl_addr =
  1063. base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
  1064. 0xFFFFFF);
  1065. pm8001_ha->outbnd_q_tbl_addr =
  1066. base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
  1067. 0xFFFFFF);
  1068. pm8001_ha->ivt_tbl_addr =
  1069. base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
  1070. 0xFFFFFF);
  1071. pm8001_ha->pspa_q_tbl_addr =
  1072. base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
  1073. 0xFFFFFF);
  1074. pm8001_ha->fatal_tbl_addr =
  1075. base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
  1076. 0xFFFFFF);
  1077. pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
  1078. pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
  1079. pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
  1080. pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
  1081. pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
  1082. pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
  1083. pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
  1084. pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
  1085. pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
  1086. pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
  1087. pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
  1088. pm8001_ha->main_cfg_tbl_addr,
  1089. pm8001_ha->general_stat_tbl_addr);
  1090. pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
  1091. pm8001_ha->inbnd_q_tbl_addr,
  1092. pm8001_ha->outbnd_q_tbl_addr);
  1093. pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
  1094. pm8001_ha->pspa_q_tbl_addr,
  1095. pm8001_ha->ivt_tbl_addr);
  1096. }
  1097. /**
  1098. * pm80xx_set_thermal_config - support the thermal configuration
  1099. * @pm8001_ha: our hba card information.
  1100. */
  1101. int
  1102. pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
  1103. {
  1104. struct set_ctrl_cfg_req payload;
  1105. struct inbound_queue_table *circularQ;
  1106. int rc;
  1107. u32 tag;
  1108. u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
  1109. u32 page_code;
  1110. memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
  1111. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  1112. if (rc)
  1113. return -1;
  1114. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1115. payload.tag = cpu_to_le32(tag);
  1116. if (IS_SPCV_12G(pm8001_ha->pdev))
  1117. page_code = THERMAL_PAGE_CODE_7H;
  1118. else
  1119. page_code = THERMAL_PAGE_CODE_8H;
  1120. payload.cfg_pg[0] =
  1121. cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
  1122. (THERMAL_ENABLE << 8) | page_code);
  1123. payload.cfg_pg[1] =
  1124. cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
  1125. pm8001_dbg(pm8001_ha, DEV,
  1126. "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
  1127. payload.cfg_pg[0], payload.cfg_pg[1]);
  1128. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  1129. sizeof(payload), 0);
  1130. if (rc)
  1131. pm8001_tag_free(pm8001_ha, tag);
  1132. return rc;
  1133. }
  1134. /**
  1135. * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
  1136. * Timer configuration page
  1137. * @pm8001_ha: our hba card information.
  1138. */
  1139. static int
  1140. pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
  1141. {
  1142. struct set_ctrl_cfg_req payload;
  1143. struct inbound_queue_table *circularQ;
  1144. SASProtocolTimerConfig_t SASConfigPage;
  1145. int rc;
  1146. u32 tag;
  1147. u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
  1148. memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
  1149. memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
  1150. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  1151. if (rc)
  1152. return -1;
  1153. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1154. payload.tag = cpu_to_le32(tag);
  1155. SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
  1156. SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
  1157. SASConfigPage.STP_SSP_MCT_TMO =
  1158. cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
  1159. SASConfigPage.STP_FRM_TMO =
  1160. cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
  1161. (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
  1162. SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
  1163. SASConfigPage.OPNRJT_RTRY_INTVL =
  1164. cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
  1165. SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
  1166. cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
  1167. SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
  1168. cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
  1169. SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
  1170. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
  1171. le32_to_cpu(SASConfigPage.pageCode));
  1172. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n",
  1173. le32_to_cpu(SASConfigPage.MST_MSI));
  1174. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",
  1175. le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
  1176. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n",
  1177. le32_to_cpu(SASConfigPage.STP_FRM_TMO));
  1178. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n",
  1179. le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
  1180. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",
  1181. le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
  1182. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",
  1183. le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
  1184. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",
  1185. le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
  1186. pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n",
  1187. le32_to_cpu(SASConfigPage.MAX_AIP));
  1188. memcpy(&payload.cfg_pg, &SASConfigPage,
  1189. sizeof(SASProtocolTimerConfig_t));
  1190. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  1191. sizeof(payload), 0);
  1192. if (rc)
  1193. pm8001_tag_free(pm8001_ha, tag);
  1194. return rc;
  1195. }
  1196. /**
  1197. * pm80xx_get_encrypt_info - Check for encryption
  1198. * @pm8001_ha: our hba card information.
  1199. */
  1200. static int
  1201. pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
  1202. {
  1203. u32 scratch3_value;
  1204. int ret = -1;
  1205. /* Read encryption status from SCRATCH PAD 3 */
  1206. scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
  1207. if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
  1208. SCRATCH_PAD3_ENC_READY) {
  1209. if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
  1210. pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
  1211. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1212. SCRATCH_PAD3_SMF_ENABLED)
  1213. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
  1214. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1215. SCRATCH_PAD3_SMA_ENABLED)
  1216. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
  1217. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1218. SCRATCH_PAD3_SMB_ENABLED)
  1219. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
  1220. pm8001_ha->encrypt_info.status = 0;
  1221. pm8001_dbg(pm8001_ha, INIT,
  1222. "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
  1223. scratch3_value,
  1224. pm8001_ha->encrypt_info.cipher_mode,
  1225. pm8001_ha->encrypt_info.sec_mode,
  1226. pm8001_ha->encrypt_info.status);
  1227. ret = 0;
  1228. } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
  1229. SCRATCH_PAD3_ENC_DISABLED) {
  1230. pm8001_dbg(pm8001_ha, INIT,
  1231. "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
  1232. scratch3_value);
  1233. pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
  1234. pm8001_ha->encrypt_info.cipher_mode = 0;
  1235. pm8001_ha->encrypt_info.sec_mode = 0;
  1236. ret = 0;
  1237. } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
  1238. SCRATCH_PAD3_ENC_DIS_ERR) {
  1239. pm8001_ha->encrypt_info.status =
  1240. (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
  1241. if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
  1242. pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
  1243. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1244. SCRATCH_PAD3_SMF_ENABLED)
  1245. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
  1246. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1247. SCRATCH_PAD3_SMA_ENABLED)
  1248. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
  1249. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1250. SCRATCH_PAD3_SMB_ENABLED)
  1251. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
  1252. pm8001_dbg(pm8001_ha, INIT,
  1253. "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
  1254. scratch3_value,
  1255. pm8001_ha->encrypt_info.cipher_mode,
  1256. pm8001_ha->encrypt_info.sec_mode,
  1257. pm8001_ha->encrypt_info.status);
  1258. } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
  1259. SCRATCH_PAD3_ENC_ENA_ERR) {
  1260. pm8001_ha->encrypt_info.status =
  1261. (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
  1262. if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
  1263. pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
  1264. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1265. SCRATCH_PAD3_SMF_ENABLED)
  1266. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
  1267. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1268. SCRATCH_PAD3_SMA_ENABLED)
  1269. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
  1270. if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
  1271. SCRATCH_PAD3_SMB_ENABLED)
  1272. pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
  1273. pm8001_dbg(pm8001_ha, INIT,
  1274. "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
  1275. scratch3_value,
  1276. pm8001_ha->encrypt_info.cipher_mode,
  1277. pm8001_ha->encrypt_info.sec_mode,
  1278. pm8001_ha->encrypt_info.status);
  1279. }
  1280. return ret;
  1281. }
  1282. /**
  1283. * pm80xx_encrypt_update - update flash with encryption informtion
  1284. * @pm8001_ha: our hba card information.
  1285. */
  1286. static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
  1287. {
  1288. struct kek_mgmt_req payload;
  1289. struct inbound_queue_table *circularQ;
  1290. int rc;
  1291. u32 tag;
  1292. u32 opc = OPC_INB_KEK_MANAGEMENT;
  1293. memset(&payload, 0, sizeof(struct kek_mgmt_req));
  1294. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  1295. if (rc)
  1296. return -1;
  1297. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1298. payload.tag = cpu_to_le32(tag);
  1299. /* Currently only one key is used. New KEK index is 1.
  1300. * Current KEK index is 1. Store KEK to NVRAM is 1.
  1301. */
  1302. payload.new_curidx_ksop =
  1303. cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
  1304. KEK_MGMT_SUBOP_KEYCARDUPDATE));
  1305. pm8001_dbg(pm8001_ha, DEV,
  1306. "Saving Encryption info to flash. payload 0x%x\n",
  1307. le32_to_cpu(payload.new_curidx_ksop));
  1308. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  1309. sizeof(payload), 0);
  1310. if (rc)
  1311. pm8001_tag_free(pm8001_ha, tag);
  1312. return rc;
  1313. }
  1314. /**
  1315. * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
  1316. * @pm8001_ha: our hba card information
  1317. */
  1318. static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
  1319. {
  1320. int ret;
  1321. u8 i = 0;
  1322. /* check the firmware status */
  1323. if (-1 == check_fw_ready(pm8001_ha)) {
  1324. pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
  1325. return -EBUSY;
  1326. }
  1327. /* Initialize the controller fatal error flag */
  1328. pm8001_ha->controller_fatal_error = false;
  1329. /* Initialize pci space address eg: mpi offset */
  1330. init_pci_device_addresses(pm8001_ha);
  1331. init_default_table_values(pm8001_ha);
  1332. read_main_config_table(pm8001_ha);
  1333. read_general_status_table(pm8001_ha);
  1334. read_inbnd_queue_table(pm8001_ha);
  1335. read_outbnd_queue_table(pm8001_ha);
  1336. read_phy_attr_table(pm8001_ha);
  1337. /* update main config table ,inbound table and outbound table */
  1338. update_main_config_table(pm8001_ha);
  1339. for (i = 0; i < pm8001_ha->max_q_num; i++) {
  1340. update_inbnd_queue_table(pm8001_ha, i);
  1341. update_outbnd_queue_table(pm8001_ha, i);
  1342. }
  1343. /* notify firmware update finished and check initialization status */
  1344. if (0 == mpi_init_check(pm8001_ha)) {
  1345. pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
  1346. } else
  1347. return -EBUSY;
  1348. /* send SAS protocol timer configuration page to FW */
  1349. ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
  1350. /* Check for encryption */
  1351. if (pm8001_ha->chip->encrypt) {
  1352. pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
  1353. ret = pm80xx_get_encrypt_info(pm8001_ha);
  1354. if (ret == -1) {
  1355. pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
  1356. if (pm8001_ha->encrypt_info.status == 0x81) {
  1357. pm8001_dbg(pm8001_ha, INIT,
  1358. "Encryption enabled with error.Saving encryption key to flash\n");
  1359. pm80xx_encrypt_update(pm8001_ha);
  1360. }
  1361. }
  1362. }
  1363. return 0;
  1364. }
  1365. static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
  1366. {
  1367. u32 max_wait_count;
  1368. u32 value;
  1369. u32 gst_len_mpistate;
  1370. init_pci_device_addresses(pm8001_ha);
  1371. /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
  1372. table is stop */
  1373. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
  1374. /* wait until Inbound DoorBell Clear Register toggled */
  1375. if (IS_SPCV_12G(pm8001_ha->pdev)) {
  1376. max_wait_count = 30 * 1000 * 1000; /* 30 sec */
  1377. } else {
  1378. max_wait_count = 15 * 1000 * 1000; /* 15 sec */
  1379. }
  1380. do {
  1381. udelay(1);
  1382. value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
  1383. value &= SPCv_MSGU_CFG_TABLE_RESET;
  1384. } while ((value != 0) && (--max_wait_count));
  1385. if (!max_wait_count) {
  1386. pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
  1387. return -1;
  1388. }
  1389. /* check the MPI-State for termination in progress */
  1390. /* wait until Inbound DoorBell Clear Register toggled */
  1391. max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
  1392. do {
  1393. udelay(1);
  1394. gst_len_mpistate =
  1395. pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
  1396. GST_GSTLEN_MPIS_OFFSET);
  1397. if (GST_MPI_STATE_UNINIT ==
  1398. (gst_len_mpistate & GST_MPI_STATE_MASK))
  1399. break;
  1400. } while (--max_wait_count);
  1401. if (!max_wait_count) {
  1402. pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
  1403. gst_len_mpistate & GST_MPI_STATE_MASK);
  1404. return -1;
  1405. }
  1406. return 0;
  1407. }
  1408. /**
  1409. * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
  1410. * the FW register status to the originated status.
  1411. * @pm8001_ha: our hba card information
  1412. */
  1413. static int
  1414. pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
  1415. {
  1416. u32 regval;
  1417. u32 bootloader_state;
  1418. u32 ibutton0, ibutton1;
  1419. /* Process MPI table uninitialization only if FW is ready */
  1420. if (!pm8001_ha->controller_fatal_error) {
  1421. /* Check if MPI is in ready state to reset */
  1422. if (mpi_uninit_check(pm8001_ha) != 0) {
  1423. u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
  1424. u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  1425. u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  1426. u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
  1427. pm8001_dbg(pm8001_ha, FAIL,
  1428. "MPI state is not ready scratch: %x:%x:%x:%x\n",
  1429. r0, r1, r2, r3);
  1430. /* if things aren't ready but the bootloader is ok then
  1431. * try the reset anyway.
  1432. */
  1433. if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
  1434. return -1;
  1435. }
  1436. }
  1437. /* checked for reset register normal state; 0x0 */
  1438. regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
  1439. pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
  1440. regval);
  1441. pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
  1442. msleep(500);
  1443. regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
  1444. pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
  1445. regval);
  1446. if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
  1447. SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
  1448. pm8001_dbg(pm8001_ha, MSG,
  1449. " soft reset successful [regval: 0x%x]\n",
  1450. regval);
  1451. } else {
  1452. pm8001_dbg(pm8001_ha, MSG,
  1453. " soft reset failed [regval: 0x%x]\n",
  1454. regval);
  1455. /* check bootloader is successfully executed or in HDA mode */
  1456. bootloader_state =
  1457. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
  1458. SCRATCH_PAD1_BOOTSTATE_MASK;
  1459. if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
  1460. pm8001_dbg(pm8001_ha, MSG,
  1461. "Bootloader state - HDA mode SEEPROM\n");
  1462. } else if (bootloader_state ==
  1463. SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
  1464. pm8001_dbg(pm8001_ha, MSG,
  1465. "Bootloader state - HDA mode Bootstrap Pin\n");
  1466. } else if (bootloader_state ==
  1467. SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
  1468. pm8001_dbg(pm8001_ha, MSG,
  1469. "Bootloader state - HDA mode soft reset\n");
  1470. } else if (bootloader_state ==
  1471. SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
  1472. pm8001_dbg(pm8001_ha, MSG,
  1473. "Bootloader state-HDA mode critical error\n");
  1474. }
  1475. return -EBUSY;
  1476. }
  1477. /* check the firmware status after reset */
  1478. if (-1 == check_fw_ready(pm8001_ha)) {
  1479. pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
  1480. /* check iButton feature support for motherboard controller */
  1481. if (pm8001_ha->pdev->subsystem_vendor !=
  1482. PCI_VENDOR_ID_ADAPTEC2 &&
  1483. pm8001_ha->pdev->subsystem_vendor !=
  1484. PCI_VENDOR_ID_ATTO &&
  1485. pm8001_ha->pdev->subsystem_vendor != 0) {
  1486. ibutton0 = pm8001_cr32(pm8001_ha, 0,
  1487. MSGU_HOST_SCRATCH_PAD_6);
  1488. ibutton1 = pm8001_cr32(pm8001_ha, 0,
  1489. MSGU_HOST_SCRATCH_PAD_7);
  1490. if (!ibutton0 && !ibutton1) {
  1491. pm8001_dbg(pm8001_ha, FAIL,
  1492. "iButton Feature is not Available!!!\n");
  1493. return -EBUSY;
  1494. }
  1495. if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
  1496. pm8001_dbg(pm8001_ha, FAIL,
  1497. "CRC Check for iButton Feature Failed!!!\n");
  1498. return -EBUSY;
  1499. }
  1500. }
  1501. }
  1502. pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
  1503. return 0;
  1504. }
  1505. static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
  1506. {
  1507. u32 i;
  1508. pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
  1509. /* do SPCv chip reset. */
  1510. pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
  1511. pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
  1512. /* Check this ..whether delay is required or no */
  1513. /* delay 10 usec */
  1514. udelay(10);
  1515. /* wait for 20 msec until the firmware gets reloaded */
  1516. i = 20;
  1517. do {
  1518. mdelay(1);
  1519. } while ((--i) != 0);
  1520. pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
  1521. }
  1522. /**
  1523. * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
  1524. * @pm8001_ha: our hba card information
  1525. */
  1526. static void
  1527. pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
  1528. {
  1529. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
  1530. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
  1531. }
  1532. /**
  1533. * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
  1534. * @pm8001_ha: our hba card information
  1535. */
  1536. static void
  1537. pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
  1538. {
  1539. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
  1540. }
  1541. /**
  1542. * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
  1543. * @pm8001_ha: our hba card information
  1544. * @vec: interrupt number to enable
  1545. */
  1546. static void
  1547. pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
  1548. {
  1549. #ifdef PM8001_USE_MSIX
  1550. if (vec < 32)
  1551. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
  1552. else
  1553. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
  1554. 1U << (vec - 32));
  1555. return;
  1556. #endif
  1557. pm80xx_chip_intx_interrupt_enable(pm8001_ha);
  1558. }
  1559. /**
  1560. * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
  1561. * @pm8001_ha: our hba card information
  1562. * @vec: interrupt number to disable
  1563. */
  1564. static void
  1565. pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
  1566. {
  1567. #ifdef PM8001_USE_MSIX
  1568. if (vec == 0xFF) {
  1569. /* disable all vectors 0-31, 32-63 */
  1570. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
  1571. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
  1572. } else if (vec < 32)
  1573. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
  1574. else
  1575. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
  1576. 1U << (vec - 32));
  1577. return;
  1578. #endif
  1579. pm80xx_chip_intx_interrupt_disable(pm8001_ha);
  1580. }
  1581. static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
  1582. struct pm8001_device *pm8001_ha_dev)
  1583. {
  1584. int res;
  1585. u32 ccb_tag;
  1586. struct pm8001_ccb_info *ccb;
  1587. struct sas_task *task = NULL;
  1588. struct task_abort_req task_abort;
  1589. struct inbound_queue_table *circularQ;
  1590. u32 opc = OPC_INB_SATA_ABORT;
  1591. int ret;
  1592. if (!pm8001_ha_dev) {
  1593. pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
  1594. return;
  1595. }
  1596. task = sas_alloc_slow_task(GFP_ATOMIC);
  1597. if (!task) {
  1598. pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
  1599. return;
  1600. }
  1601. task->task_done = pm8001_task_done;
  1602. res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
  1603. if (res) {
  1604. sas_free_task(task);
  1605. return;
  1606. }
  1607. ccb = &pm8001_ha->ccb_info[ccb_tag];
  1608. ccb->device = pm8001_ha_dev;
  1609. ccb->ccb_tag = ccb_tag;
  1610. ccb->task = task;
  1611. ccb->n_elem = 0;
  1612. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1613. memset(&task_abort, 0, sizeof(task_abort));
  1614. task_abort.abort_all = cpu_to_le32(1);
  1615. task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  1616. task_abort.tag = cpu_to_le32(ccb_tag);
  1617. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
  1618. sizeof(task_abort), 0);
  1619. pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
  1620. if (ret) {
  1621. sas_free_task(task);
  1622. pm8001_tag_free(pm8001_ha, ccb_tag);
  1623. }
  1624. }
  1625. static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
  1626. struct pm8001_device *pm8001_ha_dev)
  1627. {
  1628. struct sata_start_req sata_cmd;
  1629. int res;
  1630. u32 ccb_tag;
  1631. struct pm8001_ccb_info *ccb;
  1632. struct sas_task *task = NULL;
  1633. struct host_to_dev_fis fis;
  1634. struct domain_device *dev;
  1635. struct inbound_queue_table *circularQ;
  1636. u32 opc = OPC_INB_SATA_HOST_OPSTART;
  1637. task = sas_alloc_slow_task(GFP_ATOMIC);
  1638. if (!task) {
  1639. pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
  1640. return;
  1641. }
  1642. task->task_done = pm8001_task_done;
  1643. res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
  1644. if (res) {
  1645. sas_free_task(task);
  1646. pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
  1647. return;
  1648. }
  1649. /* allocate domain device by ourselves as libsas
  1650. * is not going to provide any
  1651. */
  1652. dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
  1653. if (!dev) {
  1654. sas_free_task(task);
  1655. pm8001_tag_free(pm8001_ha, ccb_tag);
  1656. pm8001_dbg(pm8001_ha, FAIL,
  1657. "Domain device cannot be allocated\n");
  1658. return;
  1659. }
  1660. task->dev = dev;
  1661. task->dev->lldd_dev = pm8001_ha_dev;
  1662. ccb = &pm8001_ha->ccb_info[ccb_tag];
  1663. ccb->device = pm8001_ha_dev;
  1664. ccb->ccb_tag = ccb_tag;
  1665. ccb->task = task;
  1666. ccb->n_elem = 0;
  1667. pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
  1668. pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
  1669. memset(&sata_cmd, 0, sizeof(sata_cmd));
  1670. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1671. /* construct read log FIS */
  1672. memset(&fis, 0, sizeof(struct host_to_dev_fis));
  1673. fis.fis_type = 0x27;
  1674. fis.flags = 0x80;
  1675. fis.command = ATA_CMD_READ_LOG_EXT;
  1676. fis.lbal = 0x10;
  1677. fis.sector_count = 0x1;
  1678. sata_cmd.tag = cpu_to_le32(ccb_tag);
  1679. sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  1680. sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
  1681. memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
  1682. res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
  1683. sizeof(sata_cmd), 0);
  1684. pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
  1685. if (res) {
  1686. sas_free_task(task);
  1687. pm8001_tag_free(pm8001_ha, ccb_tag);
  1688. kfree(dev);
  1689. }
  1690. }
  1691. /**
  1692. * mpi_ssp_completion- process the event that FW response to the SSP request.
  1693. * @pm8001_ha: our hba card information
  1694. * @piomb: the message contents of this outbound message.
  1695. *
  1696. * When FW has completed a ssp request for example a IO request, after it has
  1697. * filled the SG data with the data, it will trigger this event represent
  1698. * that he has finished the job,please check the coresponding buffer.
  1699. * So we will tell the caller who maybe waiting the result to tell upper layer
  1700. * that the task has been finished.
  1701. */
  1702. static void
  1703. mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
  1704. {
  1705. struct sas_task *t;
  1706. struct pm8001_ccb_info *ccb;
  1707. unsigned long flags;
  1708. u32 status;
  1709. u32 param;
  1710. u32 tag;
  1711. struct ssp_completion_resp *psspPayload;
  1712. struct task_status_struct *ts;
  1713. struct ssp_response_iu *iu;
  1714. struct pm8001_device *pm8001_dev;
  1715. psspPayload = (struct ssp_completion_resp *)(piomb + 4);
  1716. status = le32_to_cpu(psspPayload->status);
  1717. tag = le32_to_cpu(psspPayload->tag);
  1718. ccb = &pm8001_ha->ccb_info[tag];
  1719. if ((status == IO_ABORTED) && ccb->open_retry) {
  1720. /* Being completed by another */
  1721. ccb->open_retry = 0;
  1722. return;
  1723. }
  1724. pm8001_dev = ccb->device;
  1725. param = le32_to_cpu(psspPayload->param);
  1726. t = ccb->task;
  1727. if (status && status != IO_UNDERFLOW)
  1728. pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
  1729. if (unlikely(!t || !t->lldd_task || !t->dev))
  1730. return;
  1731. ts = &t->task_status;
  1732. pm8001_dbg(pm8001_ha, DEV,
  1733. "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
  1734. /* Print sas address of IO failed device */
  1735. if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
  1736. (status != IO_UNDERFLOW))
  1737. pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
  1738. SAS_ADDR(t->dev->sas_addr));
  1739. switch (status) {
  1740. case IO_SUCCESS:
  1741. pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
  1742. param);
  1743. if (param == 0) {
  1744. ts->resp = SAS_TASK_COMPLETE;
  1745. ts->stat = SAM_STAT_GOOD;
  1746. } else {
  1747. ts->resp = SAS_TASK_COMPLETE;
  1748. ts->stat = SAS_PROTO_RESPONSE;
  1749. ts->residual = param;
  1750. iu = &psspPayload->ssp_resp_iu;
  1751. sas_ssp_task_response(pm8001_ha->dev, t, iu);
  1752. }
  1753. if (pm8001_dev)
  1754. atomic_dec(&pm8001_dev->running_req);
  1755. break;
  1756. case IO_ABORTED:
  1757. pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
  1758. ts->resp = SAS_TASK_COMPLETE;
  1759. ts->stat = SAS_ABORTED_TASK;
  1760. if (pm8001_dev)
  1761. atomic_dec(&pm8001_dev->running_req);
  1762. break;
  1763. case IO_UNDERFLOW:
  1764. /* SSP Completion with error */
  1765. pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
  1766. param);
  1767. ts->resp = SAS_TASK_COMPLETE;
  1768. ts->stat = SAS_DATA_UNDERRUN;
  1769. ts->residual = param;
  1770. if (pm8001_dev)
  1771. atomic_dec(&pm8001_dev->running_req);
  1772. break;
  1773. case IO_NO_DEVICE:
  1774. pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
  1775. ts->resp = SAS_TASK_UNDELIVERED;
  1776. ts->stat = SAS_PHY_DOWN;
  1777. if (pm8001_dev)
  1778. atomic_dec(&pm8001_dev->running_req);
  1779. break;
  1780. case IO_XFER_ERROR_BREAK:
  1781. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
  1782. ts->resp = SAS_TASK_COMPLETE;
  1783. ts->stat = SAS_OPEN_REJECT;
  1784. /* Force the midlayer to retry */
  1785. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1786. if (pm8001_dev)
  1787. atomic_dec(&pm8001_dev->running_req);
  1788. break;
  1789. case IO_XFER_ERROR_PHY_NOT_READY:
  1790. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
  1791. ts->resp = SAS_TASK_COMPLETE;
  1792. ts->stat = SAS_OPEN_REJECT;
  1793. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1794. if (pm8001_dev)
  1795. atomic_dec(&pm8001_dev->running_req);
  1796. break;
  1797. case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
  1798. pm8001_dbg(pm8001_ha, IO,
  1799. "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
  1800. ts->resp = SAS_TASK_COMPLETE;
  1801. ts->stat = SAS_OPEN_REJECT;
  1802. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1803. if (pm8001_dev)
  1804. atomic_dec(&pm8001_dev->running_req);
  1805. break;
  1806. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  1807. pm8001_dbg(pm8001_ha, IO,
  1808. "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
  1809. ts->resp = SAS_TASK_COMPLETE;
  1810. ts->stat = SAS_OPEN_REJECT;
  1811. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1812. if (pm8001_dev)
  1813. atomic_dec(&pm8001_dev->running_req);
  1814. break;
  1815. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  1816. pm8001_dbg(pm8001_ha, IO,
  1817. "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
  1818. ts->resp = SAS_TASK_COMPLETE;
  1819. ts->stat = SAS_OPEN_REJECT;
  1820. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1821. if (pm8001_dev)
  1822. atomic_dec(&pm8001_dev->running_req);
  1823. break;
  1824. case IO_OPEN_CNX_ERROR_BREAK:
  1825. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
  1826. ts->resp = SAS_TASK_COMPLETE;
  1827. ts->stat = SAS_OPEN_REJECT;
  1828. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1829. if (pm8001_dev)
  1830. atomic_dec(&pm8001_dev->running_req);
  1831. break;
  1832. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1833. case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
  1834. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
  1835. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
  1836. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
  1837. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
  1838. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
  1839. ts->resp = SAS_TASK_COMPLETE;
  1840. ts->stat = SAS_OPEN_REJECT;
  1841. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1842. if (!t->uldd_task)
  1843. pm8001_handle_event(pm8001_ha,
  1844. pm8001_dev,
  1845. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  1846. break;
  1847. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  1848. pm8001_dbg(pm8001_ha, IO,
  1849. "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
  1850. ts->resp = SAS_TASK_COMPLETE;
  1851. ts->stat = SAS_OPEN_REJECT;
  1852. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  1853. if (pm8001_dev)
  1854. atomic_dec(&pm8001_dev->running_req);
  1855. break;
  1856. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  1857. pm8001_dbg(pm8001_ha, IO,
  1858. "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
  1859. ts->resp = SAS_TASK_COMPLETE;
  1860. ts->stat = SAS_OPEN_REJECT;
  1861. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1862. if (pm8001_dev)
  1863. atomic_dec(&pm8001_dev->running_req);
  1864. break;
  1865. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  1866. pm8001_dbg(pm8001_ha, IO,
  1867. "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
  1868. ts->resp = SAS_TASK_UNDELIVERED;
  1869. ts->stat = SAS_OPEN_REJECT;
  1870. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1871. if (pm8001_dev)
  1872. atomic_dec(&pm8001_dev->running_req);
  1873. break;
  1874. case IO_XFER_ERROR_NAK_RECEIVED:
  1875. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
  1876. ts->resp = SAS_TASK_COMPLETE;
  1877. ts->stat = SAS_OPEN_REJECT;
  1878. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1879. if (pm8001_dev)
  1880. atomic_dec(&pm8001_dev->running_req);
  1881. break;
  1882. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  1883. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
  1884. ts->resp = SAS_TASK_COMPLETE;
  1885. ts->stat = SAS_NAK_R_ERR;
  1886. if (pm8001_dev)
  1887. atomic_dec(&pm8001_dev->running_req);
  1888. break;
  1889. case IO_XFER_ERROR_DMA:
  1890. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
  1891. ts->resp = SAS_TASK_COMPLETE;
  1892. ts->stat = SAS_OPEN_REJECT;
  1893. if (pm8001_dev)
  1894. atomic_dec(&pm8001_dev->running_req);
  1895. break;
  1896. case IO_XFER_OPEN_RETRY_TIMEOUT:
  1897. pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
  1898. ts->resp = SAS_TASK_COMPLETE;
  1899. ts->stat = SAS_OPEN_REJECT;
  1900. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1901. if (pm8001_dev)
  1902. atomic_dec(&pm8001_dev->running_req);
  1903. break;
  1904. case IO_XFER_ERROR_OFFSET_MISMATCH:
  1905. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
  1906. ts->resp = SAS_TASK_COMPLETE;
  1907. ts->stat = SAS_OPEN_REJECT;
  1908. if (pm8001_dev)
  1909. atomic_dec(&pm8001_dev->running_req);
  1910. break;
  1911. case IO_PORT_IN_RESET:
  1912. pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
  1913. ts->resp = SAS_TASK_COMPLETE;
  1914. ts->stat = SAS_OPEN_REJECT;
  1915. if (pm8001_dev)
  1916. atomic_dec(&pm8001_dev->running_req);
  1917. break;
  1918. case IO_DS_NON_OPERATIONAL:
  1919. pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
  1920. ts->resp = SAS_TASK_COMPLETE;
  1921. ts->stat = SAS_OPEN_REJECT;
  1922. if (!t->uldd_task)
  1923. pm8001_handle_event(pm8001_ha,
  1924. pm8001_dev,
  1925. IO_DS_NON_OPERATIONAL);
  1926. break;
  1927. case IO_DS_IN_RECOVERY:
  1928. pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
  1929. ts->resp = SAS_TASK_COMPLETE;
  1930. ts->stat = SAS_OPEN_REJECT;
  1931. if (pm8001_dev)
  1932. atomic_dec(&pm8001_dev->running_req);
  1933. break;
  1934. case IO_TM_TAG_NOT_FOUND:
  1935. pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
  1936. ts->resp = SAS_TASK_COMPLETE;
  1937. ts->stat = SAS_OPEN_REJECT;
  1938. if (pm8001_dev)
  1939. atomic_dec(&pm8001_dev->running_req);
  1940. break;
  1941. case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
  1942. pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
  1943. ts->resp = SAS_TASK_COMPLETE;
  1944. ts->stat = SAS_OPEN_REJECT;
  1945. if (pm8001_dev)
  1946. atomic_dec(&pm8001_dev->running_req);
  1947. break;
  1948. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  1949. pm8001_dbg(pm8001_ha, IO,
  1950. "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
  1951. ts->resp = SAS_TASK_COMPLETE;
  1952. ts->stat = SAS_OPEN_REJECT;
  1953. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1954. if (pm8001_dev)
  1955. atomic_dec(&pm8001_dev->running_req);
  1956. break;
  1957. default:
  1958. pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
  1959. /* not allowed case. Therefore, return failed status */
  1960. ts->resp = SAS_TASK_COMPLETE;
  1961. ts->stat = SAS_OPEN_REJECT;
  1962. if (pm8001_dev)
  1963. atomic_dec(&pm8001_dev->running_req);
  1964. break;
  1965. }
  1966. pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
  1967. psspPayload->ssp_resp_iu.status);
  1968. spin_lock_irqsave(&t->task_state_lock, flags);
  1969. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1970. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  1971. t->task_state_flags |= SAS_TASK_STATE_DONE;
  1972. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  1973. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1974. pm8001_dbg(pm8001_ha, FAIL,
  1975. "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
  1976. t, status, ts->resp, ts->stat);
  1977. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1978. if (t->slow_task)
  1979. complete(&t->slow_task->completion);
  1980. } else {
  1981. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1982. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1983. mb();/* in order to force CPU ordering */
  1984. t->task_done(t);
  1985. }
  1986. }
  1987. /*See the comments for mpi_ssp_completion */
  1988. static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  1989. {
  1990. struct sas_task *t;
  1991. unsigned long flags;
  1992. struct task_status_struct *ts;
  1993. struct pm8001_ccb_info *ccb;
  1994. struct pm8001_device *pm8001_dev;
  1995. struct ssp_event_resp *psspPayload =
  1996. (struct ssp_event_resp *)(piomb + 4);
  1997. u32 event = le32_to_cpu(psspPayload->event);
  1998. u32 tag = le32_to_cpu(psspPayload->tag);
  1999. u32 port_id = le32_to_cpu(psspPayload->port_id);
  2000. ccb = &pm8001_ha->ccb_info[tag];
  2001. t = ccb->task;
  2002. pm8001_dev = ccb->device;
  2003. if (event)
  2004. pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
  2005. if (unlikely(!t || !t->lldd_task || !t->dev))
  2006. return;
  2007. ts = &t->task_status;
  2008. pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
  2009. port_id, tag, event);
  2010. switch (event) {
  2011. case IO_OVERFLOW:
  2012. pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
  2013. ts->resp = SAS_TASK_COMPLETE;
  2014. ts->stat = SAS_DATA_OVERRUN;
  2015. ts->residual = 0;
  2016. if (pm8001_dev)
  2017. atomic_dec(&pm8001_dev->running_req);
  2018. break;
  2019. case IO_XFER_ERROR_BREAK:
  2020. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
  2021. pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
  2022. return;
  2023. case IO_XFER_ERROR_PHY_NOT_READY:
  2024. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
  2025. ts->resp = SAS_TASK_COMPLETE;
  2026. ts->stat = SAS_OPEN_REJECT;
  2027. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2028. break;
  2029. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2030. pm8001_dbg(pm8001_ha, IO,
  2031. "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
  2032. ts->resp = SAS_TASK_COMPLETE;
  2033. ts->stat = SAS_OPEN_REJECT;
  2034. ts->open_rej_reason = SAS_OREJ_EPROTO;
  2035. break;
  2036. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2037. pm8001_dbg(pm8001_ha, IO,
  2038. "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
  2039. ts->resp = SAS_TASK_COMPLETE;
  2040. ts->stat = SAS_OPEN_REJECT;
  2041. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2042. break;
  2043. case IO_OPEN_CNX_ERROR_BREAK:
  2044. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
  2045. ts->resp = SAS_TASK_COMPLETE;
  2046. ts->stat = SAS_OPEN_REJECT;
  2047. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2048. break;
  2049. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2050. case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
  2051. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
  2052. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
  2053. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
  2054. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
  2055. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
  2056. ts->resp = SAS_TASK_COMPLETE;
  2057. ts->stat = SAS_OPEN_REJECT;
  2058. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2059. if (!t->uldd_task)
  2060. pm8001_handle_event(pm8001_ha,
  2061. pm8001_dev,
  2062. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2063. break;
  2064. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2065. pm8001_dbg(pm8001_ha, IO,
  2066. "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
  2067. ts->resp = SAS_TASK_COMPLETE;
  2068. ts->stat = SAS_OPEN_REJECT;
  2069. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2070. break;
  2071. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2072. pm8001_dbg(pm8001_ha, IO,
  2073. "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
  2074. ts->resp = SAS_TASK_COMPLETE;
  2075. ts->stat = SAS_OPEN_REJECT;
  2076. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2077. break;
  2078. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2079. pm8001_dbg(pm8001_ha, IO,
  2080. "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
  2081. ts->resp = SAS_TASK_COMPLETE;
  2082. ts->stat = SAS_OPEN_REJECT;
  2083. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2084. break;
  2085. case IO_XFER_ERROR_NAK_RECEIVED:
  2086. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
  2087. ts->resp = SAS_TASK_COMPLETE;
  2088. ts->stat = SAS_OPEN_REJECT;
  2089. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2090. break;
  2091. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  2092. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
  2093. ts->resp = SAS_TASK_COMPLETE;
  2094. ts->stat = SAS_NAK_R_ERR;
  2095. break;
  2096. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2097. pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
  2098. pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
  2099. return;
  2100. case IO_XFER_ERROR_UNEXPECTED_PHASE:
  2101. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
  2102. ts->resp = SAS_TASK_COMPLETE;
  2103. ts->stat = SAS_DATA_OVERRUN;
  2104. break;
  2105. case IO_XFER_ERROR_XFER_RDY_OVERRUN:
  2106. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
  2107. ts->resp = SAS_TASK_COMPLETE;
  2108. ts->stat = SAS_DATA_OVERRUN;
  2109. break;
  2110. case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
  2111. pm8001_dbg(pm8001_ha, IO,
  2112. "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
  2113. ts->resp = SAS_TASK_COMPLETE;
  2114. ts->stat = SAS_DATA_OVERRUN;
  2115. break;
  2116. case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
  2117. pm8001_dbg(pm8001_ha, IO,
  2118. "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
  2119. ts->resp = SAS_TASK_COMPLETE;
  2120. ts->stat = SAS_DATA_OVERRUN;
  2121. break;
  2122. case IO_XFER_ERROR_OFFSET_MISMATCH:
  2123. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
  2124. ts->resp = SAS_TASK_COMPLETE;
  2125. ts->stat = SAS_DATA_OVERRUN;
  2126. break;
  2127. case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
  2128. pm8001_dbg(pm8001_ha, IO,
  2129. "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
  2130. ts->resp = SAS_TASK_COMPLETE;
  2131. ts->stat = SAS_DATA_OVERRUN;
  2132. break;
  2133. case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
  2134. pm8001_dbg(pm8001_ha, IOERR,
  2135. "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
  2136. /* TBC: used default set values */
  2137. ts->resp = SAS_TASK_COMPLETE;
  2138. ts->stat = SAS_DATA_OVERRUN;
  2139. break;
  2140. case IO_XFER_CMD_FRAME_ISSUED:
  2141. pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
  2142. return;
  2143. default:
  2144. pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
  2145. /* not allowed case. Therefore, return failed status */
  2146. ts->resp = SAS_TASK_COMPLETE;
  2147. ts->stat = SAS_DATA_OVERRUN;
  2148. break;
  2149. }
  2150. spin_lock_irqsave(&t->task_state_lock, flags);
  2151. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2152. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2153. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2154. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2155. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2156. pm8001_dbg(pm8001_ha, FAIL,
  2157. "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2158. t, event, ts->resp, ts->stat);
  2159. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2160. } else {
  2161. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2162. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2163. mb();/* in order to force CPU ordering */
  2164. t->task_done(t);
  2165. }
  2166. }
  2167. /*See the comments for mpi_ssp_completion */
  2168. static void
  2169. mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2170. {
  2171. struct sas_task *t;
  2172. struct pm8001_ccb_info *ccb;
  2173. u32 param;
  2174. u32 status;
  2175. u32 tag;
  2176. int i, j;
  2177. u8 sata_addr_low[4];
  2178. u32 temp_sata_addr_low, temp_sata_addr_hi;
  2179. u8 sata_addr_hi[4];
  2180. struct sata_completion_resp *psataPayload;
  2181. struct task_status_struct *ts;
  2182. struct ata_task_resp *resp ;
  2183. u32 *sata_resp;
  2184. struct pm8001_device *pm8001_dev;
  2185. unsigned long flags;
  2186. psataPayload = (struct sata_completion_resp *)(piomb + 4);
  2187. status = le32_to_cpu(psataPayload->status);
  2188. tag = le32_to_cpu(psataPayload->tag);
  2189. if (!tag) {
  2190. pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
  2191. return;
  2192. }
  2193. ccb = &pm8001_ha->ccb_info[tag];
  2194. param = le32_to_cpu(psataPayload->param);
  2195. if (ccb) {
  2196. t = ccb->task;
  2197. pm8001_dev = ccb->device;
  2198. } else {
  2199. pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
  2200. return;
  2201. }
  2202. if (t) {
  2203. if (t->dev && (t->dev->lldd_dev))
  2204. pm8001_dev = t->dev->lldd_dev;
  2205. } else {
  2206. pm8001_dbg(pm8001_ha, FAIL, "task null\n");
  2207. return;
  2208. }
  2209. if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
  2210. && unlikely(!t || !t->lldd_task || !t->dev)) {
  2211. pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
  2212. return;
  2213. }
  2214. ts = &t->task_status;
  2215. if (!ts) {
  2216. pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
  2217. return;
  2218. }
  2219. if (unlikely(status))
  2220. pm8001_dbg(pm8001_ha, IOERR,
  2221. "status:0x%x, tag:0x%x, task::0x%p\n",
  2222. status, tag, t);
  2223. /* Print sas address of IO failed device */
  2224. if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
  2225. (status != IO_UNDERFLOW)) {
  2226. if (!((t->dev->parent) &&
  2227. (dev_is_expander(t->dev->parent->dev_type)))) {
  2228. for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
  2229. sata_addr_low[i] = pm8001_ha->sas_addr[j];
  2230. for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
  2231. sata_addr_hi[i] = pm8001_ha->sas_addr[j];
  2232. memcpy(&temp_sata_addr_low, sata_addr_low,
  2233. sizeof(sata_addr_low));
  2234. memcpy(&temp_sata_addr_hi, sata_addr_hi,
  2235. sizeof(sata_addr_hi));
  2236. temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
  2237. |((temp_sata_addr_hi << 8) &
  2238. 0xff0000) |
  2239. ((temp_sata_addr_hi >> 8)
  2240. & 0xff00) |
  2241. ((temp_sata_addr_hi << 24) &
  2242. 0xff000000));
  2243. temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
  2244. & 0xff) |
  2245. ((temp_sata_addr_low << 8)
  2246. & 0xff0000) |
  2247. ((temp_sata_addr_low >> 8)
  2248. & 0xff00) |
  2249. ((temp_sata_addr_low << 24)
  2250. & 0xff000000)) +
  2251. pm8001_dev->attached_phy +
  2252. 0x10);
  2253. pm8001_dbg(pm8001_ha, FAIL,
  2254. "SAS Address of IO Failure Drive:%08x%08x\n",
  2255. temp_sata_addr_hi,
  2256. temp_sata_addr_low);
  2257. } else {
  2258. pm8001_dbg(pm8001_ha, FAIL,
  2259. "SAS Address of IO Failure Drive:%016llx\n",
  2260. SAS_ADDR(t->dev->sas_addr));
  2261. }
  2262. }
  2263. switch (status) {
  2264. case IO_SUCCESS:
  2265. pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
  2266. if (param == 0) {
  2267. ts->resp = SAS_TASK_COMPLETE;
  2268. ts->stat = SAM_STAT_GOOD;
  2269. /* check if response is for SEND READ LOG */
  2270. if (pm8001_dev &&
  2271. (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
  2272. /* set new bit for abort_all */
  2273. pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
  2274. /* clear bit for read log */
  2275. pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
  2276. pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
  2277. /* Free the tag */
  2278. pm8001_tag_free(pm8001_ha, tag);
  2279. sas_free_task(t);
  2280. return;
  2281. }
  2282. } else {
  2283. u8 len;
  2284. ts->resp = SAS_TASK_COMPLETE;
  2285. ts->stat = SAS_PROTO_RESPONSE;
  2286. ts->residual = param;
  2287. pm8001_dbg(pm8001_ha, IO,
  2288. "SAS_PROTO_RESPONSE len = %d\n",
  2289. param);
  2290. sata_resp = &psataPayload->sata_resp[0];
  2291. resp = (struct ata_task_resp *)ts->buf;
  2292. if (t->ata_task.dma_xfer == 0 &&
  2293. t->data_dir == DMA_FROM_DEVICE) {
  2294. len = sizeof(struct pio_setup_fis);
  2295. pm8001_dbg(pm8001_ha, IO,
  2296. "PIO read len = %d\n", len);
  2297. } else if (t->ata_task.use_ncq &&
  2298. t->data_dir != DMA_NONE) {
  2299. len = sizeof(struct set_dev_bits_fis);
  2300. pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
  2301. len);
  2302. } else {
  2303. len = sizeof(struct dev_to_host_fis);
  2304. pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
  2305. len);
  2306. }
  2307. if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
  2308. resp->frame_len = len;
  2309. memcpy(&resp->ending_fis[0], sata_resp, len);
  2310. ts->buf_valid_size = sizeof(*resp);
  2311. } else
  2312. pm8001_dbg(pm8001_ha, IO,
  2313. "response too large\n");
  2314. }
  2315. if (pm8001_dev)
  2316. atomic_dec(&pm8001_dev->running_req);
  2317. break;
  2318. case IO_ABORTED:
  2319. pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
  2320. ts->resp = SAS_TASK_COMPLETE;
  2321. ts->stat = SAS_ABORTED_TASK;
  2322. if (pm8001_dev)
  2323. atomic_dec(&pm8001_dev->running_req);
  2324. break;
  2325. /* following cases are to do cases */
  2326. case IO_UNDERFLOW:
  2327. /* SATA Completion with error */
  2328. pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
  2329. ts->resp = SAS_TASK_COMPLETE;
  2330. ts->stat = SAS_DATA_UNDERRUN;
  2331. ts->residual = param;
  2332. if (pm8001_dev)
  2333. atomic_dec(&pm8001_dev->running_req);
  2334. break;
  2335. case IO_NO_DEVICE:
  2336. pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
  2337. ts->resp = SAS_TASK_UNDELIVERED;
  2338. ts->stat = SAS_PHY_DOWN;
  2339. if (pm8001_dev)
  2340. atomic_dec(&pm8001_dev->running_req);
  2341. break;
  2342. case IO_XFER_ERROR_BREAK:
  2343. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
  2344. ts->resp = SAS_TASK_COMPLETE;
  2345. ts->stat = SAS_INTERRUPTED;
  2346. if (pm8001_dev)
  2347. atomic_dec(&pm8001_dev->running_req);
  2348. break;
  2349. case IO_XFER_ERROR_PHY_NOT_READY:
  2350. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
  2351. ts->resp = SAS_TASK_COMPLETE;
  2352. ts->stat = SAS_OPEN_REJECT;
  2353. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2354. if (pm8001_dev)
  2355. atomic_dec(&pm8001_dev->running_req);
  2356. break;
  2357. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2358. pm8001_dbg(pm8001_ha, IO,
  2359. "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
  2360. ts->resp = SAS_TASK_COMPLETE;
  2361. ts->stat = SAS_OPEN_REJECT;
  2362. ts->open_rej_reason = SAS_OREJ_EPROTO;
  2363. if (pm8001_dev)
  2364. atomic_dec(&pm8001_dev->running_req);
  2365. break;
  2366. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2367. pm8001_dbg(pm8001_ha, IO,
  2368. "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
  2369. ts->resp = SAS_TASK_COMPLETE;
  2370. ts->stat = SAS_OPEN_REJECT;
  2371. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2372. if (pm8001_dev)
  2373. atomic_dec(&pm8001_dev->running_req);
  2374. break;
  2375. case IO_OPEN_CNX_ERROR_BREAK:
  2376. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
  2377. ts->resp = SAS_TASK_COMPLETE;
  2378. ts->stat = SAS_OPEN_REJECT;
  2379. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2380. if (pm8001_dev)
  2381. atomic_dec(&pm8001_dev->running_req);
  2382. break;
  2383. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2384. case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
  2385. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
  2386. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
  2387. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
  2388. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
  2389. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
  2390. ts->resp = SAS_TASK_COMPLETE;
  2391. ts->stat = SAS_DEV_NO_RESPONSE;
  2392. if (!t->uldd_task) {
  2393. pm8001_handle_event(pm8001_ha,
  2394. pm8001_dev,
  2395. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2396. ts->resp = SAS_TASK_UNDELIVERED;
  2397. ts->stat = SAS_QUEUE_FULL;
  2398. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2399. return;
  2400. }
  2401. break;
  2402. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2403. pm8001_dbg(pm8001_ha, IO,
  2404. "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
  2405. ts->resp = SAS_TASK_UNDELIVERED;
  2406. ts->stat = SAS_OPEN_REJECT;
  2407. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2408. if (!t->uldd_task) {
  2409. pm8001_handle_event(pm8001_ha,
  2410. pm8001_dev,
  2411. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2412. ts->resp = SAS_TASK_UNDELIVERED;
  2413. ts->stat = SAS_QUEUE_FULL;
  2414. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2415. return;
  2416. }
  2417. break;
  2418. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2419. pm8001_dbg(pm8001_ha, IO,
  2420. "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
  2421. ts->resp = SAS_TASK_COMPLETE;
  2422. ts->stat = SAS_OPEN_REJECT;
  2423. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2424. if (pm8001_dev)
  2425. atomic_dec(&pm8001_dev->running_req);
  2426. break;
  2427. case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
  2428. pm8001_dbg(pm8001_ha, IO,
  2429. "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
  2430. ts->resp = SAS_TASK_COMPLETE;
  2431. ts->stat = SAS_DEV_NO_RESPONSE;
  2432. if (!t->uldd_task) {
  2433. pm8001_handle_event(pm8001_ha,
  2434. pm8001_dev,
  2435. IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
  2436. ts->resp = SAS_TASK_UNDELIVERED;
  2437. ts->stat = SAS_QUEUE_FULL;
  2438. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2439. return;
  2440. }
  2441. break;
  2442. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2443. pm8001_dbg(pm8001_ha, IO,
  2444. "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
  2445. ts->resp = SAS_TASK_COMPLETE;
  2446. ts->stat = SAS_OPEN_REJECT;
  2447. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2448. if (pm8001_dev)
  2449. atomic_dec(&pm8001_dev->running_req);
  2450. break;
  2451. case IO_XFER_ERROR_NAK_RECEIVED:
  2452. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
  2453. ts->resp = SAS_TASK_COMPLETE;
  2454. ts->stat = SAS_NAK_R_ERR;
  2455. if (pm8001_dev)
  2456. atomic_dec(&pm8001_dev->running_req);
  2457. break;
  2458. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  2459. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
  2460. ts->resp = SAS_TASK_COMPLETE;
  2461. ts->stat = SAS_NAK_R_ERR;
  2462. if (pm8001_dev)
  2463. atomic_dec(&pm8001_dev->running_req);
  2464. break;
  2465. case IO_XFER_ERROR_DMA:
  2466. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
  2467. ts->resp = SAS_TASK_COMPLETE;
  2468. ts->stat = SAS_ABORTED_TASK;
  2469. if (pm8001_dev)
  2470. atomic_dec(&pm8001_dev->running_req);
  2471. break;
  2472. case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
  2473. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
  2474. ts->resp = SAS_TASK_UNDELIVERED;
  2475. ts->stat = SAS_DEV_NO_RESPONSE;
  2476. if (pm8001_dev)
  2477. atomic_dec(&pm8001_dev->running_req);
  2478. break;
  2479. case IO_XFER_ERROR_REJECTED_NCQ_MODE:
  2480. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
  2481. ts->resp = SAS_TASK_COMPLETE;
  2482. ts->stat = SAS_DATA_UNDERRUN;
  2483. if (pm8001_dev)
  2484. atomic_dec(&pm8001_dev->running_req);
  2485. break;
  2486. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2487. pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
  2488. ts->resp = SAS_TASK_COMPLETE;
  2489. ts->stat = SAS_OPEN_TO;
  2490. if (pm8001_dev)
  2491. atomic_dec(&pm8001_dev->running_req);
  2492. break;
  2493. case IO_PORT_IN_RESET:
  2494. pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
  2495. ts->resp = SAS_TASK_COMPLETE;
  2496. ts->stat = SAS_DEV_NO_RESPONSE;
  2497. if (pm8001_dev)
  2498. atomic_dec(&pm8001_dev->running_req);
  2499. break;
  2500. case IO_DS_NON_OPERATIONAL:
  2501. pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
  2502. ts->resp = SAS_TASK_COMPLETE;
  2503. ts->stat = SAS_DEV_NO_RESPONSE;
  2504. if (!t->uldd_task) {
  2505. pm8001_handle_event(pm8001_ha, pm8001_dev,
  2506. IO_DS_NON_OPERATIONAL);
  2507. ts->resp = SAS_TASK_UNDELIVERED;
  2508. ts->stat = SAS_QUEUE_FULL;
  2509. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2510. return;
  2511. }
  2512. break;
  2513. case IO_DS_IN_RECOVERY:
  2514. pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
  2515. ts->resp = SAS_TASK_COMPLETE;
  2516. ts->stat = SAS_DEV_NO_RESPONSE;
  2517. if (pm8001_dev)
  2518. atomic_dec(&pm8001_dev->running_req);
  2519. break;
  2520. case IO_DS_IN_ERROR:
  2521. pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
  2522. ts->resp = SAS_TASK_COMPLETE;
  2523. ts->stat = SAS_DEV_NO_RESPONSE;
  2524. if (!t->uldd_task) {
  2525. pm8001_handle_event(pm8001_ha, pm8001_dev,
  2526. IO_DS_IN_ERROR);
  2527. ts->resp = SAS_TASK_UNDELIVERED;
  2528. ts->stat = SAS_QUEUE_FULL;
  2529. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2530. return;
  2531. }
  2532. break;
  2533. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  2534. pm8001_dbg(pm8001_ha, IO,
  2535. "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
  2536. ts->resp = SAS_TASK_COMPLETE;
  2537. ts->stat = SAS_OPEN_REJECT;
  2538. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2539. if (pm8001_dev)
  2540. atomic_dec(&pm8001_dev->running_req);
  2541. break;
  2542. default:
  2543. pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
  2544. /* not allowed case. Therefore, return failed status */
  2545. ts->resp = SAS_TASK_COMPLETE;
  2546. ts->stat = SAS_DEV_NO_RESPONSE;
  2547. if (pm8001_dev)
  2548. atomic_dec(&pm8001_dev->running_req);
  2549. break;
  2550. }
  2551. spin_lock_irqsave(&t->task_state_lock, flags);
  2552. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2553. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2554. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2555. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2556. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2557. pm8001_dbg(pm8001_ha, FAIL,
  2558. "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2559. t, status, ts->resp, ts->stat);
  2560. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2561. if (t->slow_task)
  2562. complete(&t->slow_task->completion);
  2563. } else {
  2564. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2565. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2566. }
  2567. }
  2568. /*See the comments for mpi_ssp_completion */
  2569. static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  2570. {
  2571. struct sas_task *t;
  2572. struct task_status_struct *ts;
  2573. struct pm8001_ccb_info *ccb;
  2574. struct pm8001_device *pm8001_dev;
  2575. struct sata_event_resp *psataPayload =
  2576. (struct sata_event_resp *)(piomb + 4);
  2577. u32 event = le32_to_cpu(psataPayload->event);
  2578. u32 tag = le32_to_cpu(psataPayload->tag);
  2579. u32 port_id = le32_to_cpu(psataPayload->port_id);
  2580. u32 dev_id = le32_to_cpu(psataPayload->device_id);
  2581. unsigned long flags;
  2582. ccb = &pm8001_ha->ccb_info[tag];
  2583. if (ccb) {
  2584. t = ccb->task;
  2585. pm8001_dev = ccb->device;
  2586. } else {
  2587. pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
  2588. return;
  2589. }
  2590. if (event)
  2591. pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
  2592. /* Check if this is NCQ error */
  2593. if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
  2594. /* find device using device id */
  2595. pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
  2596. /* send read log extension */
  2597. if (pm8001_dev)
  2598. pm80xx_send_read_log(pm8001_ha, pm8001_dev);
  2599. return;
  2600. }
  2601. if (unlikely(!t || !t->lldd_task || !t->dev)) {
  2602. pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
  2603. return;
  2604. }
  2605. ts = &t->task_status;
  2606. pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
  2607. port_id, tag, event);
  2608. switch (event) {
  2609. case IO_OVERFLOW:
  2610. pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
  2611. ts->resp = SAS_TASK_COMPLETE;
  2612. ts->stat = SAS_DATA_OVERRUN;
  2613. ts->residual = 0;
  2614. if (pm8001_dev)
  2615. atomic_dec(&pm8001_dev->running_req);
  2616. break;
  2617. case IO_XFER_ERROR_BREAK:
  2618. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
  2619. ts->resp = SAS_TASK_COMPLETE;
  2620. ts->stat = SAS_INTERRUPTED;
  2621. break;
  2622. case IO_XFER_ERROR_PHY_NOT_READY:
  2623. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
  2624. ts->resp = SAS_TASK_COMPLETE;
  2625. ts->stat = SAS_OPEN_REJECT;
  2626. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2627. break;
  2628. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2629. pm8001_dbg(pm8001_ha, IO,
  2630. "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
  2631. ts->resp = SAS_TASK_COMPLETE;
  2632. ts->stat = SAS_OPEN_REJECT;
  2633. ts->open_rej_reason = SAS_OREJ_EPROTO;
  2634. break;
  2635. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2636. pm8001_dbg(pm8001_ha, IO,
  2637. "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
  2638. ts->resp = SAS_TASK_COMPLETE;
  2639. ts->stat = SAS_OPEN_REJECT;
  2640. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2641. break;
  2642. case IO_OPEN_CNX_ERROR_BREAK:
  2643. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
  2644. ts->resp = SAS_TASK_COMPLETE;
  2645. ts->stat = SAS_OPEN_REJECT;
  2646. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2647. break;
  2648. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2649. case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
  2650. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
  2651. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
  2652. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
  2653. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
  2654. pm8001_dbg(pm8001_ha, FAIL,
  2655. "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
  2656. ts->resp = SAS_TASK_UNDELIVERED;
  2657. ts->stat = SAS_DEV_NO_RESPONSE;
  2658. if (!t->uldd_task) {
  2659. pm8001_handle_event(pm8001_ha,
  2660. pm8001_dev,
  2661. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2662. ts->resp = SAS_TASK_COMPLETE;
  2663. ts->stat = SAS_QUEUE_FULL;
  2664. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2665. return;
  2666. }
  2667. break;
  2668. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2669. pm8001_dbg(pm8001_ha, IO,
  2670. "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
  2671. ts->resp = SAS_TASK_UNDELIVERED;
  2672. ts->stat = SAS_OPEN_REJECT;
  2673. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2674. break;
  2675. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2676. pm8001_dbg(pm8001_ha, IO,
  2677. "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
  2678. ts->resp = SAS_TASK_COMPLETE;
  2679. ts->stat = SAS_OPEN_REJECT;
  2680. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2681. break;
  2682. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2683. pm8001_dbg(pm8001_ha, IO,
  2684. "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
  2685. ts->resp = SAS_TASK_COMPLETE;
  2686. ts->stat = SAS_OPEN_REJECT;
  2687. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2688. break;
  2689. case IO_XFER_ERROR_NAK_RECEIVED:
  2690. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
  2691. ts->resp = SAS_TASK_COMPLETE;
  2692. ts->stat = SAS_NAK_R_ERR;
  2693. break;
  2694. case IO_XFER_ERROR_PEER_ABORTED:
  2695. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
  2696. ts->resp = SAS_TASK_COMPLETE;
  2697. ts->stat = SAS_NAK_R_ERR;
  2698. break;
  2699. case IO_XFER_ERROR_REJECTED_NCQ_MODE:
  2700. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
  2701. ts->resp = SAS_TASK_COMPLETE;
  2702. ts->stat = SAS_DATA_UNDERRUN;
  2703. break;
  2704. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2705. pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
  2706. ts->resp = SAS_TASK_COMPLETE;
  2707. ts->stat = SAS_OPEN_TO;
  2708. break;
  2709. case IO_XFER_ERROR_UNEXPECTED_PHASE:
  2710. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
  2711. ts->resp = SAS_TASK_COMPLETE;
  2712. ts->stat = SAS_OPEN_TO;
  2713. break;
  2714. case IO_XFER_ERROR_XFER_RDY_OVERRUN:
  2715. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
  2716. ts->resp = SAS_TASK_COMPLETE;
  2717. ts->stat = SAS_OPEN_TO;
  2718. break;
  2719. case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
  2720. pm8001_dbg(pm8001_ha, IO,
  2721. "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
  2722. ts->resp = SAS_TASK_COMPLETE;
  2723. ts->stat = SAS_OPEN_TO;
  2724. break;
  2725. case IO_XFER_ERROR_OFFSET_MISMATCH:
  2726. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
  2727. ts->resp = SAS_TASK_COMPLETE;
  2728. ts->stat = SAS_OPEN_TO;
  2729. break;
  2730. case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
  2731. pm8001_dbg(pm8001_ha, IO,
  2732. "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
  2733. ts->resp = SAS_TASK_COMPLETE;
  2734. ts->stat = SAS_OPEN_TO;
  2735. break;
  2736. case IO_XFER_CMD_FRAME_ISSUED:
  2737. pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
  2738. break;
  2739. case IO_XFER_PIO_SETUP_ERROR:
  2740. pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
  2741. ts->resp = SAS_TASK_COMPLETE;
  2742. ts->stat = SAS_OPEN_TO;
  2743. break;
  2744. case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
  2745. pm8001_dbg(pm8001_ha, FAIL,
  2746. "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
  2747. /* TBC: used default set values */
  2748. ts->resp = SAS_TASK_COMPLETE;
  2749. ts->stat = SAS_OPEN_TO;
  2750. break;
  2751. case IO_XFER_DMA_ACTIVATE_TIMEOUT:
  2752. pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
  2753. /* TBC: used default set values */
  2754. ts->resp = SAS_TASK_COMPLETE;
  2755. ts->stat = SAS_OPEN_TO;
  2756. break;
  2757. default:
  2758. pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
  2759. /* not allowed case. Therefore, return failed status */
  2760. ts->resp = SAS_TASK_COMPLETE;
  2761. ts->stat = SAS_OPEN_TO;
  2762. break;
  2763. }
  2764. spin_lock_irqsave(&t->task_state_lock, flags);
  2765. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2766. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2767. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2768. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2769. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2770. pm8001_dbg(pm8001_ha, FAIL,
  2771. "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2772. t, event, ts->resp, ts->stat);
  2773. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2774. } else {
  2775. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2776. pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
  2777. }
  2778. }
  2779. /*See the comments for mpi_ssp_completion */
  2780. static void
  2781. mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2782. {
  2783. u32 param, i;
  2784. struct sas_task *t;
  2785. struct pm8001_ccb_info *ccb;
  2786. unsigned long flags;
  2787. u32 status;
  2788. u32 tag;
  2789. struct smp_completion_resp *psmpPayload;
  2790. struct task_status_struct *ts;
  2791. struct pm8001_device *pm8001_dev;
  2792. char *pdma_respaddr = NULL;
  2793. psmpPayload = (struct smp_completion_resp *)(piomb + 4);
  2794. status = le32_to_cpu(psmpPayload->status);
  2795. tag = le32_to_cpu(psmpPayload->tag);
  2796. ccb = &pm8001_ha->ccb_info[tag];
  2797. param = le32_to_cpu(psmpPayload->param);
  2798. t = ccb->task;
  2799. ts = &t->task_status;
  2800. pm8001_dev = ccb->device;
  2801. if (status)
  2802. pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
  2803. if (unlikely(!t || !t->lldd_task || !t->dev))
  2804. return;
  2805. pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
  2806. switch (status) {
  2807. case IO_SUCCESS:
  2808. pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
  2809. ts->resp = SAS_TASK_COMPLETE;
  2810. ts->stat = SAM_STAT_GOOD;
  2811. if (pm8001_dev)
  2812. atomic_dec(&pm8001_dev->running_req);
  2813. if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
  2814. pm8001_dbg(pm8001_ha, IO,
  2815. "DIRECT RESPONSE Length:%d\n",
  2816. param);
  2817. pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
  2818. ((u64)sg_dma_address
  2819. (&t->smp_task.smp_resp))));
  2820. for (i = 0; i < param; i++) {
  2821. *(pdma_respaddr+i) = psmpPayload->_r_a[i];
  2822. pm8001_dbg(pm8001_ha, IO,
  2823. "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
  2824. i, *(pdma_respaddr + i),
  2825. psmpPayload->_r_a[i]);
  2826. }
  2827. }
  2828. break;
  2829. case IO_ABORTED:
  2830. pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
  2831. ts->resp = SAS_TASK_COMPLETE;
  2832. ts->stat = SAS_ABORTED_TASK;
  2833. if (pm8001_dev)
  2834. atomic_dec(&pm8001_dev->running_req);
  2835. break;
  2836. case IO_OVERFLOW:
  2837. pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
  2838. ts->resp = SAS_TASK_COMPLETE;
  2839. ts->stat = SAS_DATA_OVERRUN;
  2840. ts->residual = 0;
  2841. if (pm8001_dev)
  2842. atomic_dec(&pm8001_dev->running_req);
  2843. break;
  2844. case IO_NO_DEVICE:
  2845. pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
  2846. ts->resp = SAS_TASK_COMPLETE;
  2847. ts->stat = SAS_PHY_DOWN;
  2848. break;
  2849. case IO_ERROR_HW_TIMEOUT:
  2850. pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
  2851. ts->resp = SAS_TASK_COMPLETE;
  2852. ts->stat = SAM_STAT_BUSY;
  2853. break;
  2854. case IO_XFER_ERROR_BREAK:
  2855. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
  2856. ts->resp = SAS_TASK_COMPLETE;
  2857. ts->stat = SAM_STAT_BUSY;
  2858. break;
  2859. case IO_XFER_ERROR_PHY_NOT_READY:
  2860. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
  2861. ts->resp = SAS_TASK_COMPLETE;
  2862. ts->stat = SAM_STAT_BUSY;
  2863. break;
  2864. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2865. pm8001_dbg(pm8001_ha, IO,
  2866. "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
  2867. ts->resp = SAS_TASK_COMPLETE;
  2868. ts->stat = SAS_OPEN_REJECT;
  2869. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2870. break;
  2871. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2872. pm8001_dbg(pm8001_ha, IO,
  2873. "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
  2874. ts->resp = SAS_TASK_COMPLETE;
  2875. ts->stat = SAS_OPEN_REJECT;
  2876. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2877. break;
  2878. case IO_OPEN_CNX_ERROR_BREAK:
  2879. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
  2880. ts->resp = SAS_TASK_COMPLETE;
  2881. ts->stat = SAS_OPEN_REJECT;
  2882. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2883. break;
  2884. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2885. case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
  2886. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
  2887. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
  2888. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
  2889. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
  2890. pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
  2891. ts->resp = SAS_TASK_COMPLETE;
  2892. ts->stat = SAS_OPEN_REJECT;
  2893. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2894. pm8001_handle_event(pm8001_ha,
  2895. pm8001_dev,
  2896. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2897. break;
  2898. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2899. pm8001_dbg(pm8001_ha, IO,
  2900. "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
  2901. ts->resp = SAS_TASK_COMPLETE;
  2902. ts->stat = SAS_OPEN_REJECT;
  2903. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2904. break;
  2905. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2906. pm8001_dbg(pm8001_ha, IO,
  2907. "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
  2908. ts->resp = SAS_TASK_COMPLETE;
  2909. ts->stat = SAS_OPEN_REJECT;
  2910. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2911. break;
  2912. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2913. pm8001_dbg(pm8001_ha, IO,
  2914. "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
  2915. ts->resp = SAS_TASK_COMPLETE;
  2916. ts->stat = SAS_OPEN_REJECT;
  2917. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2918. break;
  2919. case IO_XFER_ERROR_RX_FRAME:
  2920. pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
  2921. ts->resp = SAS_TASK_COMPLETE;
  2922. ts->stat = SAS_DEV_NO_RESPONSE;
  2923. break;
  2924. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2925. pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
  2926. ts->resp = SAS_TASK_COMPLETE;
  2927. ts->stat = SAS_OPEN_REJECT;
  2928. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2929. break;
  2930. case IO_ERROR_INTERNAL_SMP_RESOURCE:
  2931. pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
  2932. ts->resp = SAS_TASK_COMPLETE;
  2933. ts->stat = SAS_QUEUE_FULL;
  2934. break;
  2935. case IO_PORT_IN_RESET:
  2936. pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
  2937. ts->resp = SAS_TASK_COMPLETE;
  2938. ts->stat = SAS_OPEN_REJECT;
  2939. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2940. break;
  2941. case IO_DS_NON_OPERATIONAL:
  2942. pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
  2943. ts->resp = SAS_TASK_COMPLETE;
  2944. ts->stat = SAS_DEV_NO_RESPONSE;
  2945. break;
  2946. case IO_DS_IN_RECOVERY:
  2947. pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
  2948. ts->resp = SAS_TASK_COMPLETE;
  2949. ts->stat = SAS_OPEN_REJECT;
  2950. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2951. break;
  2952. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  2953. pm8001_dbg(pm8001_ha, IO,
  2954. "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
  2955. ts->resp = SAS_TASK_COMPLETE;
  2956. ts->stat = SAS_OPEN_REJECT;
  2957. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2958. break;
  2959. default:
  2960. pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
  2961. ts->resp = SAS_TASK_COMPLETE;
  2962. ts->stat = SAS_DEV_NO_RESPONSE;
  2963. /* not allowed case. Therefore, return failed status */
  2964. break;
  2965. }
  2966. spin_lock_irqsave(&t->task_state_lock, flags);
  2967. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2968. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2969. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2970. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2971. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2972. pm8001_dbg(pm8001_ha, FAIL,
  2973. "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
  2974. t, status, ts->resp, ts->stat);
  2975. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2976. } else {
  2977. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2978. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2979. mb();/* in order to force CPU ordering */
  2980. t->task_done(t);
  2981. }
  2982. }
  2983. /**
  2984. * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
  2985. * @pm8001_ha: our hba card information
  2986. * @Qnum: the outbound queue message number.
  2987. * @SEA: source of event to ack
  2988. * @port_id: port id.
  2989. * @phyId: phy id.
  2990. * @param0: parameter 0.
  2991. * @param1: parameter 1.
  2992. */
  2993. static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
  2994. u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
  2995. {
  2996. struct hw_event_ack_req payload;
  2997. u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
  2998. struct inbound_queue_table *circularQ;
  2999. memset((u8 *)&payload, 0, sizeof(payload));
  3000. circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
  3001. payload.tag = cpu_to_le32(1);
  3002. payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
  3003. ((phyId & 0xFF) << 24) | (port_id & 0xFF));
  3004. payload.param0 = cpu_to_le32(param0);
  3005. payload.param1 = cpu_to_le32(param1);
  3006. pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  3007. sizeof(payload), 0);
  3008. }
  3009. static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
  3010. u32 phyId, u32 phy_op);
  3011. static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
  3012. void *piomb)
  3013. {
  3014. struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
  3015. u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
  3016. u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
  3017. u32 lr_status_evt_portid =
  3018. le32_to_cpu(pPayload->lr_status_evt_portid);
  3019. u8 deviceType = pPayload->sas_identify.dev_type;
  3020. u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
  3021. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3022. u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
  3023. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3024. if (deviceType == SAS_END_DEVICE) {
  3025. pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
  3026. PHY_NOTIFY_ENABLE_SPINUP);
  3027. }
  3028. port->wide_port_phymap |= (1U << phy_id);
  3029. pm8001_get_lrate_mode(phy, link_rate);
  3030. phy->sas_phy.oob_mode = SAS_OOB_MODE;
  3031. phy->phy_state = PHY_STATE_LINK_UP_SPCV;
  3032. phy->phy_attached = 1;
  3033. }
  3034. /**
  3035. * hw_event_sas_phy_up -FW tells me a SAS phy up event.
  3036. * @pm8001_ha: our hba card information
  3037. * @piomb: IO message buffer
  3038. */
  3039. static void
  3040. hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3041. {
  3042. struct hw_event_resp *pPayload =
  3043. (struct hw_event_resp *)(piomb + 4);
  3044. u32 lr_status_evt_portid =
  3045. le32_to_cpu(pPayload->lr_status_evt_portid);
  3046. u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
  3047. u8 link_rate =
  3048. (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
  3049. u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
  3050. u8 phy_id =
  3051. (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
  3052. u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
  3053. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3054. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3055. unsigned long flags;
  3056. u8 deviceType = pPayload->sas_identify.dev_type;
  3057. port->port_state = portstate;
  3058. port->wide_port_phymap |= (1U << phy_id);
  3059. phy->phy_state = PHY_STATE_LINK_UP_SPCV;
  3060. pm8001_dbg(pm8001_ha, MSG,
  3061. "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
  3062. port_id, phy_id, link_rate, portstate, deviceType);
  3063. switch (deviceType) {
  3064. case SAS_PHY_UNUSED:
  3065. pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
  3066. break;
  3067. case SAS_END_DEVICE:
  3068. pm8001_dbg(pm8001_ha, MSG, "end device.\n");
  3069. pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
  3070. PHY_NOTIFY_ENABLE_SPINUP);
  3071. port->port_attached = 1;
  3072. pm8001_get_lrate_mode(phy, link_rate);
  3073. break;
  3074. case SAS_EDGE_EXPANDER_DEVICE:
  3075. pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
  3076. port->port_attached = 1;
  3077. pm8001_get_lrate_mode(phy, link_rate);
  3078. break;
  3079. case SAS_FANOUT_EXPANDER_DEVICE:
  3080. pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
  3081. port->port_attached = 1;
  3082. pm8001_get_lrate_mode(phy, link_rate);
  3083. break;
  3084. default:
  3085. pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
  3086. deviceType);
  3087. break;
  3088. }
  3089. phy->phy_type |= PORT_TYPE_SAS;
  3090. phy->identify.device_type = deviceType;
  3091. phy->phy_attached = 1;
  3092. if (phy->identify.device_type == SAS_END_DEVICE)
  3093. phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
  3094. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  3095. phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
  3096. phy->sas_phy.oob_mode = SAS_OOB_MODE;
  3097. sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
  3098. spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
  3099. memcpy(phy->frame_rcvd, &pPayload->sas_identify,
  3100. sizeof(struct sas_identify_frame)-4);
  3101. phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
  3102. pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
  3103. spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
  3104. if (pm8001_ha->flags == PM8001F_RUN_TIME)
  3105. mdelay(200); /* delay a moment to wait for disk to spin up */
  3106. pm8001_bytes_dmaed(pm8001_ha, phy_id);
  3107. }
  3108. /**
  3109. * hw_event_sata_phy_up -FW tells me a SATA phy up event.
  3110. * @pm8001_ha: our hba card information
  3111. * @piomb: IO message buffer
  3112. */
  3113. static void
  3114. hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3115. {
  3116. struct hw_event_resp *pPayload =
  3117. (struct hw_event_resp *)(piomb + 4);
  3118. u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
  3119. u32 lr_status_evt_portid =
  3120. le32_to_cpu(pPayload->lr_status_evt_portid);
  3121. u8 link_rate =
  3122. (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
  3123. u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
  3124. u8 phy_id =
  3125. (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
  3126. u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
  3127. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3128. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3129. unsigned long flags;
  3130. pm8001_dbg(pm8001_ha, DEVIO,
  3131. "port id %d, phy id %d link_rate %d portstate 0x%x\n",
  3132. port_id, phy_id, link_rate, portstate);
  3133. port->port_state = portstate;
  3134. phy->phy_state = PHY_STATE_LINK_UP_SPCV;
  3135. port->port_attached = 1;
  3136. pm8001_get_lrate_mode(phy, link_rate);
  3137. phy->phy_type |= PORT_TYPE_SATA;
  3138. phy->phy_attached = 1;
  3139. phy->sas_phy.oob_mode = SATA_OOB_MODE;
  3140. sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
  3141. spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
  3142. memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
  3143. sizeof(struct dev_to_host_fis));
  3144. phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
  3145. phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
  3146. phy->identify.device_type = SAS_SATA_DEV;
  3147. pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
  3148. spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
  3149. pm8001_bytes_dmaed(pm8001_ha, phy_id);
  3150. }
  3151. /**
  3152. * hw_event_phy_down -we should notify the libsas the phy is down.
  3153. * @pm8001_ha: our hba card information
  3154. * @piomb: IO message buffer
  3155. */
  3156. static void
  3157. hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3158. {
  3159. struct hw_event_resp *pPayload =
  3160. (struct hw_event_resp *)(piomb + 4);
  3161. u32 lr_status_evt_portid =
  3162. le32_to_cpu(pPayload->lr_status_evt_portid);
  3163. u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
  3164. u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
  3165. u8 phy_id =
  3166. (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
  3167. u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
  3168. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3169. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3170. u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
  3171. port->port_state = portstate;
  3172. phy->identify.device_type = 0;
  3173. phy->phy_attached = 0;
  3174. switch (portstate) {
  3175. case PORT_VALID:
  3176. break;
  3177. case PORT_INVALID:
  3178. pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
  3179. port_id);
  3180. pm8001_dbg(pm8001_ha, MSG,
  3181. " Last phy Down and port invalid\n");
  3182. if (port_sata) {
  3183. phy->phy_type = 0;
  3184. port->port_attached = 0;
  3185. pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  3186. port_id, phy_id, 0, 0);
  3187. }
  3188. sas_phy_disconnected(&phy->sas_phy);
  3189. break;
  3190. case PORT_IN_RESET:
  3191. pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
  3192. port_id);
  3193. break;
  3194. case PORT_NOT_ESTABLISHED:
  3195. pm8001_dbg(pm8001_ha, MSG,
  3196. " Phy Down and PORT_NOT_ESTABLISHED\n");
  3197. port->port_attached = 0;
  3198. break;
  3199. case PORT_LOSTCOMM:
  3200. pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
  3201. pm8001_dbg(pm8001_ha, MSG,
  3202. " Last phy Down and port invalid\n");
  3203. if (port_sata) {
  3204. port->port_attached = 0;
  3205. phy->phy_type = 0;
  3206. pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  3207. port_id, phy_id, 0, 0);
  3208. }
  3209. sas_phy_disconnected(&phy->sas_phy);
  3210. break;
  3211. default:
  3212. port->port_attached = 0;
  3213. pm8001_dbg(pm8001_ha, DEVIO,
  3214. " Phy Down and(default) = 0x%x\n",
  3215. portstate);
  3216. break;
  3217. }
  3218. if (port_sata && (portstate != PORT_IN_RESET))
  3219. sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
  3220. }
  3221. static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3222. {
  3223. struct phy_start_resp *pPayload =
  3224. (struct phy_start_resp *)(piomb + 4);
  3225. u32 status =
  3226. le32_to_cpu(pPayload->status);
  3227. u32 phy_id =
  3228. le32_to_cpu(pPayload->phyid);
  3229. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3230. pm8001_dbg(pm8001_ha, INIT,
  3231. "phy start resp status:0x%x, phyid:0x%x\n",
  3232. status, phy_id);
  3233. if (status == 0)
  3234. phy->phy_state = PHY_LINK_DOWN;
  3235. if (pm8001_ha->flags == PM8001F_RUN_TIME &&
  3236. phy->enable_completion != NULL) {
  3237. complete(phy->enable_completion);
  3238. phy->enable_completion = NULL;
  3239. }
  3240. return 0;
  3241. }
  3242. /**
  3243. * mpi_thermal_hw_event -The hw event has come.
  3244. * @pm8001_ha: our hba card information
  3245. * @piomb: IO message buffer
  3246. */
  3247. static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3248. {
  3249. struct thermal_hw_event *pPayload =
  3250. (struct thermal_hw_event *)(piomb + 4);
  3251. u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
  3252. u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
  3253. if (thermal_event & 0x40) {
  3254. pm8001_dbg(pm8001_ha, IO,
  3255. "Thermal Event: Local high temperature violated!\n");
  3256. pm8001_dbg(pm8001_ha, IO,
  3257. "Thermal Event: Measured local high temperature %d\n",
  3258. ((rht_lht & 0xFF00) >> 8));
  3259. }
  3260. if (thermal_event & 0x10) {
  3261. pm8001_dbg(pm8001_ha, IO,
  3262. "Thermal Event: Remote high temperature violated!\n");
  3263. pm8001_dbg(pm8001_ha, IO,
  3264. "Thermal Event: Measured remote high temperature %d\n",
  3265. ((rht_lht & 0xFF000000) >> 24));
  3266. }
  3267. return 0;
  3268. }
  3269. /**
  3270. * mpi_hw_event -The hw event has come.
  3271. * @pm8001_ha: our hba card information
  3272. * @piomb: IO message buffer
  3273. */
  3274. static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3275. {
  3276. unsigned long flags, i;
  3277. struct hw_event_resp *pPayload =
  3278. (struct hw_event_resp *)(piomb + 4);
  3279. u32 lr_status_evt_portid =
  3280. le32_to_cpu(pPayload->lr_status_evt_portid);
  3281. u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
  3282. u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
  3283. u8 phy_id =
  3284. (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
  3285. u16 eventType =
  3286. (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
  3287. u8 status =
  3288. (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
  3289. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  3290. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3291. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3292. struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
  3293. pm8001_dbg(pm8001_ha, DEV,
  3294. "portid:%d phyid:%d event:0x%x status:0x%x\n",
  3295. port_id, phy_id, eventType, status);
  3296. switch (eventType) {
  3297. case HW_EVENT_SAS_PHY_UP:
  3298. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
  3299. hw_event_sas_phy_up(pm8001_ha, piomb);
  3300. break;
  3301. case HW_EVENT_SATA_PHY_UP:
  3302. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
  3303. hw_event_sata_phy_up(pm8001_ha, piomb);
  3304. break;
  3305. case HW_EVENT_SATA_SPINUP_HOLD:
  3306. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
  3307. sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
  3308. break;
  3309. case HW_EVENT_PHY_DOWN:
  3310. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
  3311. hw_event_phy_down(pm8001_ha, piomb);
  3312. if (pm8001_ha->reset_in_progress) {
  3313. pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
  3314. return 0;
  3315. }
  3316. phy->phy_attached = 0;
  3317. phy->phy_state = PHY_LINK_DISABLE;
  3318. break;
  3319. case HW_EVENT_PORT_INVALID:
  3320. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
  3321. sas_phy_disconnected(sas_phy);
  3322. phy->phy_attached = 0;
  3323. sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3324. break;
  3325. /* the broadcast change primitive received, tell the LIBSAS this event
  3326. to revalidate the sas domain*/
  3327. case HW_EVENT_BROADCAST_CHANGE:
  3328. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
  3329. pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
  3330. port_id, phy_id, 1, 0);
  3331. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3332. sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
  3333. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3334. sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3335. break;
  3336. case HW_EVENT_PHY_ERROR:
  3337. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
  3338. sas_phy_disconnected(&phy->sas_phy);
  3339. phy->phy_attached = 0;
  3340. sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
  3341. break;
  3342. case HW_EVENT_BROADCAST_EXP:
  3343. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
  3344. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3345. sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
  3346. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3347. sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3348. break;
  3349. case HW_EVENT_LINK_ERR_INVALID_DWORD:
  3350. pm8001_dbg(pm8001_ha, MSG,
  3351. "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
  3352. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3353. HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
  3354. break;
  3355. case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
  3356. pm8001_dbg(pm8001_ha, MSG,
  3357. "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
  3358. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3359. HW_EVENT_LINK_ERR_DISPARITY_ERROR,
  3360. port_id, phy_id, 0, 0);
  3361. break;
  3362. case HW_EVENT_LINK_ERR_CODE_VIOLATION:
  3363. pm8001_dbg(pm8001_ha, MSG,
  3364. "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
  3365. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3366. HW_EVENT_LINK_ERR_CODE_VIOLATION,
  3367. port_id, phy_id, 0, 0);
  3368. break;
  3369. case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
  3370. pm8001_dbg(pm8001_ha, MSG,
  3371. "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
  3372. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3373. HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
  3374. port_id, phy_id, 0, 0);
  3375. break;
  3376. case HW_EVENT_MALFUNCTION:
  3377. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
  3378. break;
  3379. case HW_EVENT_BROADCAST_SES:
  3380. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
  3381. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3382. sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
  3383. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3384. sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3385. break;
  3386. case HW_EVENT_INBOUND_CRC_ERROR:
  3387. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
  3388. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3389. HW_EVENT_INBOUND_CRC_ERROR,
  3390. port_id, phy_id, 0, 0);
  3391. break;
  3392. case HW_EVENT_HARD_RESET_RECEIVED:
  3393. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
  3394. sas_notify_port_event(sas_phy, PORTE_HARD_RESET);
  3395. break;
  3396. case HW_EVENT_ID_FRAME_TIMEOUT:
  3397. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
  3398. sas_phy_disconnected(sas_phy);
  3399. phy->phy_attached = 0;
  3400. sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3401. break;
  3402. case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
  3403. pm8001_dbg(pm8001_ha, MSG,
  3404. "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
  3405. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3406. HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
  3407. port_id, phy_id, 0, 0);
  3408. sas_phy_disconnected(sas_phy);
  3409. phy->phy_attached = 0;
  3410. sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3411. break;
  3412. case HW_EVENT_PORT_RESET_TIMER_TMO:
  3413. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
  3414. pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  3415. port_id, phy_id, 0, 0);
  3416. sas_phy_disconnected(sas_phy);
  3417. phy->phy_attached = 0;
  3418. sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3419. if (pm8001_ha->phy[phy_id].reset_completion) {
  3420. pm8001_ha->phy[phy_id].port_reset_status =
  3421. PORT_RESET_TMO;
  3422. complete(pm8001_ha->phy[phy_id].reset_completion);
  3423. pm8001_ha->phy[phy_id].reset_completion = NULL;
  3424. }
  3425. break;
  3426. case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
  3427. pm8001_dbg(pm8001_ha, MSG,
  3428. "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
  3429. pm80xx_hw_event_ack_req(pm8001_ha, 0,
  3430. HW_EVENT_PORT_RECOVERY_TIMER_TMO,
  3431. port_id, phy_id, 0, 0);
  3432. for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
  3433. if (port->wide_port_phymap & (1 << i)) {
  3434. phy = &pm8001_ha->phy[i];
  3435. sas_notify_phy_event(&phy->sas_phy,
  3436. PHYE_LOSS_OF_SIGNAL);
  3437. port->wide_port_phymap &= ~(1 << i);
  3438. }
  3439. }
  3440. break;
  3441. case HW_EVENT_PORT_RECOVER:
  3442. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
  3443. hw_event_port_recover(pm8001_ha, piomb);
  3444. break;
  3445. case HW_EVENT_PORT_RESET_COMPLETE:
  3446. pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
  3447. if (pm8001_ha->phy[phy_id].reset_completion) {
  3448. pm8001_ha->phy[phy_id].port_reset_status =
  3449. PORT_RESET_SUCCESS;
  3450. complete(pm8001_ha->phy[phy_id].reset_completion);
  3451. pm8001_ha->phy[phy_id].reset_completion = NULL;
  3452. }
  3453. break;
  3454. case EVENT_BROADCAST_ASYNCH_EVENT:
  3455. pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
  3456. break;
  3457. default:
  3458. pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
  3459. eventType);
  3460. break;
  3461. }
  3462. return 0;
  3463. }
  3464. /**
  3465. * mpi_phy_stop_resp - SPCv specific
  3466. * @pm8001_ha: our hba card information
  3467. * @piomb: IO message buffer
  3468. */
  3469. static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3470. {
  3471. struct phy_stop_resp *pPayload =
  3472. (struct phy_stop_resp *)(piomb + 4);
  3473. u32 status =
  3474. le32_to_cpu(pPayload->status);
  3475. u32 phyid =
  3476. le32_to_cpu(pPayload->phyid) & 0xFF;
  3477. struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
  3478. pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
  3479. phyid, status);
  3480. if (status == PHY_STOP_SUCCESS ||
  3481. status == PHY_STOP_ERR_DEVICE_ATTACHED)
  3482. phy->phy_state = PHY_LINK_DISABLE;
  3483. return 0;
  3484. }
  3485. /**
  3486. * mpi_set_controller_config_resp - SPCv specific
  3487. * @pm8001_ha: our hba card information
  3488. * @piomb: IO message buffer
  3489. */
  3490. static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
  3491. void *piomb)
  3492. {
  3493. struct set_ctrl_cfg_resp *pPayload =
  3494. (struct set_ctrl_cfg_resp *)(piomb + 4);
  3495. u32 status = le32_to_cpu(pPayload->status);
  3496. u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
  3497. pm8001_dbg(pm8001_ha, MSG,
  3498. "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
  3499. status, err_qlfr_pgcd);
  3500. return 0;
  3501. }
  3502. /**
  3503. * mpi_get_controller_config_resp - SPCv specific
  3504. * @pm8001_ha: our hba card information
  3505. * @piomb: IO message buffer
  3506. */
  3507. static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
  3508. void *piomb)
  3509. {
  3510. pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
  3511. return 0;
  3512. }
  3513. /**
  3514. * mpi_get_phy_profile_resp - SPCv specific
  3515. * @pm8001_ha: our hba card information
  3516. * @piomb: IO message buffer
  3517. */
  3518. static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
  3519. void *piomb)
  3520. {
  3521. pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
  3522. return 0;
  3523. }
  3524. /**
  3525. * mpi_flash_op_ext_resp - SPCv specific
  3526. * @pm8001_ha: our hba card information
  3527. * @piomb: IO message buffer
  3528. */
  3529. static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3530. {
  3531. pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
  3532. return 0;
  3533. }
  3534. /**
  3535. * mpi_set_phy_profile_resp - SPCv specific
  3536. * @pm8001_ha: our hba card information
  3537. * @piomb: IO message buffer
  3538. */
  3539. static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
  3540. void *piomb)
  3541. {
  3542. u32 tag;
  3543. u8 page_code;
  3544. int rc = 0;
  3545. struct set_phy_profile_resp *pPayload =
  3546. (struct set_phy_profile_resp *)(piomb + 4);
  3547. u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
  3548. u32 status = le32_to_cpu(pPayload->status);
  3549. tag = le32_to_cpu(pPayload->tag);
  3550. page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
  3551. if (status) {
  3552. /* status is FAILED */
  3553. pm8001_dbg(pm8001_ha, FAIL,
  3554. "PhyProfile command failed with status 0x%08X\n",
  3555. status);
  3556. rc = -1;
  3557. } else {
  3558. if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
  3559. pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
  3560. page_code);
  3561. rc = -1;
  3562. }
  3563. }
  3564. pm8001_tag_free(pm8001_ha, tag);
  3565. return rc;
  3566. }
  3567. /**
  3568. * mpi_kek_management_resp - SPCv specific
  3569. * @pm8001_ha: our hba card information
  3570. * @piomb: IO message buffer
  3571. */
  3572. static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
  3573. void *piomb)
  3574. {
  3575. struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
  3576. u32 status = le32_to_cpu(pPayload->status);
  3577. u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
  3578. u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
  3579. pm8001_dbg(pm8001_ha, MSG,
  3580. "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
  3581. status, kidx_new_curr_ksop, err_qlfr);
  3582. return 0;
  3583. }
  3584. /**
  3585. * mpi_dek_management_resp - SPCv specific
  3586. * @pm8001_ha: our hba card information
  3587. * @piomb: IO message buffer
  3588. */
  3589. static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
  3590. void *piomb)
  3591. {
  3592. pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
  3593. return 0;
  3594. }
  3595. /**
  3596. * ssp_coalesced_comp_resp - SPCv specific
  3597. * @pm8001_ha: our hba card information
  3598. * @piomb: IO message buffer
  3599. */
  3600. static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
  3601. void *piomb)
  3602. {
  3603. pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
  3604. return 0;
  3605. }
  3606. /**
  3607. * process_one_iomb - process one outbound Queue memory block
  3608. * @pm8001_ha: our hba card information
  3609. * @piomb: IO message buffer
  3610. */
  3611. static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3612. {
  3613. __le32 pHeader = *(__le32 *)piomb;
  3614. u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
  3615. switch (opc) {
  3616. case OPC_OUB_ECHO:
  3617. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
  3618. break;
  3619. case OPC_OUB_HW_EVENT:
  3620. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
  3621. mpi_hw_event(pm8001_ha, piomb);
  3622. break;
  3623. case OPC_OUB_THERM_HW_EVENT:
  3624. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
  3625. mpi_thermal_hw_event(pm8001_ha, piomb);
  3626. break;
  3627. case OPC_OUB_SSP_COMP:
  3628. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
  3629. mpi_ssp_completion(pm8001_ha, piomb);
  3630. break;
  3631. case OPC_OUB_SMP_COMP:
  3632. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
  3633. mpi_smp_completion(pm8001_ha, piomb);
  3634. break;
  3635. case OPC_OUB_LOCAL_PHY_CNTRL:
  3636. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
  3637. pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
  3638. break;
  3639. case OPC_OUB_DEV_REGIST:
  3640. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
  3641. pm8001_mpi_reg_resp(pm8001_ha, piomb);
  3642. break;
  3643. case OPC_OUB_DEREG_DEV:
  3644. pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
  3645. pm8001_mpi_dereg_resp(pm8001_ha, piomb);
  3646. break;
  3647. case OPC_OUB_GET_DEV_HANDLE:
  3648. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
  3649. break;
  3650. case OPC_OUB_SATA_COMP:
  3651. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
  3652. mpi_sata_completion(pm8001_ha, piomb);
  3653. break;
  3654. case OPC_OUB_SATA_EVENT:
  3655. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
  3656. mpi_sata_event(pm8001_ha, piomb);
  3657. break;
  3658. case OPC_OUB_SSP_EVENT:
  3659. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
  3660. mpi_ssp_event(pm8001_ha, piomb);
  3661. break;
  3662. case OPC_OUB_DEV_HANDLE_ARRIV:
  3663. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
  3664. /*This is for target*/
  3665. break;
  3666. case OPC_OUB_SSP_RECV_EVENT:
  3667. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
  3668. /*This is for target*/
  3669. break;
  3670. case OPC_OUB_FW_FLASH_UPDATE:
  3671. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
  3672. pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
  3673. break;
  3674. case OPC_OUB_GPIO_RESPONSE:
  3675. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
  3676. break;
  3677. case OPC_OUB_GPIO_EVENT:
  3678. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
  3679. break;
  3680. case OPC_OUB_GENERAL_EVENT:
  3681. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
  3682. pm8001_mpi_general_event(pm8001_ha, piomb);
  3683. break;
  3684. case OPC_OUB_SSP_ABORT_RSP:
  3685. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
  3686. pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
  3687. break;
  3688. case OPC_OUB_SATA_ABORT_RSP:
  3689. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
  3690. pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
  3691. break;
  3692. case OPC_OUB_SAS_DIAG_MODE_START_END:
  3693. pm8001_dbg(pm8001_ha, MSG,
  3694. "OPC_OUB_SAS_DIAG_MODE_START_END\n");
  3695. break;
  3696. case OPC_OUB_SAS_DIAG_EXECUTE:
  3697. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
  3698. break;
  3699. case OPC_OUB_GET_TIME_STAMP:
  3700. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
  3701. break;
  3702. case OPC_OUB_SAS_HW_EVENT_ACK:
  3703. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
  3704. break;
  3705. case OPC_OUB_PORT_CONTROL:
  3706. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
  3707. break;
  3708. case OPC_OUB_SMP_ABORT_RSP:
  3709. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
  3710. pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
  3711. break;
  3712. case OPC_OUB_GET_NVMD_DATA:
  3713. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
  3714. pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
  3715. break;
  3716. case OPC_OUB_SET_NVMD_DATA:
  3717. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
  3718. pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
  3719. break;
  3720. case OPC_OUB_DEVICE_HANDLE_REMOVAL:
  3721. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
  3722. break;
  3723. case OPC_OUB_SET_DEVICE_STATE:
  3724. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
  3725. pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
  3726. break;
  3727. case OPC_OUB_GET_DEVICE_STATE:
  3728. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
  3729. break;
  3730. case OPC_OUB_SET_DEV_INFO:
  3731. pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
  3732. break;
  3733. /* spcv specifc commands */
  3734. case OPC_OUB_PHY_START_RESP:
  3735. pm8001_dbg(pm8001_ha, MSG,
  3736. "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
  3737. mpi_phy_start_resp(pm8001_ha, piomb);
  3738. break;
  3739. case OPC_OUB_PHY_STOP_RESP:
  3740. pm8001_dbg(pm8001_ha, MSG,
  3741. "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
  3742. mpi_phy_stop_resp(pm8001_ha, piomb);
  3743. break;
  3744. case OPC_OUB_SET_CONTROLLER_CONFIG:
  3745. pm8001_dbg(pm8001_ha, MSG,
  3746. "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
  3747. mpi_set_controller_config_resp(pm8001_ha, piomb);
  3748. break;
  3749. case OPC_OUB_GET_CONTROLLER_CONFIG:
  3750. pm8001_dbg(pm8001_ha, MSG,
  3751. "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
  3752. mpi_get_controller_config_resp(pm8001_ha, piomb);
  3753. break;
  3754. case OPC_OUB_GET_PHY_PROFILE:
  3755. pm8001_dbg(pm8001_ha, MSG,
  3756. "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
  3757. mpi_get_phy_profile_resp(pm8001_ha, piomb);
  3758. break;
  3759. case OPC_OUB_FLASH_OP_EXT:
  3760. pm8001_dbg(pm8001_ha, MSG,
  3761. "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
  3762. mpi_flash_op_ext_resp(pm8001_ha, piomb);
  3763. break;
  3764. case OPC_OUB_SET_PHY_PROFILE:
  3765. pm8001_dbg(pm8001_ha, MSG,
  3766. "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
  3767. mpi_set_phy_profile_resp(pm8001_ha, piomb);
  3768. break;
  3769. case OPC_OUB_KEK_MANAGEMENT_RESP:
  3770. pm8001_dbg(pm8001_ha, MSG,
  3771. "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
  3772. mpi_kek_management_resp(pm8001_ha, piomb);
  3773. break;
  3774. case OPC_OUB_DEK_MANAGEMENT_RESP:
  3775. pm8001_dbg(pm8001_ha, MSG,
  3776. "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
  3777. mpi_dek_management_resp(pm8001_ha, piomb);
  3778. break;
  3779. case OPC_OUB_SSP_COALESCED_COMP_RESP:
  3780. pm8001_dbg(pm8001_ha, MSG,
  3781. "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
  3782. ssp_coalesced_comp_resp(pm8001_ha, piomb);
  3783. break;
  3784. default:
  3785. pm8001_dbg(pm8001_ha, DEVIO,
  3786. "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
  3787. break;
  3788. }
  3789. }
  3790. static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
  3791. {
  3792. pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
  3793. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
  3794. pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
  3795. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
  3796. pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
  3797. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
  3798. pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
  3799. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
  3800. pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
  3801. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
  3802. pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
  3803. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
  3804. pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
  3805. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
  3806. pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
  3807. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
  3808. pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
  3809. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
  3810. pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
  3811. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
  3812. pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
  3813. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6));
  3814. pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
  3815. pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7));
  3816. }
  3817. static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
  3818. {
  3819. struct outbound_queue_table *circularQ;
  3820. void *pMsg1 = NULL;
  3821. u8 bc;
  3822. u32 ret = MPI_IO_STATUS_FAIL;
  3823. unsigned long flags;
  3824. u32 regval;
  3825. /*
  3826. * Fatal errors are programmed to be signalled in irq vector
  3827. * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
  3828. * fatal_err_interrupt
  3829. */
  3830. if (vec == (pm8001_ha->max_q_num - 1)) {
  3831. u32 mipsall_ready;
  3832. if (pm8001_ha->chip_id == chip_8008 ||
  3833. pm8001_ha->chip_id == chip_8009)
  3834. mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
  3835. else
  3836. mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
  3837. regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  3838. if ((regval & mipsall_ready) != mipsall_ready) {
  3839. pm8001_ha->controller_fatal_error = true;
  3840. pm8001_dbg(pm8001_ha, FAIL,
  3841. "Firmware Fatal error! Regval:0x%x\n",
  3842. regval);
  3843. print_scratchpad_registers(pm8001_ha);
  3844. return ret;
  3845. }
  3846. }
  3847. spin_lock_irqsave(&pm8001_ha->lock, flags);
  3848. circularQ = &pm8001_ha->outbnd_q_tbl[vec];
  3849. do {
  3850. /* spurious interrupt during setup if kexec-ing and
  3851. * driver doing a doorbell access w/ the pre-kexec oq
  3852. * interrupt setup.
  3853. */
  3854. if (!circularQ->pi_virt)
  3855. break;
  3856. ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
  3857. if (MPI_IO_STATUS_SUCCESS == ret) {
  3858. /* process the outbound message */
  3859. process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
  3860. /* free the message from the outbound circular buffer */
  3861. pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
  3862. circularQ, bc);
  3863. }
  3864. if (MPI_IO_STATUS_BUSY == ret) {
  3865. /* Update the producer index from SPC */
  3866. circularQ->producer_index =
  3867. cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
  3868. if (le32_to_cpu(circularQ->producer_index) ==
  3869. circularQ->consumer_idx)
  3870. /* OQ is empty */
  3871. break;
  3872. }
  3873. } while (1);
  3874. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  3875. return ret;
  3876. }
  3877. /* DMA_... to our direction translation. */
  3878. static const u8 data_dir_flags[] = {
  3879. [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
  3880. [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
  3881. [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
  3882. [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
  3883. };
  3884. static void build_smp_cmd(u32 deviceID, __le32 hTag,
  3885. struct smp_req *psmp_cmd, int mode, int length)
  3886. {
  3887. psmp_cmd->tag = hTag;
  3888. psmp_cmd->device_id = cpu_to_le32(deviceID);
  3889. if (mode == SMP_DIRECT) {
  3890. length = length - 4; /* subtract crc */
  3891. psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
  3892. } else {
  3893. psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
  3894. }
  3895. }
  3896. /**
  3897. * pm8001_chip_smp_req - send a SMP task to FW
  3898. * @pm8001_ha: our hba card information.
  3899. * @ccb: the ccb information this request used.
  3900. */
  3901. static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
  3902. struct pm8001_ccb_info *ccb)
  3903. {
  3904. int elem, rc;
  3905. struct sas_task *task = ccb->task;
  3906. struct domain_device *dev = task->dev;
  3907. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  3908. struct scatterlist *sg_req, *sg_resp;
  3909. u32 req_len, resp_len;
  3910. struct smp_req smp_cmd;
  3911. u32 opc;
  3912. struct inbound_queue_table *circularQ;
  3913. char *preq_dma_addr = NULL;
  3914. __le64 tmp_addr;
  3915. u32 i, length;
  3916. memset(&smp_cmd, 0, sizeof(smp_cmd));
  3917. /*
  3918. * DMA-map SMP request, response buffers
  3919. */
  3920. sg_req = &task->smp_task.smp_req;
  3921. elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
  3922. if (!elem)
  3923. return -ENOMEM;
  3924. req_len = sg_dma_len(sg_req);
  3925. sg_resp = &task->smp_task.smp_resp;
  3926. elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
  3927. if (!elem) {
  3928. rc = -ENOMEM;
  3929. goto err_out;
  3930. }
  3931. resp_len = sg_dma_len(sg_resp);
  3932. /* must be in dwords */
  3933. if ((req_len & 0x3) || (resp_len & 0x3)) {
  3934. rc = -EINVAL;
  3935. goto err_out_2;
  3936. }
  3937. opc = OPC_INB_SMP_REQUEST;
  3938. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3939. smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
  3940. length = sg_req->length;
  3941. pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
  3942. if (!(length - 8))
  3943. pm8001_ha->smp_exp_mode = SMP_DIRECT;
  3944. else
  3945. pm8001_ha->smp_exp_mode = SMP_INDIRECT;
  3946. tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
  3947. preq_dma_addr = (char *)phys_to_virt(tmp_addr);
  3948. /* INDIRECT MODE command settings. Use DMA */
  3949. if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
  3950. pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
  3951. /* for SPCv indirect mode. Place the top 4 bytes of
  3952. * SMP Request header here. */
  3953. for (i = 0; i < 4; i++)
  3954. smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
  3955. /* exclude top 4 bytes for SMP req header */
  3956. smp_cmd.long_smp_req.long_req_addr =
  3957. cpu_to_le64((u64)sg_dma_address
  3958. (&task->smp_task.smp_req) + 4);
  3959. /* exclude 4 bytes for SMP req header and CRC */
  3960. smp_cmd.long_smp_req.long_req_size =
  3961. cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
  3962. smp_cmd.long_smp_req.long_resp_addr =
  3963. cpu_to_le64((u64)sg_dma_address
  3964. (&task->smp_task.smp_resp));
  3965. smp_cmd.long_smp_req.long_resp_size =
  3966. cpu_to_le32((u32)sg_dma_len
  3967. (&task->smp_task.smp_resp)-4);
  3968. } else { /* DIRECT MODE */
  3969. smp_cmd.long_smp_req.long_req_addr =
  3970. cpu_to_le64((u64)sg_dma_address
  3971. (&task->smp_task.smp_req));
  3972. smp_cmd.long_smp_req.long_req_size =
  3973. cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
  3974. smp_cmd.long_smp_req.long_resp_addr =
  3975. cpu_to_le64((u64)sg_dma_address
  3976. (&task->smp_task.smp_resp));
  3977. smp_cmd.long_smp_req.long_resp_size =
  3978. cpu_to_le32
  3979. ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
  3980. }
  3981. if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
  3982. pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
  3983. for (i = 0; i < length; i++)
  3984. if (i < 16) {
  3985. smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
  3986. pm8001_dbg(pm8001_ha, IO,
  3987. "Byte[%d]:%x (DMA data:%x)\n",
  3988. i, smp_cmd.smp_req16[i],
  3989. *(preq_dma_addr));
  3990. } else {
  3991. smp_cmd.smp_req[i] = *(preq_dma_addr+i);
  3992. pm8001_dbg(pm8001_ha, IO,
  3993. "Byte[%d]:%x (DMA data:%x)\n",
  3994. i, smp_cmd.smp_req[i],
  3995. *(preq_dma_addr));
  3996. }
  3997. }
  3998. build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
  3999. &smp_cmd, pm8001_ha->smp_exp_mode, length);
  4000. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
  4001. sizeof(smp_cmd), 0);
  4002. if (rc)
  4003. goto err_out_2;
  4004. return 0;
  4005. err_out_2:
  4006. dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
  4007. DMA_FROM_DEVICE);
  4008. err_out:
  4009. dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
  4010. DMA_TO_DEVICE);
  4011. return rc;
  4012. }
  4013. static int check_enc_sas_cmd(struct sas_task *task)
  4014. {
  4015. u8 cmd = task->ssp_task.cmd->cmnd[0];
  4016. if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
  4017. return 1;
  4018. else
  4019. return 0;
  4020. }
  4021. static int check_enc_sat_cmd(struct sas_task *task)
  4022. {
  4023. int ret = 0;
  4024. switch (task->ata_task.fis.command) {
  4025. case ATA_CMD_FPDMA_READ:
  4026. case ATA_CMD_READ_EXT:
  4027. case ATA_CMD_READ:
  4028. case ATA_CMD_FPDMA_WRITE:
  4029. case ATA_CMD_WRITE_EXT:
  4030. case ATA_CMD_WRITE:
  4031. case ATA_CMD_PIO_READ:
  4032. case ATA_CMD_PIO_READ_EXT:
  4033. case ATA_CMD_PIO_WRITE:
  4034. case ATA_CMD_PIO_WRITE_EXT:
  4035. ret = 1;
  4036. break;
  4037. default:
  4038. ret = 0;
  4039. break;
  4040. }
  4041. return ret;
  4042. }
  4043. /**
  4044. * pm80xx_chip_ssp_io_req - send a SSP task to FW
  4045. * @pm8001_ha: our hba card information.
  4046. * @ccb: the ccb information this request used.
  4047. */
  4048. static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
  4049. struct pm8001_ccb_info *ccb)
  4050. {
  4051. struct sas_task *task = ccb->task;
  4052. struct domain_device *dev = task->dev;
  4053. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  4054. struct ssp_ini_io_start_req ssp_cmd;
  4055. u32 tag = ccb->ccb_tag;
  4056. int ret;
  4057. u64 phys_addr, end_addr;
  4058. u32 end_addr_high, end_addr_low;
  4059. struct inbound_queue_table *circularQ;
  4060. u32 q_index, cpu_id;
  4061. u32 opc = OPC_INB_SSPINIIOSTART;
  4062. memset(&ssp_cmd, 0, sizeof(ssp_cmd));
  4063. memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
  4064. /* data address domain added for spcv; set to 0 by host,
  4065. * used internally by controller
  4066. * 0 for SAS 1.1 and SAS 2.0 compatible TLR
  4067. */
  4068. ssp_cmd.dad_dir_m_tlr =
  4069. cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
  4070. ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
  4071. ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
  4072. ssp_cmd.tag = cpu_to_le32(tag);
  4073. if (task->ssp_task.enable_first_burst)
  4074. ssp_cmd.ssp_iu.efb_prio_attr = 0x80;
  4075. ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
  4076. ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
  4077. memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
  4078. task->ssp_task.cmd->cmd_len);
  4079. cpu_id = smp_processor_id();
  4080. q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
  4081. circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
  4082. /* Check if encryption is set */
  4083. if (pm8001_ha->chip->encrypt &&
  4084. !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
  4085. pm8001_dbg(pm8001_ha, IO,
  4086. "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
  4087. task->ssp_task.cmd->cmnd[0]);
  4088. opc = OPC_INB_SSP_INI_DIF_ENC_IO;
  4089. /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
  4090. ssp_cmd.dad_dir_m_tlr = cpu_to_le32
  4091. ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
  4092. /* fill in PRD (scatter/gather) table, if any */
  4093. if (task->num_scatter > 1) {
  4094. pm8001_chip_make_sg(task->scatter,
  4095. ccb->n_elem, ccb->buf_prd);
  4096. phys_addr = ccb->ccb_dma_handle;
  4097. ssp_cmd.enc_addr_low =
  4098. cpu_to_le32(lower_32_bits(phys_addr));
  4099. ssp_cmd.enc_addr_high =
  4100. cpu_to_le32(upper_32_bits(phys_addr));
  4101. ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
  4102. } else if (task->num_scatter == 1) {
  4103. u64 dma_addr = sg_dma_address(task->scatter);
  4104. ssp_cmd.enc_addr_low =
  4105. cpu_to_le32(lower_32_bits(dma_addr));
  4106. ssp_cmd.enc_addr_high =
  4107. cpu_to_le32(upper_32_bits(dma_addr));
  4108. ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
  4109. ssp_cmd.enc_esgl = 0;
  4110. /* Check 4G Boundary */
  4111. end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
  4112. end_addr_low = lower_32_bits(end_addr);
  4113. end_addr_high = upper_32_bits(end_addr);
  4114. if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
  4115. pm8001_dbg(pm8001_ha, FAIL,
  4116. "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
  4117. dma_addr,
  4118. le32_to_cpu(ssp_cmd.enc_len),
  4119. end_addr_high, end_addr_low);
  4120. pm8001_chip_make_sg(task->scatter, 1,
  4121. ccb->buf_prd);
  4122. phys_addr = ccb->ccb_dma_handle;
  4123. ssp_cmd.enc_addr_low =
  4124. cpu_to_le32(lower_32_bits(phys_addr));
  4125. ssp_cmd.enc_addr_high =
  4126. cpu_to_le32(upper_32_bits(phys_addr));
  4127. ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
  4128. }
  4129. } else if (task->num_scatter == 0) {
  4130. ssp_cmd.enc_addr_low = 0;
  4131. ssp_cmd.enc_addr_high = 0;
  4132. ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
  4133. ssp_cmd.enc_esgl = 0;
  4134. }
  4135. /* XTS mode. All other fields are 0 */
  4136. ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
  4137. /* set tweak values. Should be the start lba */
  4138. ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
  4139. (task->ssp_task.cmd->cmnd[3] << 16) |
  4140. (task->ssp_task.cmd->cmnd[4] << 8) |
  4141. (task->ssp_task.cmd->cmnd[5]));
  4142. } else {
  4143. pm8001_dbg(pm8001_ha, IO,
  4144. "Sending Normal SAS command 0x%x inb q %x\n",
  4145. task->ssp_task.cmd->cmnd[0], q_index);
  4146. /* fill in PRD (scatter/gather) table, if any */
  4147. if (task->num_scatter > 1) {
  4148. pm8001_chip_make_sg(task->scatter, ccb->n_elem,
  4149. ccb->buf_prd);
  4150. phys_addr = ccb->ccb_dma_handle;
  4151. ssp_cmd.addr_low =
  4152. cpu_to_le32(lower_32_bits(phys_addr));
  4153. ssp_cmd.addr_high =
  4154. cpu_to_le32(upper_32_bits(phys_addr));
  4155. ssp_cmd.esgl = cpu_to_le32(1<<31);
  4156. } else if (task->num_scatter == 1) {
  4157. u64 dma_addr = sg_dma_address(task->scatter);
  4158. ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
  4159. ssp_cmd.addr_high =
  4160. cpu_to_le32(upper_32_bits(dma_addr));
  4161. ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
  4162. ssp_cmd.esgl = 0;
  4163. /* Check 4G Boundary */
  4164. end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
  4165. end_addr_low = lower_32_bits(end_addr);
  4166. end_addr_high = upper_32_bits(end_addr);
  4167. if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
  4168. pm8001_dbg(pm8001_ha, FAIL,
  4169. "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
  4170. dma_addr,
  4171. le32_to_cpu(ssp_cmd.len),
  4172. end_addr_high, end_addr_low);
  4173. pm8001_chip_make_sg(task->scatter, 1,
  4174. ccb->buf_prd);
  4175. phys_addr = ccb->ccb_dma_handle;
  4176. ssp_cmd.addr_low =
  4177. cpu_to_le32(lower_32_bits(phys_addr));
  4178. ssp_cmd.addr_high =
  4179. cpu_to_le32(upper_32_bits(phys_addr));
  4180. ssp_cmd.esgl = cpu_to_le32(1<<31);
  4181. }
  4182. } else if (task->num_scatter == 0) {
  4183. ssp_cmd.addr_low = 0;
  4184. ssp_cmd.addr_high = 0;
  4185. ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
  4186. ssp_cmd.esgl = 0;
  4187. }
  4188. }
  4189. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
  4190. &ssp_cmd, sizeof(ssp_cmd), q_index);
  4191. return ret;
  4192. }
  4193. static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
  4194. struct pm8001_ccb_info *ccb)
  4195. {
  4196. struct sas_task *task = ccb->task;
  4197. struct domain_device *dev = task->dev;
  4198. struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
  4199. u32 tag = ccb->ccb_tag;
  4200. int ret;
  4201. u32 q_index, cpu_id;
  4202. struct sata_start_req sata_cmd;
  4203. u32 hdr_tag, ncg_tag = 0;
  4204. u64 phys_addr, end_addr;
  4205. u32 end_addr_high, end_addr_low;
  4206. u32 ATAP = 0x0;
  4207. u32 dir;
  4208. struct inbound_queue_table *circularQ;
  4209. unsigned long flags;
  4210. u32 opc = OPC_INB_SATA_HOST_OPSTART;
  4211. memset(&sata_cmd, 0, sizeof(sata_cmd));
  4212. cpu_id = smp_processor_id();
  4213. q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
  4214. circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
  4215. if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
  4216. ATAP = 0x04; /* no data*/
  4217. pm8001_dbg(pm8001_ha, IO, "no data\n");
  4218. } else if (likely(!task->ata_task.device_control_reg_update)) {
  4219. if (task->ata_task.use_ncq &&
  4220. dev->sata_dev.class != ATA_DEV_ATAPI) {
  4221. ATAP = 0x07; /* FPDMA */
  4222. pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
  4223. } else if (task->ata_task.dma_xfer) {
  4224. ATAP = 0x06; /* DMA */
  4225. pm8001_dbg(pm8001_ha, IO, "DMA\n");
  4226. } else {
  4227. ATAP = 0x05; /* PIO*/
  4228. pm8001_dbg(pm8001_ha, IO, "PIO\n");
  4229. }
  4230. }
  4231. if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
  4232. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  4233. ncg_tag = hdr_tag;
  4234. }
  4235. dir = data_dir_flags[task->data_dir] << 8;
  4236. sata_cmd.tag = cpu_to_le32(tag);
  4237. sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  4238. sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
  4239. sata_cmd.sata_fis = task->ata_task.fis;
  4240. if (likely(!task->ata_task.device_control_reg_update))
  4241. sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
  4242. sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
  4243. /* Check if encryption is set */
  4244. if (pm8001_ha->chip->encrypt &&
  4245. !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
  4246. pm8001_dbg(pm8001_ha, IO,
  4247. "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
  4248. sata_cmd.sata_fis.command);
  4249. opc = OPC_INB_SATA_DIF_ENC_IO;
  4250. /* set encryption bit */
  4251. sata_cmd.ncqtag_atap_dir_m_dad =
  4252. cpu_to_le32(((ncg_tag & 0xff)<<16)|
  4253. ((ATAP & 0x3f) << 10) | 0x20 | dir);
  4254. /* dad (bit 0-1) is 0 */
  4255. /* fill in PRD (scatter/gather) table, if any */
  4256. if (task->num_scatter > 1) {
  4257. pm8001_chip_make_sg(task->scatter,
  4258. ccb->n_elem, ccb->buf_prd);
  4259. phys_addr = ccb->ccb_dma_handle;
  4260. sata_cmd.enc_addr_low =
  4261. cpu_to_le32(lower_32_bits(phys_addr));
  4262. sata_cmd.enc_addr_high =
  4263. cpu_to_le32(upper_32_bits(phys_addr));
  4264. sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
  4265. } else if (task->num_scatter == 1) {
  4266. u64 dma_addr = sg_dma_address(task->scatter);
  4267. sata_cmd.enc_addr_low =
  4268. cpu_to_le32(lower_32_bits(dma_addr));
  4269. sata_cmd.enc_addr_high =
  4270. cpu_to_le32(upper_32_bits(dma_addr));
  4271. sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
  4272. sata_cmd.enc_esgl = 0;
  4273. /* Check 4G Boundary */
  4274. end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
  4275. end_addr_low = lower_32_bits(end_addr);
  4276. end_addr_high = upper_32_bits(end_addr);
  4277. if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
  4278. pm8001_dbg(pm8001_ha, FAIL,
  4279. "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
  4280. dma_addr,
  4281. le32_to_cpu(sata_cmd.enc_len),
  4282. end_addr_high, end_addr_low);
  4283. pm8001_chip_make_sg(task->scatter, 1,
  4284. ccb->buf_prd);
  4285. phys_addr = ccb->ccb_dma_handle;
  4286. sata_cmd.enc_addr_low =
  4287. cpu_to_le32(lower_32_bits(phys_addr));
  4288. sata_cmd.enc_addr_high =
  4289. cpu_to_le32(upper_32_bits(phys_addr));
  4290. sata_cmd.enc_esgl =
  4291. cpu_to_le32(1 << 31);
  4292. }
  4293. } else if (task->num_scatter == 0) {
  4294. sata_cmd.enc_addr_low = 0;
  4295. sata_cmd.enc_addr_high = 0;
  4296. sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
  4297. sata_cmd.enc_esgl = 0;
  4298. }
  4299. /* XTS mode. All other fields are 0 */
  4300. sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
  4301. /* set tweak values. Should be the start lba */
  4302. sata_cmd.twk_val0 =
  4303. cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
  4304. (sata_cmd.sata_fis.lbah << 16) |
  4305. (sata_cmd.sata_fis.lbam << 8) |
  4306. (sata_cmd.sata_fis.lbal));
  4307. sata_cmd.twk_val1 =
  4308. cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
  4309. (sata_cmd.sata_fis.lbam_exp));
  4310. } else {
  4311. pm8001_dbg(pm8001_ha, IO,
  4312. "Sending Normal SATA command 0x%x inb %x\n",
  4313. sata_cmd.sata_fis.command, q_index);
  4314. /* dad (bit 0-1) is 0 */
  4315. sata_cmd.ncqtag_atap_dir_m_dad =
  4316. cpu_to_le32(((ncg_tag & 0xff)<<16) |
  4317. ((ATAP & 0x3f) << 10) | dir);
  4318. /* fill in PRD (scatter/gather) table, if any */
  4319. if (task->num_scatter > 1) {
  4320. pm8001_chip_make_sg(task->scatter,
  4321. ccb->n_elem, ccb->buf_prd);
  4322. phys_addr = ccb->ccb_dma_handle;
  4323. sata_cmd.addr_low = lower_32_bits(phys_addr);
  4324. sata_cmd.addr_high = upper_32_bits(phys_addr);
  4325. sata_cmd.esgl = cpu_to_le32(1U << 31);
  4326. } else if (task->num_scatter == 1) {
  4327. u64 dma_addr = sg_dma_address(task->scatter);
  4328. sata_cmd.addr_low = lower_32_bits(dma_addr);
  4329. sata_cmd.addr_high = upper_32_bits(dma_addr);
  4330. sata_cmd.len = cpu_to_le32(task->total_xfer_len);
  4331. sata_cmd.esgl = 0;
  4332. /* Check 4G Boundary */
  4333. end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
  4334. end_addr_low = lower_32_bits(end_addr);
  4335. end_addr_high = upper_32_bits(end_addr);
  4336. if (end_addr_high != sata_cmd.addr_high) {
  4337. pm8001_dbg(pm8001_ha, FAIL,
  4338. "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
  4339. dma_addr,
  4340. le32_to_cpu(sata_cmd.len),
  4341. end_addr_high, end_addr_low);
  4342. pm8001_chip_make_sg(task->scatter, 1,
  4343. ccb->buf_prd);
  4344. phys_addr = ccb->ccb_dma_handle;
  4345. sata_cmd.addr_low = lower_32_bits(phys_addr);
  4346. sata_cmd.addr_high = upper_32_bits(phys_addr);
  4347. sata_cmd.esgl = cpu_to_le32(1U << 31);
  4348. }
  4349. } else if (task->num_scatter == 0) {
  4350. sata_cmd.addr_low = 0;
  4351. sata_cmd.addr_high = 0;
  4352. sata_cmd.len = cpu_to_le32(task->total_xfer_len);
  4353. sata_cmd.esgl = 0;
  4354. }
  4355. /* scsi cdb */
  4356. sata_cmd.atapi_scsi_cdb[0] =
  4357. cpu_to_le32(((task->ata_task.atapi_packet[0]) |
  4358. (task->ata_task.atapi_packet[1] << 8) |
  4359. (task->ata_task.atapi_packet[2] << 16) |
  4360. (task->ata_task.atapi_packet[3] << 24)));
  4361. sata_cmd.atapi_scsi_cdb[1] =
  4362. cpu_to_le32(((task->ata_task.atapi_packet[4]) |
  4363. (task->ata_task.atapi_packet[5] << 8) |
  4364. (task->ata_task.atapi_packet[6] << 16) |
  4365. (task->ata_task.atapi_packet[7] << 24)));
  4366. sata_cmd.atapi_scsi_cdb[2] =
  4367. cpu_to_le32(((task->ata_task.atapi_packet[8]) |
  4368. (task->ata_task.atapi_packet[9] << 8) |
  4369. (task->ata_task.atapi_packet[10] << 16) |
  4370. (task->ata_task.atapi_packet[11] << 24)));
  4371. sata_cmd.atapi_scsi_cdb[3] =
  4372. cpu_to_le32(((task->ata_task.atapi_packet[12]) |
  4373. (task->ata_task.atapi_packet[13] << 8) |
  4374. (task->ata_task.atapi_packet[14] << 16) |
  4375. (task->ata_task.atapi_packet[15] << 24)));
  4376. }
  4377. /* Check for read log for failed drive and return */
  4378. if (sata_cmd.sata_fis.command == 0x2f) {
  4379. if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
  4380. (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
  4381. (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
  4382. struct task_status_struct *ts;
  4383. pm8001_ha_dev->id &= 0xDFFFFFFF;
  4384. ts = &task->task_status;
  4385. spin_lock_irqsave(&task->task_state_lock, flags);
  4386. ts->resp = SAS_TASK_COMPLETE;
  4387. ts->stat = SAM_STAT_GOOD;
  4388. task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  4389. task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  4390. task->task_state_flags |= SAS_TASK_STATE_DONE;
  4391. if (unlikely((task->task_state_flags &
  4392. SAS_TASK_STATE_ABORTED))) {
  4393. spin_unlock_irqrestore(&task->task_state_lock,
  4394. flags);
  4395. pm8001_dbg(pm8001_ha, FAIL,
  4396. "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
  4397. task, ts->resp,
  4398. ts->stat);
  4399. pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
  4400. return 0;
  4401. } else {
  4402. spin_unlock_irqrestore(&task->task_state_lock,
  4403. flags);
  4404. pm8001_ccb_task_free_done(pm8001_ha, task,
  4405. ccb, tag);
  4406. atomic_dec(&pm8001_ha_dev->running_req);
  4407. return 0;
  4408. }
  4409. }
  4410. }
  4411. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
  4412. &sata_cmd, sizeof(sata_cmd), q_index);
  4413. return ret;
  4414. }
  4415. /**
  4416. * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
  4417. * @pm8001_ha: our hba card information.
  4418. * @phy_id: the phy id which we wanted to start up.
  4419. */
  4420. static int
  4421. pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
  4422. {
  4423. struct phy_start_req payload;
  4424. struct inbound_queue_table *circularQ;
  4425. int ret;
  4426. u32 tag = 0x01;
  4427. u32 opcode = OPC_INB_PHYSTART;
  4428. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4429. memset(&payload, 0, sizeof(payload));
  4430. payload.tag = cpu_to_le32(tag);
  4431. pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
  4432. payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
  4433. LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
  4434. /* SSC Disable and SAS Analog ST configuration */
  4435. /**
  4436. payload.ase_sh_lm_slr_phyid =
  4437. cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
  4438. LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
  4439. phy_id);
  4440. Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
  4441. **/
  4442. payload.sas_identify.dev_type = SAS_END_DEVICE;
  4443. payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
  4444. memcpy(payload.sas_identify.sas_addr,
  4445. &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
  4446. payload.sas_identify.phy_id = phy_id;
  4447. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
  4448. sizeof(payload), 0);
  4449. return ret;
  4450. }
  4451. /**
  4452. * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
  4453. * @pm8001_ha: our hba card information.
  4454. * @phy_id: the phy id which we wanted to start up.
  4455. */
  4456. static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
  4457. u8 phy_id)
  4458. {
  4459. struct phy_stop_req payload;
  4460. struct inbound_queue_table *circularQ;
  4461. int ret;
  4462. u32 tag = 0x01;
  4463. u32 opcode = OPC_INB_PHYSTOP;
  4464. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4465. memset(&payload, 0, sizeof(payload));
  4466. payload.tag = cpu_to_le32(tag);
  4467. payload.phy_id = cpu_to_le32(phy_id);
  4468. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
  4469. sizeof(payload), 0);
  4470. return ret;
  4471. }
  4472. /*
  4473. * see comments on pm8001_mpi_reg_resp.
  4474. */
  4475. static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
  4476. struct pm8001_device *pm8001_dev, u32 flag)
  4477. {
  4478. struct reg_dev_req payload;
  4479. u32 opc;
  4480. u32 stp_sspsmp_sata = 0x4;
  4481. struct inbound_queue_table *circularQ;
  4482. u32 linkrate, phy_id;
  4483. int rc, tag = 0xdeadbeef;
  4484. struct pm8001_ccb_info *ccb;
  4485. u8 retryFlag = 0x1;
  4486. u16 firstBurstSize = 0;
  4487. u16 ITNT = 2000;
  4488. struct domain_device *dev = pm8001_dev->sas_device;
  4489. struct domain_device *parent_dev = dev->parent;
  4490. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4491. memset(&payload, 0, sizeof(payload));
  4492. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4493. if (rc)
  4494. return rc;
  4495. ccb = &pm8001_ha->ccb_info[tag];
  4496. ccb->device = pm8001_dev;
  4497. ccb->ccb_tag = tag;
  4498. payload.tag = cpu_to_le32(tag);
  4499. if (flag == 1) {
  4500. stp_sspsmp_sata = 0x02; /*direct attached sata */
  4501. } else {
  4502. if (pm8001_dev->dev_type == SAS_SATA_DEV)
  4503. stp_sspsmp_sata = 0x00; /* stp*/
  4504. else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
  4505. pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
  4506. pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
  4507. stp_sspsmp_sata = 0x01; /*ssp or smp*/
  4508. }
  4509. if (parent_dev && dev_is_expander(parent_dev->dev_type))
  4510. phy_id = parent_dev->ex_dev.ex_phy->phy_id;
  4511. else
  4512. phy_id = pm8001_dev->attached_phy;
  4513. opc = OPC_INB_REG_DEV;
  4514. linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
  4515. pm8001_dev->sas_device->linkrate : dev->port->linkrate;
  4516. payload.phyid_portid =
  4517. cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
  4518. ((phy_id & 0xFF) << 8));
  4519. payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
  4520. ((linkrate & 0x0F) << 24) |
  4521. ((stp_sspsmp_sata & 0x03) << 28));
  4522. payload.firstburstsize_ITNexustimeout =
  4523. cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
  4524. memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
  4525. SAS_ADDR_SIZE);
  4526. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  4527. sizeof(payload), 0);
  4528. if (rc)
  4529. pm8001_tag_free(pm8001_ha, tag);
  4530. return rc;
  4531. }
  4532. /**
  4533. * pm80xx_chip_phy_ctl_req - support the local phy operation
  4534. * @pm8001_ha: our hba card information.
  4535. * @phyId: the phy id which we wanted to operate
  4536. * @phy_op: phy operation to request
  4537. */
  4538. static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
  4539. u32 phyId, u32 phy_op)
  4540. {
  4541. u32 tag;
  4542. int rc;
  4543. struct local_phy_ctl_req payload;
  4544. struct inbound_queue_table *circularQ;
  4545. u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
  4546. memset(&payload, 0, sizeof(payload));
  4547. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4548. if (rc)
  4549. return rc;
  4550. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4551. payload.tag = cpu_to_le32(tag);
  4552. payload.phyop_phyid =
  4553. cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
  4554. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  4555. sizeof(payload), 0);
  4556. if (rc)
  4557. pm8001_tag_free(pm8001_ha, tag);
  4558. return rc;
  4559. }
  4560. static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
  4561. {
  4562. #ifdef PM8001_USE_MSIX
  4563. return 1;
  4564. #else
  4565. u32 value;
  4566. value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
  4567. if (value)
  4568. return 1;
  4569. return 0;
  4570. #endif
  4571. }
  4572. /**
  4573. * pm8001_chip_isr - PM8001 isr handler.
  4574. * @pm8001_ha: our hba card information.
  4575. * @vec: irq number.
  4576. */
  4577. static irqreturn_t
  4578. pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
  4579. {
  4580. pm80xx_chip_interrupt_disable(pm8001_ha, vec);
  4581. pm8001_dbg(pm8001_ha, DEVIO,
  4582. "irq vec %d, ODMR:0x%x\n",
  4583. vec, pm8001_cr32(pm8001_ha, 0, 0x30));
  4584. process_oq(pm8001_ha, vec);
  4585. pm80xx_chip_interrupt_enable(pm8001_ha, vec);
  4586. return IRQ_HANDLED;
  4587. }
  4588. static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
  4589. u32 operation, u32 phyid,
  4590. u32 length, u32 *buf)
  4591. {
  4592. u32 tag , i, j = 0;
  4593. int rc;
  4594. struct set_phy_profile_req payload;
  4595. struct inbound_queue_table *circularQ;
  4596. u32 opc = OPC_INB_SET_PHY_PROFILE;
  4597. memset(&payload, 0, sizeof(payload));
  4598. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4599. if (rc)
  4600. pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
  4601. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4602. payload.tag = cpu_to_le32(tag);
  4603. payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
  4604. pm8001_dbg(pm8001_ha, INIT,
  4605. " phy profile command for phy %x ,length is %d\n",
  4606. payload.ppc_phyid, length);
  4607. for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
  4608. payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
  4609. j++;
  4610. }
  4611. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  4612. sizeof(payload), 0);
  4613. if (rc)
  4614. pm8001_tag_free(pm8001_ha, tag);
  4615. }
  4616. void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
  4617. u32 length, u8 *buf)
  4618. {
  4619. u32 i;
  4620. for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
  4621. mpi_set_phy_profile_req(pm8001_ha,
  4622. SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
  4623. length = length + PHY_DWORD_LENGTH;
  4624. }
  4625. pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
  4626. }
  4627. void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
  4628. u32 phy, u32 length, u32 *buf)
  4629. {
  4630. u32 tag, opc;
  4631. int rc, i;
  4632. struct set_phy_profile_req payload;
  4633. struct inbound_queue_table *circularQ;
  4634. memset(&payload, 0, sizeof(payload));
  4635. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4636. if (rc)
  4637. pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
  4638. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4639. opc = OPC_INB_SET_PHY_PROFILE;
  4640. payload.tag = cpu_to_le32(tag);
  4641. payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
  4642. | (phy & 0xFF));
  4643. for (i = 0; i < length; i++)
  4644. payload.reserved[i] = cpu_to_le32(*(buf + i));
  4645. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
  4646. sizeof(payload), 0);
  4647. if (rc)
  4648. pm8001_tag_free(pm8001_ha, tag);
  4649. pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
  4650. }
  4651. const struct pm8001_dispatch pm8001_80xx_dispatch = {
  4652. .name = "pmc80xx",
  4653. .chip_init = pm80xx_chip_init,
  4654. .chip_soft_rst = pm80xx_chip_soft_rst,
  4655. .chip_rst = pm80xx_hw_chip_rst,
  4656. .chip_iounmap = pm8001_chip_iounmap,
  4657. .isr = pm80xx_chip_isr,
  4658. .is_our_interrupt = pm80xx_chip_is_our_interrupt,
  4659. .isr_process_oq = process_oq,
  4660. .interrupt_enable = pm80xx_chip_interrupt_enable,
  4661. .interrupt_disable = pm80xx_chip_interrupt_disable,
  4662. .make_prd = pm8001_chip_make_sg,
  4663. .smp_req = pm80xx_chip_smp_req,
  4664. .ssp_io_req = pm80xx_chip_ssp_io_req,
  4665. .sata_req = pm80xx_chip_sata_req,
  4666. .phy_start_req = pm80xx_chip_phy_start_req,
  4667. .phy_stop_req = pm80xx_chip_phy_stop_req,
  4668. .reg_dev_req = pm80xx_chip_reg_dev_req,
  4669. .dereg_dev_req = pm8001_chip_dereg_dev_req,
  4670. .phy_ctl_req = pm80xx_chip_phy_ctl_req,
  4671. .task_abort = pm8001_chip_abort_task,
  4672. .ssp_tm_req = pm8001_chip_ssp_tm_req,
  4673. .get_nvmd_req = pm8001_chip_get_nvmd_req,
  4674. .set_nvmd_req = pm8001_chip_set_nvmd_req,
  4675. .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
  4676. .set_dev_state_req = pm8001_chip_set_dev_state_req,
  4677. };