pm8001_sas.h 24 KB

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  1. /*
  2. * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
  3. *
  4. * Copyright (c) 2008-2009 USI Co., Ltd.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. */
  40. #ifndef _PM8001_SAS_H_
  41. #define _PM8001_SAS_H_
  42. #include <linux/kernel.h>
  43. #include <linux/module.h>
  44. #include <linux/spinlock.h>
  45. #include <linux/delay.h>
  46. #include <linux/types.h>
  47. #include <linux/ctype.h>
  48. #include <linux/dma-mapping.h>
  49. #include <linux/pci.h>
  50. #include <linux/interrupt.h>
  51. #include <linux/workqueue.h>
  52. #include <scsi/libsas.h>
  53. #include <scsi/scsi_tcq.h>
  54. #include <scsi/sas_ata.h>
  55. #include <linux/atomic.h>
  56. #include "pm8001_defs.h"
  57. #define DRV_NAME "pm80xx"
  58. #define DRV_VERSION "0.1.40"
  59. #define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
  60. #define PM8001_INIT_LOGGING 0x02 /* driver init logging */
  61. #define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
  62. #define PM8001_IO_LOGGING 0x08 /* I/O path logging */
  63. #define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
  64. #define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
  65. #define PM8001_MSG_LOGGING 0x40 /* misc message logging */
  66. #define PM8001_DEV_LOGGING 0x80 /* development message logging */
  67. #define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */
  68. #define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */
  69. #define pm8001_printk(fmt, ...) \
  70. pr_info("%s:: %s %d:" fmt, \
  71. pm8001_ha->name, __func__, __LINE__, ##__VA_ARGS__)
  72. #define pm8001_dbg(HBA, level, fmt, ...) \
  73. do { \
  74. if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING)) \
  75. pm8001_printk(fmt, ##__VA_ARGS__); \
  76. } while (0)
  77. #define PM8001_USE_TASKLET
  78. #define PM8001_USE_MSIX
  79. #define PM8001_READ_VPD
  80. #define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
  81. || (dev->device == 0X8076) \
  82. || (dev->device == 0X8077) \
  83. || (dev->device == 0X8070) \
  84. || (dev->device == 0X8072))
  85. #define PM8001_NAME_LENGTH 32/* generic length of strings */
  86. extern struct list_head hba_list;
  87. extern const struct pm8001_dispatch pm8001_8001_dispatch;
  88. extern const struct pm8001_dispatch pm8001_80xx_dispatch;
  89. struct pm8001_hba_info;
  90. struct pm8001_ccb_info;
  91. struct pm8001_device;
  92. /* define task management IU */
  93. struct pm8001_tmf_task {
  94. u8 tmf;
  95. u32 tag_of_task_to_be_managed;
  96. };
  97. struct pm8001_ioctl_payload {
  98. u32 signature;
  99. u16 major_function;
  100. u16 minor_function;
  101. u16 status;
  102. u16 offset;
  103. u16 id;
  104. u32 wr_length;
  105. u32 rd_length;
  106. u8 *func_specific;
  107. };
  108. #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
  109. #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
  110. #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
  111. #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
  112. #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
  113. #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
  114. #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
  115. #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
  116. #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN 0x18 /* TOTALLEN */
  117. #define MPI_FATAL_EDUMP_TABLE_SIGNATURE 0x1C /* SIGNITURE */
  118. #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
  119. #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
  120. #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
  121. #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
  122. #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
  123. #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
  124. #define TYPE_GSM_SPACE 1
  125. #define TYPE_QUEUE 2
  126. #define TYPE_FATAL 3
  127. #define TYPE_NON_FATAL 4
  128. #define TYPE_INBOUND 1
  129. #define TYPE_OUTBOUND 2
  130. struct forensic_data {
  131. u32 data_type;
  132. union {
  133. struct {
  134. u32 direct_len;
  135. u32 direct_offset;
  136. void *direct_data;
  137. } gsm_buf;
  138. struct {
  139. u16 queue_type;
  140. u16 queue_index;
  141. u32 direct_len;
  142. void *direct_data;
  143. } queue_buf;
  144. struct {
  145. u32 direct_len;
  146. u32 direct_offset;
  147. u32 read_len;
  148. void *direct_data;
  149. } data_buf;
  150. };
  151. };
  152. /* bit31-26 - mask bar */
  153. #define SCRATCH_PAD0_BAR_MASK 0xFC000000
  154. /* bit25-0 - offset mask */
  155. #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
  156. /* if AAP error state */
  157. #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
  158. /* Inbound doorbell bit7 */
  159. #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
  160. /* Inbound doorbell bit7 SPCV */
  161. #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
  162. #define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
  163. struct pm8001_dispatch {
  164. char *name;
  165. int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
  166. int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
  167. void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
  168. int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
  169. void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
  170. irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
  171. u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
  172. int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
  173. void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
  174. void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
  175. void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
  176. int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
  177. struct pm8001_ccb_info *ccb);
  178. int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
  179. struct pm8001_ccb_info *ccb);
  180. int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
  181. struct pm8001_ccb_info *ccb);
  182. int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
  183. int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
  184. int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
  185. struct pm8001_device *pm8001_dev, u32 flag);
  186. int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
  187. int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
  188. u32 phy_id, u32 phy_op);
  189. int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
  190. struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
  191. u32 cmd_tag);
  192. int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
  193. struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
  194. int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
  195. int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
  196. int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
  197. void *payload);
  198. int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
  199. struct pm8001_device *pm8001_dev, u32 state);
  200. int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
  201. u32 state);
  202. int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
  203. u32 state);
  204. int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
  205. };
  206. struct pm8001_chip_info {
  207. u32 encrypt;
  208. u32 n_phy;
  209. const struct pm8001_dispatch *dispatch;
  210. };
  211. #define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
  212. struct pm8001_port {
  213. struct asd_sas_port sas_port;
  214. u8 port_attached;
  215. u16 wide_port_phymap;
  216. u8 port_state;
  217. struct list_head list;
  218. };
  219. struct pm8001_phy {
  220. struct pm8001_hba_info *pm8001_ha;
  221. struct pm8001_port *port;
  222. struct asd_sas_phy sas_phy;
  223. struct sas_identify identify;
  224. struct scsi_device *sdev;
  225. u64 dev_sas_addr;
  226. u32 phy_type;
  227. struct completion *enable_completion;
  228. u32 frame_rcvd_size;
  229. u8 frame_rcvd[32];
  230. u8 phy_attached;
  231. u8 phy_state;
  232. enum sas_linkrate minimum_linkrate;
  233. enum sas_linkrate maximum_linkrate;
  234. struct completion *reset_completion;
  235. bool port_reset_status;
  236. bool reset_success;
  237. };
  238. /* port reset status */
  239. #define PORT_RESET_SUCCESS 0x00
  240. #define PORT_RESET_TMO 0x01
  241. struct pm8001_device {
  242. enum sas_device_type dev_type;
  243. struct domain_device *sas_device;
  244. u32 attached_phy;
  245. u32 id;
  246. struct completion *dcompletion;
  247. struct completion *setds_completion;
  248. u32 device_id;
  249. atomic_t running_req;
  250. };
  251. struct pm8001_prd_imt {
  252. __le32 len;
  253. __le32 e;
  254. };
  255. struct pm8001_prd {
  256. __le64 addr; /* 64-bit buffer address */
  257. struct pm8001_prd_imt im_len; /* 64-bit length */
  258. } __attribute__ ((packed));
  259. /*
  260. * CCB(Command Control Block)
  261. */
  262. struct pm8001_ccb_info {
  263. struct list_head entry;
  264. struct sas_task *task;
  265. u32 n_elem;
  266. u32 ccb_tag;
  267. dma_addr_t ccb_dma_handle;
  268. struct pm8001_device *device;
  269. struct pm8001_prd *buf_prd;
  270. struct fw_control_ex *fw_control_context;
  271. u8 open_retry;
  272. };
  273. struct mpi_mem {
  274. void *virt_ptr;
  275. dma_addr_t phys_addr;
  276. u32 phys_addr_hi;
  277. u32 phys_addr_lo;
  278. u32 total_len;
  279. u32 num_elements;
  280. u32 element_size;
  281. u32 alignment;
  282. };
  283. struct mpi_mem_req {
  284. /* The number of element in the mpiMemory array */
  285. u32 count;
  286. /* The array of structures that define memroy regions*/
  287. struct mpi_mem region[USI_MAX_MEMCNT];
  288. };
  289. struct encrypt {
  290. u32 cipher_mode;
  291. u32 sec_mode;
  292. u32 status;
  293. u32 flag;
  294. };
  295. struct sas_phy_attribute_table {
  296. u32 phystart1_16[16];
  297. u32 outbound_hw_event_pid1_16[16];
  298. };
  299. union main_cfg_table {
  300. struct {
  301. u32 signature;
  302. u32 interface_rev;
  303. u32 firmware_rev;
  304. u32 max_out_io;
  305. u32 max_sgl;
  306. u32 ctrl_cap_flag;
  307. u32 gst_offset;
  308. u32 inbound_queue_offset;
  309. u32 outbound_queue_offset;
  310. u32 inbound_q_nppd_hppd;
  311. u32 outbound_hw_event_pid0_3;
  312. u32 outbound_hw_event_pid4_7;
  313. u32 outbound_ncq_event_pid0_3;
  314. u32 outbound_ncq_event_pid4_7;
  315. u32 outbound_tgt_ITNexus_event_pid0_3;
  316. u32 outbound_tgt_ITNexus_event_pid4_7;
  317. u32 outbound_tgt_ssp_event_pid0_3;
  318. u32 outbound_tgt_ssp_event_pid4_7;
  319. u32 outbound_tgt_smp_event_pid0_3;
  320. u32 outbound_tgt_smp_event_pid4_7;
  321. u32 upper_event_log_addr;
  322. u32 lower_event_log_addr;
  323. u32 event_log_size;
  324. u32 event_log_option;
  325. u32 upper_iop_event_log_addr;
  326. u32 lower_iop_event_log_addr;
  327. u32 iop_event_log_size;
  328. u32 iop_event_log_option;
  329. u32 fatal_err_interrupt;
  330. u32 fatal_err_dump_offset0;
  331. u32 fatal_err_dump_length0;
  332. u32 fatal_err_dump_offset1;
  333. u32 fatal_err_dump_length1;
  334. u32 hda_mode_flag;
  335. u32 anolog_setup_table_offset;
  336. u32 rsvd[4];
  337. } pm8001_tbl;
  338. struct {
  339. u32 signature;
  340. u32 interface_rev;
  341. u32 firmware_rev;
  342. u32 max_out_io;
  343. u32 max_sgl;
  344. u32 ctrl_cap_flag;
  345. u32 gst_offset;
  346. u32 inbound_queue_offset;
  347. u32 outbound_queue_offset;
  348. u32 inbound_q_nppd_hppd;
  349. u32 rsvd[8];
  350. u32 crc_core_dump;
  351. u32 rsvd1;
  352. u32 upper_event_log_addr;
  353. u32 lower_event_log_addr;
  354. u32 event_log_size;
  355. u32 event_log_severity;
  356. u32 upper_pcs_event_log_addr;
  357. u32 lower_pcs_event_log_addr;
  358. u32 pcs_event_log_size;
  359. u32 pcs_event_log_severity;
  360. u32 fatal_err_interrupt;
  361. u32 fatal_err_dump_offset0;
  362. u32 fatal_err_dump_length0;
  363. u32 fatal_err_dump_offset1;
  364. u32 fatal_err_dump_length1;
  365. u32 gpio_led_mapping;
  366. u32 analog_setup_table_offset;
  367. u32 int_vec_table_offset;
  368. u32 phy_attr_table_offset;
  369. u32 port_recovery_timer;
  370. u32 interrupt_reassertion_delay;
  371. u32 fatal_n_non_fatal_dump; /* 0x28 */
  372. u32 ila_version;
  373. u32 inc_fw_version;
  374. } pm80xx_tbl;
  375. };
  376. union general_status_table {
  377. struct {
  378. u32 gst_len_mpistate;
  379. u32 iq_freeze_state0;
  380. u32 iq_freeze_state1;
  381. u32 msgu_tcnt;
  382. u32 iop_tcnt;
  383. u32 rsvd;
  384. u32 phy_state[8];
  385. u32 gpio_input_val;
  386. u32 rsvd1[2];
  387. u32 recover_err_info[8];
  388. } pm8001_tbl;
  389. struct {
  390. u32 gst_len_mpistate;
  391. u32 iq_freeze_state0;
  392. u32 iq_freeze_state1;
  393. u32 msgu_tcnt;
  394. u32 iop_tcnt;
  395. u32 rsvd[9];
  396. u32 gpio_input_val;
  397. u32 rsvd1[2];
  398. u32 recover_err_info[8];
  399. } pm80xx_tbl;
  400. };
  401. struct inbound_queue_table {
  402. u32 element_pri_size_cnt;
  403. u32 upper_base_addr;
  404. u32 lower_base_addr;
  405. u32 ci_upper_base_addr;
  406. u32 ci_lower_base_addr;
  407. u32 pi_pci_bar;
  408. u32 pi_offset;
  409. u32 total_length;
  410. void *base_virt;
  411. void *ci_virt;
  412. u32 reserved;
  413. __le32 consumer_index;
  414. u32 producer_idx;
  415. spinlock_t iq_lock;
  416. };
  417. struct outbound_queue_table {
  418. u32 element_size_cnt;
  419. u32 upper_base_addr;
  420. u32 lower_base_addr;
  421. void *base_virt;
  422. u32 pi_upper_base_addr;
  423. u32 pi_lower_base_addr;
  424. u32 ci_pci_bar;
  425. u32 ci_offset;
  426. u32 total_length;
  427. void *pi_virt;
  428. u32 interrup_vec_cnt_delay;
  429. u32 dinterrup_to_pci_offset;
  430. __le32 producer_index;
  431. u32 consumer_idx;
  432. };
  433. struct pm8001_hba_memspace {
  434. void __iomem *memvirtaddr;
  435. u64 membase;
  436. u32 memsize;
  437. };
  438. struct isr_param {
  439. struct pm8001_hba_info *drv_inst;
  440. u32 irq_id;
  441. };
  442. struct pm8001_hba_info {
  443. char name[PM8001_NAME_LENGTH];
  444. struct list_head list;
  445. unsigned long flags;
  446. spinlock_t lock;/* host-wide lock */
  447. spinlock_t bitmap_lock;
  448. struct pci_dev *pdev;/* our device */
  449. struct device *dev;
  450. struct pm8001_hba_memspace io_mem[6];
  451. struct mpi_mem_req memoryMap;
  452. struct encrypt encrypt_info; /* support encryption */
  453. struct forensic_data forensic_info;
  454. u32 fatal_bar_loc;
  455. u32 forensic_last_offset;
  456. u32 fatal_forensic_shift_offset;
  457. u32 forensic_fatal_step;
  458. u32 forensic_preserved_accumulated_transfer;
  459. u32 evtlog_ib_offset;
  460. u32 evtlog_ob_offset;
  461. void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
  462. void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
  463. void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
  464. void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
  465. void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
  466. void __iomem *pspa_q_tbl_addr;
  467. /*MPI SAS PHY attributes Queue Config Table Addr*/
  468. void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
  469. void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
  470. union main_cfg_table main_cfg_tbl;
  471. union general_status_table gs_tbl;
  472. struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM];
  473. struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
  474. struct sas_phy_attribute_table phy_attr_table;
  475. /* MPI SAS PHY attributes */
  476. u8 sas_addr[SAS_ADDR_SIZE];
  477. struct sas_ha_struct *sas;/* SCSI/SAS glue */
  478. struct Scsi_Host *shost;
  479. u32 chip_id;
  480. const struct pm8001_chip_info *chip;
  481. struct completion *nvmd_completion;
  482. int tags_num;
  483. unsigned long *tags;
  484. struct pm8001_phy phy[PM8001_MAX_PHYS];
  485. struct pm8001_port port[PM8001_MAX_PHYS];
  486. u32 id;
  487. u32 irq;
  488. u32 iomb_size; /* SPC and SPCV IOMB size */
  489. struct pm8001_device *devices;
  490. struct pm8001_ccb_info *ccb_info;
  491. #ifdef PM8001_USE_MSIX
  492. int number_of_intr;/*will be used in remove()*/
  493. char intr_drvname[PM8001_MAX_MSIX_VEC]
  494. [PM8001_NAME_LENGTH+1+3+1];
  495. #endif
  496. #ifdef PM8001_USE_TASKLET
  497. struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
  498. #endif
  499. u32 logging_level;
  500. u32 link_rate;
  501. u32 fw_status;
  502. u32 smp_exp_mode;
  503. bool controller_fatal_error;
  504. const struct firmware *fw_image;
  505. struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
  506. u32 reset_in_progress;
  507. u32 non_fatal_count;
  508. u32 non_fatal_read_length;
  509. u32 max_q_num;
  510. u32 ib_offset;
  511. u32 ob_offset;
  512. u32 ci_offset;
  513. u32 pi_offset;
  514. u32 max_memcnt;
  515. };
  516. struct pm8001_work {
  517. struct work_struct work;
  518. struct pm8001_hba_info *pm8001_ha;
  519. void *data;
  520. int handler;
  521. };
  522. struct pm8001_fw_image_header {
  523. u8 vender_id[8];
  524. u8 product_id;
  525. u8 hardware_rev;
  526. u8 dest_partition;
  527. u8 reserved;
  528. u8 fw_rev[4];
  529. __be32 image_length;
  530. __be32 image_crc;
  531. __be32 startup_entry;
  532. } __attribute__((packed, aligned(4)));
  533. /**
  534. * FW Flash Update status values
  535. */
  536. #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
  537. #define FLASH_UPDATE_IN_PROGRESS 0x01
  538. #define FLASH_UPDATE_HDR_ERR 0x02
  539. #define FLASH_UPDATE_OFFSET_ERR 0x03
  540. #define FLASH_UPDATE_CRC_ERR 0x04
  541. #define FLASH_UPDATE_LENGTH_ERR 0x05
  542. #define FLASH_UPDATE_HW_ERR 0x06
  543. #define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
  544. #define FLASH_UPDATE_DISABLED 0x11
  545. #define NCQ_READ_LOG_FLAG 0x80000000
  546. #define NCQ_ABORT_ALL_FLAG 0x40000000
  547. #define NCQ_2ND_RLE_FLAG 0x20000000
  548. /* Device states */
  549. #define DS_OPERATIONAL 0x01
  550. #define DS_PORT_IN_RESET 0x02
  551. #define DS_IN_RECOVERY 0x03
  552. #define DS_IN_ERROR 0x04
  553. #define DS_NON_OPERATIONAL 0x07
  554. /**
  555. * brief param structure for firmware flash update.
  556. */
  557. struct fw_flash_updata_info {
  558. u32 cur_image_offset;
  559. u32 cur_image_len;
  560. u32 total_image_len;
  561. struct pm8001_prd sgl;
  562. };
  563. struct fw_control_info {
  564. u32 retcode;/*ret code (status)*/
  565. u32 phase;/*ret code phase*/
  566. u32 phaseCmplt;/*percent complete for the current
  567. update phase */
  568. u32 version;/*Hex encoded firmware version number*/
  569. u32 offset;/*Used for downloading firmware */
  570. u32 len; /*len of buffer*/
  571. u32 size;/* Used in OS VPD and Trace get size
  572. operations.*/
  573. u32 reserved;/* padding required for 64 bit
  574. alignment */
  575. u8 buffer[1];/* Start of buffer */
  576. };
  577. struct fw_control_ex {
  578. struct fw_control_info *fw_control;
  579. void *buffer;/* keep buffer pointer to be
  580. freed when the response comes*/
  581. void *virtAddr;/* keep virtual address of the data */
  582. void *usrAddr;/* keep virtual address of the
  583. user data */
  584. dma_addr_t phys_addr;
  585. u32 len; /* len of buffer */
  586. void *payload; /* pointer to IOCTL Payload */
  587. u8 inProgress;/*if 1 - the IOCTL request is in
  588. progress */
  589. void *param1;
  590. void *param2;
  591. void *param3;
  592. };
  593. /* pm8001 workqueue */
  594. extern struct workqueue_struct *pm8001_wq;
  595. /******************** function prototype *********************/
  596. int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
  597. void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
  598. u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
  599. void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
  600. struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
  601. int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  602. void *funcdata);
  603. void pm8001_scan_start(struct Scsi_Host *shost);
  604. int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
  605. int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
  606. int pm8001_abort_task(struct sas_task *task);
  607. int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
  608. int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
  609. int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
  610. int pm8001_dev_found(struct domain_device *dev);
  611. void pm8001_dev_gone(struct domain_device *dev);
  612. int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
  613. int pm8001_I_T_nexus_reset(struct domain_device *dev);
  614. int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
  615. int pm8001_query_task(struct sas_task *task);
  616. void pm8001_open_reject_retry(
  617. struct pm8001_hba_info *pm8001_ha,
  618. struct sas_task *task_to_close,
  619. struct pm8001_device *device_to_close);
  620. int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
  621. dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
  622. u32 mem_size, u32 align);
  623. void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
  624. int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
  625. struct inbound_queue_table *circularQ,
  626. u32 opCode, void *payload, size_t nb,
  627. u32 responseQueue);
  628. int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
  629. u16 messageSize, void **messagePtr);
  630. u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
  631. struct outbound_queue_table *circularQ, u8 bc);
  632. u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
  633. struct outbound_queue_table *circularQ,
  634. void **messagePtr1, u8 *pBC);
  635. int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
  636. struct pm8001_device *pm8001_dev, u32 state);
  637. int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
  638. void *payload);
  639. int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
  640. void *fw_flash_updata_info, u32 tag);
  641. int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
  642. int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
  643. int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
  644. struct pm8001_ccb_info *ccb,
  645. struct pm8001_tmf_task *tmf);
  646. int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
  647. struct pm8001_device *pm8001_dev,
  648. u8 flag, u32 task_tag, u32 cmd_tag);
  649. int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
  650. void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
  651. void pm8001_work_fn(struct work_struct *work);
  652. int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
  653. void *data, int handler);
  654. void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
  655. void *piomb);
  656. void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
  657. void *piomb);
  658. void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
  659. void *piomb);
  660. int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
  661. void *piomb);
  662. void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
  663. void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
  664. void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
  665. int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
  666. int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
  667. int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
  668. void *piomb);
  669. int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
  670. int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
  671. struct sas_task *pm8001_alloc_task(void);
  672. void pm8001_task_done(struct sas_task *task);
  673. void pm8001_free_task(struct sas_task *task);
  674. void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
  675. struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
  676. u32 device_id);
  677. int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
  678. int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
  679. void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
  680. u32 length, u8 *buf);
  681. void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
  682. u32 phy, u32 length, u32 *buf);
  683. int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
  684. ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  685. struct device_attribute *attr, char *buf);
  686. ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
  687. struct device_attribute *attr, char *buf);
  688. ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
  689. /* ctl shared API */
  690. extern struct device_attribute *pm8001_host_attrs[];
  691. static inline void
  692. pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
  693. struct sas_task *task, struct pm8001_ccb_info *ccb,
  694. u32 ccb_idx)
  695. {
  696. pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
  697. smp_mb(); /*in order to force CPU ordering*/
  698. spin_unlock(&pm8001_ha->lock);
  699. task->task_done(task);
  700. spin_lock(&pm8001_ha->lock);
  701. }
  702. #endif