pm8001_hwi.h 31 KB

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  1. /*
  2. * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
  3. *
  4. * Copyright (c) 2008-2009 USI Co., Ltd.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. */
  40. #ifndef _PMC8001_REG_H_
  41. #define _PMC8001_REG_H_
  42. #include <linux/types.h>
  43. #include <scsi/libsas.h>
  44. /* for Request Opcode of IOMB */
  45. #define OPC_INB_ECHO 1 /* 0x000 */
  46. #define OPC_INB_PHYSTART 4 /* 0x004 */
  47. #define OPC_INB_PHYSTOP 5 /* 0x005 */
  48. #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
  49. #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
  50. #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
  51. #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
  52. #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
  53. #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
  54. #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
  55. #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
  56. #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
  57. #define OPC_INB_SSP_ABORT 15 /* 0x00F */
  58. #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
  59. #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
  60. #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
  61. /* SMP_RESPONSE is removed */
  62. #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
  63. #define OPC_INB_SMP_ABORT 20 /* 0x014 */
  64. #define OPC_INB_REG_DEV 22 /* 0x016 */
  65. #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
  66. #define OPC_INB_SATA_ABORT 24 /* 0x018 */
  67. #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
  68. #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
  69. #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
  70. #define OPC_INB_GPIO 34 /* 0x022 */
  71. #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
  72. #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
  73. #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
  74. #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
  75. #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
  76. #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
  77. #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
  78. #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
  79. #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
  80. #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
  81. #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
  82. /* for Response Opcode of IOMB */
  83. #define OPC_OUB_ECHO 1 /* 0x001 */
  84. #define OPC_OUB_HW_EVENT 4 /* 0x004 */
  85. #define OPC_OUB_SSP_COMP 5 /* 0x005 */
  86. #define OPC_OUB_SMP_COMP 6 /* 0x006 */
  87. #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
  88. #define OPC_OUB_DEV_REGIST 10 /* 0x00A */
  89. #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
  90. #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
  91. #define OPC_OUB_SATA_COMP 13 /* 0x00D */
  92. #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
  93. #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
  94. #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
  95. /* SMP_RECEIVED Notification is removed */
  96. #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
  97. #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
  98. #define OPC_OUB_DEV_INFO 19 /* 0x013 */
  99. #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
  100. #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
  101. #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
  102. #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
  103. #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
  104. #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
  105. #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
  106. #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
  107. #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
  108. #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
  109. #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
  110. #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
  111. #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
  112. #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
  113. #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
  114. #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
  115. #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
  116. #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
  117. #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
  118. #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
  119. /* for phy start*/
  120. #define SPINHOLD_DISABLE (0x00 << 14)
  121. #define SPINHOLD_ENABLE (0x01 << 14)
  122. #define LINKMODE_SAS (0x01 << 12)
  123. #define LINKMODE_DSATA (0x02 << 12)
  124. #define LINKMODE_AUTO (0x03 << 12)
  125. #define LINKRATE_15 (0x01 << 8)
  126. #define LINKRATE_30 (0x02 << 8)
  127. #define LINKRATE_60 (0x04 << 8)
  128. /* for new SPC controllers MEMBASE III is shared between BIOS and DATA */
  129. #define GSM_SM_BASE 0x4F0000
  130. struct mpi_msg_hdr{
  131. __le32 header; /* Bits [11:0] - Message operation code */
  132. /* Bits [15:12] - Message Category */
  133. /* Bits [21:16] - Outboundqueue ID for the
  134. operation completion message */
  135. /* Bits [23:22] - Reserved */
  136. /* Bits [28:24] - Buffer Count, indicates how
  137. many buffer are allocated for the massage */
  138. /* Bits [30:29] - Reserved */
  139. /* Bits [31] - Message Valid bit */
  140. } __attribute__((packed, aligned(4)));
  141. /*
  142. * brief the data structure of PHY Start Command
  143. * use to describe enable the phy (64 bytes)
  144. */
  145. struct phy_start_req {
  146. __le32 tag;
  147. __le32 ase_sh_lm_slr_phyid;
  148. struct sas_identify_frame sas_identify;
  149. u32 reserved[5];
  150. } __attribute__((packed, aligned(4)));
  151. /*
  152. * brief the data structure of PHY Start Command
  153. * use to disable the phy (64 bytes)
  154. */
  155. struct phy_stop_req {
  156. __le32 tag;
  157. __le32 phy_id;
  158. u32 reserved[13];
  159. } __attribute__((packed, aligned(4)));
  160. /* set device bits fis - device to host */
  161. struct set_dev_bits_fis {
  162. u8 fis_type; /* 0xA1*/
  163. u8 n_i_pmport;
  164. /* b7 : n Bit. Notification bit. If set device needs attention. */
  165. /* b6 : i Bit. Interrupt Bit */
  166. /* b5-b4: reserved2 */
  167. /* b3-b0: PM Port */
  168. u8 status;
  169. u8 error;
  170. u32 _r_a;
  171. } __attribute__ ((packed));
  172. /* PIO setup FIS - device to host */
  173. struct pio_setup_fis {
  174. u8 fis_type; /* 0x5f */
  175. u8 i_d_pmPort;
  176. /* b7 : reserved */
  177. /* b6 : i bit. Interrupt bit */
  178. /* b5 : d bit. data transfer direction. set to 1 for device to host
  179. xfer */
  180. /* b4 : reserved */
  181. /* b3-b0: PM Port */
  182. u8 status;
  183. u8 error;
  184. u8 lbal;
  185. u8 lbam;
  186. u8 lbah;
  187. u8 device;
  188. u8 lbal_exp;
  189. u8 lbam_exp;
  190. u8 lbah_exp;
  191. u8 _r_a;
  192. u8 sector_count;
  193. u8 sector_count_exp;
  194. u8 _r_b;
  195. u8 e_status;
  196. u8 _r_c[2];
  197. u8 transfer_count;
  198. } __attribute__ ((packed));
  199. /*
  200. * brief the data structure of SATA Completion Response
  201. * use to describe the sata task response (64 bytes)
  202. */
  203. struct sata_completion_resp {
  204. __le32 tag;
  205. __le32 status;
  206. __le32 param;
  207. u32 sata_resp[12];
  208. } __attribute__((packed, aligned(4)));
  209. /*
  210. * brief the data structure of SAS HW Event Notification
  211. * use to alert the host about the hardware event(64 bytes)
  212. */
  213. struct hw_event_resp {
  214. __le32 lr_evt_status_phyid_portid;
  215. __le32 evt_param;
  216. __le32 npip_portstate;
  217. struct sas_identify_frame sas_identify;
  218. struct dev_to_host_fis sata_fis;
  219. } __attribute__((packed, aligned(4)));
  220. /*
  221. * brief the data structure of REGISTER DEVICE Command
  222. * use to describe MPI REGISTER DEVICE Command (64 bytes)
  223. */
  224. struct reg_dev_req {
  225. __le32 tag;
  226. __le32 phyid_portid;
  227. __le32 dtype_dlr_retry;
  228. __le32 firstburstsize_ITNexustimeout;
  229. u8 sas_addr[SAS_ADDR_SIZE];
  230. __le32 upper_device_id;
  231. u32 reserved[8];
  232. } __attribute__((packed, aligned(4)));
  233. /*
  234. * brief the data structure of DEREGISTER DEVICE Command
  235. * use to request spc to remove all internal resources associated
  236. * with the device id (64 bytes)
  237. */
  238. struct dereg_dev_req {
  239. __le32 tag;
  240. __le32 device_id;
  241. u32 reserved[13];
  242. } __attribute__((packed, aligned(4)));
  243. /*
  244. * brief the data structure of DEVICE_REGISTRATION Response
  245. * use to notify the completion of the device registration (64 bytes)
  246. */
  247. struct dev_reg_resp {
  248. __le32 tag;
  249. __le32 status;
  250. __le32 device_id;
  251. u32 reserved[12];
  252. } __attribute__((packed, aligned(4)));
  253. /*
  254. * brief the data structure of Local PHY Control Command
  255. * use to issue PHY CONTROL to local phy (64 bytes)
  256. */
  257. struct local_phy_ctl_req {
  258. __le32 tag;
  259. __le32 phyop_phyid;
  260. u32 reserved1[13];
  261. } __attribute__((packed, aligned(4)));
  262. /**
  263. * brief the data structure of Local Phy Control Response
  264. * use to describe MPI Local Phy Control Response (64 bytes)
  265. */
  266. struct local_phy_ctl_resp {
  267. __le32 tag;
  268. __le32 phyop_phyid;
  269. __le32 status;
  270. u32 reserved[12];
  271. } __attribute__((packed, aligned(4)));
  272. #define OP_BITS 0x0000FF00
  273. #define ID_BITS 0x000000FF
  274. /*
  275. * brief the data structure of PORT Control Command
  276. * use to control port properties (64 bytes)
  277. */
  278. struct port_ctl_req {
  279. __le32 tag;
  280. __le32 portop_portid;
  281. __le32 param0;
  282. __le32 param1;
  283. u32 reserved1[11];
  284. } __attribute__((packed, aligned(4)));
  285. /*
  286. * brief the data structure of HW Event Ack Command
  287. * use to acknowledge receive HW event (64 bytes)
  288. */
  289. struct hw_event_ack_req {
  290. __le32 tag;
  291. __le32 sea_phyid_portid;
  292. __le32 param0;
  293. __le32 param1;
  294. u32 reserved1[11];
  295. } __attribute__((packed, aligned(4)));
  296. /*
  297. * brief the data structure of SSP Completion Response
  298. * use to indicate a SSP Completion (n bytes)
  299. */
  300. struct ssp_completion_resp {
  301. __le32 tag;
  302. __le32 status;
  303. __le32 param;
  304. __le32 ssptag_rescv_rescpad;
  305. struct ssp_response_iu ssp_resp_iu;
  306. __le32 residual_count;
  307. } __attribute__((packed, aligned(4)));
  308. #define SSP_RESCV_BIT 0x00010000
  309. /*
  310. * brief the data structure of SATA EVNET esponse
  311. * use to indicate a SATA Completion (64 bytes)
  312. */
  313. struct sata_event_resp {
  314. __le32 tag;
  315. __le32 event;
  316. __le32 port_id;
  317. __le32 device_id;
  318. u32 reserved[11];
  319. } __attribute__((packed, aligned(4)));
  320. /*
  321. * brief the data structure of SSP EVNET esponse
  322. * use to indicate a SSP Completion (64 bytes)
  323. */
  324. struct ssp_event_resp {
  325. __le32 tag;
  326. __le32 event;
  327. __le32 port_id;
  328. __le32 device_id;
  329. u32 reserved[11];
  330. } __attribute__((packed, aligned(4)));
  331. /**
  332. * brief the data structure of General Event Notification Response
  333. * use to describe MPI General Event Notification Response (64 bytes)
  334. */
  335. struct general_event_resp {
  336. __le32 status;
  337. __le32 inb_IOMB_payload[14];
  338. } __attribute__((packed, aligned(4)));
  339. #define GENERAL_EVENT_PAYLOAD 14
  340. #define OPCODE_BITS 0x00000fff
  341. /*
  342. * brief the data structure of SMP Request Command
  343. * use to describe MPI SMP REQUEST Command (64 bytes)
  344. */
  345. struct smp_req {
  346. __le32 tag;
  347. __le32 device_id;
  348. __le32 len_ip_ir;
  349. /* Bits [0] - Indirect response */
  350. /* Bits [1] - Indirect Payload */
  351. /* Bits [15:2] - Reserved */
  352. /* Bits [23:16] - direct payload Len */
  353. /* Bits [31:24] - Reserved */
  354. u8 smp_req16[16];
  355. union {
  356. u8 smp_req[32];
  357. struct {
  358. __le64 long_req_addr;/* sg dma address, LE */
  359. __le32 long_req_size;/* LE */
  360. u32 _r_a;
  361. __le64 long_resp_addr;/* sg dma address, LE */
  362. __le32 long_resp_size;/* LE */
  363. u32 _r_b;
  364. } long_smp_req;/* sequencer extension */
  365. };
  366. } __attribute__((packed, aligned(4)));
  367. /*
  368. * brief the data structure of SMP Completion Response
  369. * use to describe MPI SMP Completion Response (64 bytes)
  370. */
  371. struct smp_completion_resp {
  372. __le32 tag;
  373. __le32 status;
  374. __le32 param;
  375. __le32 _r_a[12];
  376. } __attribute__((packed, aligned(4)));
  377. /*
  378. *brief the data structure of SSP SMP SATA Abort Command
  379. * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
  380. */
  381. struct task_abort_req {
  382. __le32 tag;
  383. __le32 device_id;
  384. __le32 tag_to_abort;
  385. __le32 abort_all;
  386. u32 reserved[11];
  387. } __attribute__((packed, aligned(4)));
  388. /* These flags used for SSP SMP & SATA Abort */
  389. #define ABORT_MASK 0x3
  390. #define ABORT_SINGLE 0x0
  391. #define ABORT_ALL 0x1
  392. /**
  393. * brief the data structure of SSP SATA SMP Abort Response
  394. * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
  395. */
  396. struct task_abort_resp {
  397. __le32 tag;
  398. __le32 status;
  399. __le32 scp;
  400. u32 reserved[12];
  401. } __attribute__((packed, aligned(4)));
  402. /**
  403. * brief the data structure of SAS Diagnostic Start/End Command
  404. * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
  405. */
  406. struct sas_diag_start_end_req {
  407. __le32 tag;
  408. __le32 operation_phyid;
  409. u32 reserved[13];
  410. } __attribute__((packed, aligned(4)));
  411. /**
  412. * brief the data structure of SAS Diagnostic Execute Command
  413. * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
  414. */
  415. struct sas_diag_execute_req{
  416. __le32 tag;
  417. __le32 cmdtype_cmddesc_phyid;
  418. __le32 pat1_pat2;
  419. __le32 threshold;
  420. __le32 codepat_errmsk;
  421. __le32 pmon;
  422. __le32 pERF1CTL;
  423. u32 reserved[8];
  424. } __attribute__((packed, aligned(4)));
  425. #define SAS_DIAG_PARAM_BYTES 24
  426. /*
  427. * brief the data structure of Set Device State Command
  428. * use to describe MPI Set Device State Command (64 bytes)
  429. */
  430. struct set_dev_state_req {
  431. __le32 tag;
  432. __le32 device_id;
  433. __le32 nds;
  434. u32 reserved[12];
  435. } __attribute__((packed, aligned(4)));
  436. /*
  437. * brief the data structure of sas_re_initialization
  438. */
  439. struct sas_re_initialization_req {
  440. __le32 tag;
  441. __le32 SSAHOLT;/* bit29-set max port;
  442. ** bit28-set open reject cmd retries.
  443. ** bit27-set open reject data retries.
  444. ** bit26-set open reject option, remap:1 or not:0.
  445. ** bit25-set sata head of line time out.
  446. */
  447. __le32 reserved_maxPorts;
  448. __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16;
  449. * data retries: bit15-bit0.
  450. */
  451. __le32 sata_hol_tmo;
  452. u32 reserved1[10];
  453. } __attribute__((packed, aligned(4)));
  454. /*
  455. * brief the data structure of SATA Start Command
  456. * use to describe MPI SATA IO Start Command (64 bytes)
  457. */
  458. struct sata_start_req {
  459. __le32 tag;
  460. __le32 device_id;
  461. __le32 data_len;
  462. __le32 ncqtag_atap_dir_m;
  463. struct host_to_dev_fis sata_fis;
  464. u32 reserved1;
  465. u32 reserved2;
  466. u32 addr_low;
  467. u32 addr_high;
  468. __le32 len;
  469. __le32 esgl;
  470. } __attribute__((packed, aligned(4)));
  471. /**
  472. * brief the data structure of SSP INI TM Start Command
  473. * use to describe MPI SSP INI TM Start Command (64 bytes)
  474. */
  475. struct ssp_ini_tm_start_req {
  476. __le32 tag;
  477. __le32 device_id;
  478. __le32 relate_tag;
  479. __le32 tmf;
  480. u8 lun[8];
  481. __le32 ds_ads_m;
  482. u32 reserved[8];
  483. } __attribute__((packed, aligned(4)));
  484. struct ssp_info_unit {
  485. u8 lun[8];/* SCSI Logical Unit Number */
  486. u8 reserved1;/* reserved */
  487. u8 efb_prio_attr;
  488. /* B7 : enabledFirstBurst */
  489. /* B6-3 : taskPriority */
  490. /* B2-0 : taskAttribute */
  491. u8 reserved2; /* reserved */
  492. u8 additional_cdb_len;
  493. /* B7-2 : additional_cdb_len */
  494. /* B1-0 : reserved */
  495. u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
  496. } __attribute__((packed, aligned(4)));
  497. /**
  498. * brief the data structure of SSP INI IO Start Command
  499. * use to describe MPI SSP INI IO Start Command (64 bytes)
  500. */
  501. struct ssp_ini_io_start_req {
  502. __le32 tag;
  503. __le32 device_id;
  504. __le32 data_len;
  505. __le32 dir_m_tlr;
  506. struct ssp_info_unit ssp_iu;
  507. __le32 addr_low;
  508. __le32 addr_high;
  509. __le32 len;
  510. __le32 esgl;
  511. } __attribute__((packed, aligned(4)));
  512. /**
  513. * brief the data structure of Firmware download
  514. * use to describe MPI FW DOWNLOAD Command (64 bytes)
  515. */
  516. struct fw_flash_Update_req {
  517. __le32 tag;
  518. __le32 cur_image_offset;
  519. __le32 cur_image_len;
  520. __le32 total_image_len;
  521. u32 reserved0[7];
  522. __le32 sgl_addr_lo;
  523. __le32 sgl_addr_hi;
  524. __le32 len;
  525. __le32 ext_reserved;
  526. } __attribute__((packed, aligned(4)));
  527. #define FWFLASH_IOMB_RESERVED_LEN 0x07
  528. /**
  529. * brief the data structure of FW_FLASH_UPDATE Response
  530. * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
  531. *
  532. */
  533. struct fw_flash_Update_resp {
  534. __le32 tag;
  535. __le32 status;
  536. u32 reserved[13];
  537. } __attribute__((packed, aligned(4)));
  538. /**
  539. * brief the data structure of Get NVM Data Command
  540. * use to get data from NVM in HBA(64 bytes)
  541. */
  542. struct get_nvm_data_req {
  543. __le32 tag;
  544. __le32 len_ir_vpdd;
  545. __le32 vpd_offset;
  546. u32 reserved[8];
  547. __le32 resp_addr_lo;
  548. __le32 resp_addr_hi;
  549. __le32 resp_len;
  550. u32 reserved1;
  551. } __attribute__((packed, aligned(4)));
  552. struct set_nvm_data_req {
  553. __le32 tag;
  554. __le32 len_ir_vpdd;
  555. __le32 vpd_offset;
  556. __le32 reserved[8];
  557. __le32 resp_addr_lo;
  558. __le32 resp_addr_hi;
  559. __le32 resp_len;
  560. u32 reserved1;
  561. } __attribute__((packed, aligned(4)));
  562. #define TWI_DEVICE 0x0
  563. #define C_SEEPROM 0x1
  564. #define VPD_FLASH 0x4
  565. #define AAP1_RDUMP 0x5
  566. #define IOP_RDUMP 0x6
  567. #define EXPAN_ROM 0x7
  568. #define IPMode 0x80000000
  569. #define NVMD_TYPE 0x0000000F
  570. #define NVMD_STAT 0x0000FFFF
  571. #define NVMD_LEN 0xFF000000
  572. /**
  573. * brief the data structure of Get NVMD Data Response
  574. * use to describe MPI Get NVMD Data Response (64 bytes)
  575. */
  576. struct get_nvm_data_resp {
  577. __le32 tag;
  578. __le32 ir_tda_bn_dps_das_nvm;
  579. __le32 dlen_status;
  580. __le32 nvm_data[12];
  581. } __attribute__((packed, aligned(4)));
  582. /**
  583. * brief the data structure of SAS Diagnostic Start/End Response
  584. * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
  585. *
  586. */
  587. struct sas_diag_start_end_resp {
  588. __le32 tag;
  589. __le32 status;
  590. u32 reserved[13];
  591. } __attribute__((packed, aligned(4)));
  592. /**
  593. * brief the data structure of SAS Diagnostic Execute Response
  594. * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
  595. *
  596. */
  597. struct sas_diag_execute_resp {
  598. __le32 tag;
  599. __le32 cmdtype_cmddesc_phyid;
  600. __le32 Status;
  601. __le32 ReportData;
  602. u32 reserved[11];
  603. } __attribute__((packed, aligned(4)));
  604. /**
  605. * brief the data structure of Set Device State Response
  606. * use to describe MPI Set Device State Response (64 bytes)
  607. *
  608. */
  609. struct set_dev_state_resp {
  610. __le32 tag;
  611. __le32 status;
  612. __le32 device_id;
  613. __le32 pds_nds;
  614. u32 reserved[11];
  615. } __attribute__((packed, aligned(4)));
  616. #define NDS_BITS 0x0F
  617. #define PDS_BITS 0xF0
  618. /*
  619. * HW Events type
  620. */
  621. #define HW_EVENT_RESET_START 0x01
  622. #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
  623. #define HW_EVENT_PHY_STOP_STATUS 0x03
  624. #define HW_EVENT_SAS_PHY_UP 0x04
  625. #define HW_EVENT_SATA_PHY_UP 0x05
  626. #define HW_EVENT_SATA_SPINUP_HOLD 0x06
  627. #define HW_EVENT_PHY_DOWN 0x07
  628. #define HW_EVENT_PORT_INVALID 0x08
  629. #define HW_EVENT_BROADCAST_CHANGE 0x09
  630. #define HW_EVENT_PHY_ERROR 0x0A
  631. #define HW_EVENT_BROADCAST_SES 0x0B
  632. #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
  633. #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
  634. #define HW_EVENT_MALFUNCTION 0x0E
  635. #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
  636. #define HW_EVENT_BROADCAST_EXP 0x10
  637. #define HW_EVENT_PHY_START_STATUS 0x11
  638. #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
  639. #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
  640. #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
  641. #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
  642. #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
  643. #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
  644. #define HW_EVENT_PORT_RECOVER 0x18
  645. #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
  646. #define HW_EVENT_PORT_RESET_COMPLETE 0x20
  647. #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
  648. /* port state */
  649. #define PORT_NOT_ESTABLISHED 0x00
  650. #define PORT_VALID 0x01
  651. #define PORT_LOSTCOMM 0x02
  652. #define PORT_IN_RESET 0x04
  653. #define PORT_INVALID 0x08
  654. /*
  655. * SSP/SMP/SATA IO Completion Status values
  656. */
  657. #define IO_SUCCESS 0x00
  658. #define IO_ABORTED 0x01
  659. #define IO_OVERFLOW 0x02
  660. #define IO_UNDERFLOW 0x03
  661. #define IO_FAILED 0x04
  662. #define IO_ABORT_RESET 0x05
  663. #define IO_NOT_VALID 0x06
  664. #define IO_NO_DEVICE 0x07
  665. #define IO_ILLEGAL_PARAMETER 0x08
  666. #define IO_LINK_FAILURE 0x09
  667. #define IO_PROG_ERROR 0x0A
  668. #define IO_EDC_IN_ERROR 0x0B
  669. #define IO_EDC_OUT_ERROR 0x0C
  670. #define IO_ERROR_HW_TIMEOUT 0x0D
  671. #define IO_XFER_ERROR_BREAK 0x0E
  672. #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
  673. #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
  674. #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
  675. #define IO_OPEN_CNX_ERROR_BREAK 0x12
  676. #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
  677. #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
  678. #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
  679. #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
  680. #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
  681. #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
  682. #define IO_XFER_ERROR_NAK_RECEIVED 0x19
  683. #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
  684. #define IO_XFER_ERROR_PEER_ABORTED 0x1B
  685. #define IO_XFER_ERROR_RX_FRAME 0x1C
  686. #define IO_XFER_ERROR_DMA 0x1D
  687. #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
  688. #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
  689. #define IO_XFER_ERROR_SATA 0x20
  690. #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
  691. #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
  692. #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
  693. #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
  694. #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
  695. #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
  696. #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
  697. #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
  698. #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
  699. #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
  700. #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
  701. #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
  702. #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
  703. #define IO_XFER_CMD_FRAME_ISSUED 0x36
  704. #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
  705. #define IO_PORT_IN_RESET 0x38
  706. #define IO_DS_NON_OPERATIONAL 0x39
  707. #define IO_DS_IN_RECOVERY 0x3A
  708. #define IO_TM_TAG_NOT_FOUND 0x3B
  709. #define IO_XFER_PIO_SETUP_ERROR 0x3C
  710. #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
  711. #define IO_DS_IN_ERROR 0x3E
  712. #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
  713. #define IO_ABORT_IN_PROGRESS 0x40
  714. #define IO_ABORT_DELAYED 0x41
  715. #define IO_INVALID_LENGTH 0x42
  716. /* WARNING: This error code must always be the last number.
  717. * If you add error code, modify this code also
  718. * It is used as an index
  719. */
  720. #define IO_ERROR_UNKNOWN_GENERIC 0x43
  721. /* MSGU CONFIGURATION TABLE*/
  722. #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
  723. #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
  724. #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
  725. #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
  726. #define MSGU_IBDB_SET 0x04
  727. #define MSGU_HOST_INT_STATUS 0x08
  728. #define MSGU_HOST_INT_MASK 0x0C
  729. #define MSGU_IOPIB_INT_STATUS 0x18
  730. #define MSGU_IOPIB_INT_MASK 0x1C
  731. #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
  732. #define MSGU_MSGU_CONTROL 0x24
  733. #define MSGU_ODR 0x3C/* RevB */
  734. #define MSGU_ODCR 0x40/* RevB */
  735. #define MSGU_SCRATCH_PAD_0 0x44
  736. #define MSGU_SCRATCH_PAD_1 0x48
  737. #define MSGU_SCRATCH_PAD_2 0x4C
  738. #define MSGU_SCRATCH_PAD_3 0x50
  739. #define MSGU_HOST_SCRATCH_PAD_0 0x54
  740. #define MSGU_HOST_SCRATCH_PAD_1 0x58
  741. #define MSGU_HOST_SCRATCH_PAD_2 0x5C
  742. #define MSGU_HOST_SCRATCH_PAD_3 0x60
  743. #define MSGU_HOST_SCRATCH_PAD_4 0x64
  744. #define MSGU_HOST_SCRATCH_PAD_5 0x68
  745. #define MSGU_HOST_SCRATCH_PAD_6 0x6C
  746. #define MSGU_HOST_SCRATCH_PAD_7 0x70
  747. #define MSGU_ODMR 0x74/* RevB */
  748. /* bit definition for ODMR register */
  749. #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
  750. interrupt vector */
  751. #define ODMR_CLEAR_ALL 0/* clear all
  752. interrupt vector */
  753. /* bit definition for ODCR register */
  754. #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
  755. interrupt vector*/
  756. /* MSIX Interupts */
  757. #define MSIX_TABLE_OFFSET 0x2000
  758. #define MSIX_TABLE_ELEMENT_SIZE 0x10
  759. #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
  760. #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
  761. #define MSIX_INTERRUPT_DISABLE 0x1
  762. #define MSIX_INTERRUPT_ENABLE 0x0
  763. /* state definition for Scratch Pad1 register */
  764. #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
  765. #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
  766. #define SCRATCH_PAD1_ERR 0x02 /* error state */
  767. #define SCRATCH_PAD1_RDY 0x03 /* ready state */
  768. #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
  769. #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
  770. #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
  771. Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
  772. #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
  773. Reserved bit 3 to 9 */
  774. /* state definition for Scratch Pad2 register */
  775. #define SCRATCH_PAD2_POR 0x00 /* power on state */
  776. #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
  777. #define SCRATCH_PAD2_ERR 0x02 /* error state */
  778. #define SCRATCH_PAD2_RDY 0x03 /* ready state */
  779. #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
  780. #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
  781. #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
  782. Mask, bit1-0 State */
  783. #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
  784. Reserved bit 2 to 9 */
  785. #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
  786. #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
  787. /* main configuration offset - byte offset */
  788. #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
  789. #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
  790. #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
  791. #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
  792. #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
  793. #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
  794. #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
  795. #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
  796. #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
  797. #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
  798. #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
  799. #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
  800. #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
  801. #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
  802. #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
  803. #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
  804. #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
  805. #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
  806. #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
  807. #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
  808. #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
  809. #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
  810. #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
  811. #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
  812. #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
  813. #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
  814. #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
  815. #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
  816. #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
  817. #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
  818. #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
  819. #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
  820. #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
  821. #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
  822. #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
  823. /* Gereral Status Table offset - byte offset */
  824. #define GST_GSTLEN_MPIS_OFFSET 0x00
  825. #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
  826. #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
  827. #define GST_MSGUTCNT_OFFSET 0x0C
  828. #define GST_IOPTCNT_OFFSET 0x10
  829. #define GST_PHYSTATE_OFFSET 0x18
  830. #define GST_PHYSTATE0_OFFSET 0x18
  831. #define GST_PHYSTATE1_OFFSET 0x1C
  832. #define GST_PHYSTATE2_OFFSET 0x20
  833. #define GST_PHYSTATE3_OFFSET 0x24
  834. #define GST_PHYSTATE4_OFFSET 0x28
  835. #define GST_PHYSTATE5_OFFSET 0x2C
  836. #define GST_PHYSTATE6_OFFSET 0x30
  837. #define GST_PHYSTATE7_OFFSET 0x34
  838. #define GST_RERRINFO_OFFSET 0x44
  839. /* General Status Table - MPI state */
  840. #define GST_MPI_STATE_UNINIT 0x00
  841. #define GST_MPI_STATE_INIT 0x01
  842. #define GST_MPI_STATE_TERMINATION 0x02
  843. #define GST_MPI_STATE_ERROR 0x03
  844. #define GST_MPI_STATE_MASK 0x07
  845. #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
  846. #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
  847. /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
  848. #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
  849. #define PCIE_EVENT_INTERRUPT 0x003044
  850. #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
  851. #define PCIE_ERROR_INTERRUPT 0x00304C
  852. /* signature definition for host scratch pad0 register */
  853. #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
  854. /* Signature for Soft Reset */
  855. /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
  856. #define SPC_REG_RESET 0x000000/* reset register */
  857. /* bit difination for SPC_RESET register */
  858. #define SPC_REG_RESET_OSSP 0x00000001
  859. #define SPC_REG_RESET_RAAE 0x00000002
  860. #define SPC_REG_RESET_PCS_SPBC 0x00000004
  861. #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
  862. #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
  863. #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
  864. #define SPC_REG_RESET_PCS_LM 0x00000040
  865. #define SPC_REG_RESET_PCS 0x00000080
  866. #define SPC_REG_RESET_GSM 0x00000100
  867. #define SPC_REG_RESET_DDR2 0x00010000
  868. #define SPC_REG_RESET_BDMA_CORE 0x00020000
  869. #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
  870. #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
  871. #define SPC_REG_RESET_PCIE_PWR 0x00100000
  872. #define SPC_REG_RESET_PCIE_SFT 0x00200000
  873. #define SPC_REG_RESET_PCS_SXCBI 0x00400000
  874. #define SPC_REG_RESET_LMS_SXCBI 0x00800000
  875. #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
  876. #define SPC_REG_RESET_PMIC_CORE 0x02000000
  877. #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
  878. #define SPC_REG_RESET_DEVICE 0x80000000
  879. /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
  880. #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
  881. #define MBIC_AAP1_ADDR_BASE 0x060000
  882. #define MBIC_IOP_ADDR_BASE 0x070000
  883. #define GSM_ADDR_BASE 0x0700000
  884. /* Dynamic map through Bar4 - 0x00700000 */
  885. #define GSM_CONFIG_RESET 0x00000000
  886. #define RAM_ECC_DB_ERR 0x00000018
  887. #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
  888. #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
  889. #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
  890. #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
  891. #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
  892. #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
  893. #define RB6_ACCESS_REG 0x6A0000
  894. #define HDAC_EXEC_CMD 0x0002
  895. #define HDA_C_PA 0xcb
  896. #define HDA_SEQ_ID_BITS 0x00ff0000
  897. #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
  898. #define MBIC_AAP1_ADDR_BASE 0x060000
  899. #define MBIC_IOP_ADDR_BASE 0x070000
  900. #define GSM_ADDR_BASE 0x0700000
  901. #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
  902. #define GSM_CONFIG_RESET_VALUE 0x00003b00
  903. #define GPIO_ADDR_BASE 0x00090000
  904. #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
  905. /* RB6 offset */
  906. #define SPC_RB6_OFFSET 0x80C0
  907. /* Magic number of soft reset for RB6 */
  908. #define RB6_MAGIC_NUMBER_RST 0x1234
  909. /* Device Register status */
  910. #define DEVREG_SUCCESS 0x00
  911. #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
  912. #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
  913. #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
  914. #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
  915. #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
  916. #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
  917. #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
  918. #define GSM_BASE 0x4F0000
  919. #define SHIFT_REG_64K_MASK 0xffff0000
  920. #define SHIFT_REG_BIT_SHIFT 8
  921. #endif