myrb.h 30 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
  4. *
  5. * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
  6. *
  7. * Based on the original DAC960 driver,
  8. * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
  9. * Portions Copyright 2002 by Mylex (An IBM Business Unit)
  10. *
  11. */
  12. #ifndef MYRB_H
  13. #define MYRB_H
  14. #define MYRB_MAX_LDEVS 32
  15. #define MYRB_MAX_CHANNELS 3
  16. #define MYRB_MAX_TARGETS 16
  17. #define MYRB_MAX_PHYSICAL_DEVICES 45
  18. #define MYRB_SCATTER_GATHER_LIMIT 32
  19. #define MYRB_CMD_MBOX_COUNT 256
  20. #define MYRB_STAT_MBOX_COUNT 1024
  21. #define MYRB_BLKSIZE_BITS 9
  22. #define MYRB_MAILBOX_TIMEOUT 1000000
  23. #define MYRB_DCMD_TAG 1
  24. #define MYRB_MCMD_TAG 2
  25. #define MYRB_PRIMARY_MONITOR_INTERVAL (10 * HZ)
  26. #define MYRB_SECONDARY_MONITOR_INTERVAL (60 * HZ)
  27. /*
  28. * DAC960 V1 Firmware Command Opcodes.
  29. */
  30. enum myrb_cmd_opcode {
  31. /* I/O Commands */
  32. MYRB_CMD_READ_EXTENDED = 0x33,
  33. MYRB_CMD_WRITE_EXTENDED = 0x34,
  34. MYRB_CMD_READAHEAD_EXTENDED = 0x35,
  35. MYRB_CMD_READ_EXTENDED_SG = 0xB3,
  36. MYRB_CMD_WRITE_EXTENDED_SG = 0xB4,
  37. MYRB_CMD_READ = 0x36,
  38. MYRB_CMD_READ_SG = 0xB6,
  39. MYRB_CMD_WRITE = 0x37,
  40. MYRB_CMD_WRITE_SG = 0xB7,
  41. MYRB_CMD_DCDB = 0x04,
  42. MYRB_CMD_DCDB_SG = 0x84,
  43. MYRB_CMD_FLUSH = 0x0A,
  44. /* Controller Status Related Commands */
  45. MYRB_CMD_ENQUIRY = 0x53,
  46. MYRB_CMD_ENQUIRY2 = 0x1C,
  47. MYRB_CMD_GET_LDRV_ELEMENT = 0x55,
  48. MYRB_CMD_GET_LDEV_INFO = 0x19,
  49. MYRB_CMD_IOPORTREAD = 0x39,
  50. MYRB_CMD_IOPORTWRITE = 0x3A,
  51. MYRB_CMD_GET_SD_STATS = 0x3E,
  52. MYRB_CMD_GET_PD_STATS = 0x3F,
  53. MYRB_CMD_EVENT_LOG_OPERATION = 0x72,
  54. /* Device Related Commands */
  55. MYRB_CMD_START_DEVICE = 0x10,
  56. MYRB_CMD_GET_DEVICE_STATE = 0x50,
  57. MYRB_CMD_STOP_CHANNEL = 0x13,
  58. MYRB_CMD_START_CHANNEL = 0x12,
  59. MYRB_CMD_RESET_CHANNEL = 0x1A,
  60. /* Commands Associated with Data Consistency and Errors */
  61. MYRB_CMD_REBUILD = 0x09,
  62. MYRB_CMD_REBUILD_ASYNC = 0x16,
  63. MYRB_CMD_CHECK_CONSISTENCY = 0x0F,
  64. MYRB_CMD_CHECK_CONSISTENCY_ASYNC = 0x1E,
  65. MYRB_CMD_REBUILD_STAT = 0x0C,
  66. MYRB_CMD_GET_REBUILD_PROGRESS = 0x27,
  67. MYRB_CMD_REBUILD_CONTROL = 0x1F,
  68. MYRB_CMD_READ_BADBLOCK_TABLE = 0x0B,
  69. MYRB_CMD_READ_BADDATA_TABLE = 0x25,
  70. MYRB_CMD_CLEAR_BADDATA_TABLE = 0x26,
  71. MYRB_CMD_GET_ERROR_TABLE = 0x17,
  72. MYRB_CMD_ADD_CAPACITY_ASYNC = 0x2A,
  73. MYRB_CMD_BGI_CONTROL = 0x2B,
  74. /* Configuration Related Commands */
  75. MYRB_CMD_READ_CONFIG2 = 0x3D,
  76. MYRB_CMD_WRITE_CONFIG2 = 0x3C,
  77. MYRB_CMD_READ_CONFIG_ONDISK = 0x4A,
  78. MYRB_CMD_WRITE_CONFIG_ONDISK = 0x4B,
  79. MYRB_CMD_READ_CONFIG = 0x4E,
  80. MYRB_CMD_READ_BACKUP_CONFIG = 0x4D,
  81. MYRB_CMD_WRITE_CONFIG = 0x4F,
  82. MYRB_CMD_ADD_CONFIG = 0x4C,
  83. MYRB_CMD_READ_CONFIG_LABEL = 0x48,
  84. MYRB_CMD_WRITE_CONFIG_LABEL = 0x49,
  85. /* Firmware Upgrade Related Commands */
  86. MYRB_CMD_LOAD_IMAGE = 0x20,
  87. MYRB_CMD_STORE_IMAGE = 0x21,
  88. MYRB_CMD_PROGRAM_IMAGE = 0x22,
  89. /* Diagnostic Commands */
  90. MYRB_CMD_SET_DIAGNOSTIC_MODE = 0x31,
  91. MYRB_CMD_RUN_DIAGNOSTIC = 0x32,
  92. /* Subsystem Service Commands */
  93. MYRB_CMD_GET_SUBSYS_DATA = 0x70,
  94. MYRB_CMD_SET_SUBSYS_PARAM = 0x71,
  95. /* Version 2.xx Firmware Commands */
  96. MYRB_CMD_ENQUIRY_OLD = 0x05,
  97. MYRB_CMD_GET_DEVICE_STATE_OLD = 0x14,
  98. MYRB_CMD_READ_OLD = 0x02,
  99. MYRB_CMD_WRITE_OLD = 0x03,
  100. MYRB_CMD_READ_SG_OLD = 0x82,
  101. MYRB_CMD_WRITE_SG_OLD = 0x83
  102. } __packed;
  103. /*
  104. * DAC960 V1 Firmware Command Status Codes.
  105. */
  106. #define MYRB_STATUS_SUCCESS 0x0000 /* Common */
  107. #define MYRB_STATUS_CHECK_CONDITION 0x0002 /* Common */
  108. #define MYRB_STATUS_NO_DEVICE 0x0102 /* Common */
  109. #define MYRB_STATUS_INVALID_ADDRESS 0x0105 /* Common */
  110. #define MYRB_STATUS_INVALID_PARAM 0x0105 /* Common */
  111. #define MYRB_STATUS_IRRECOVERABLE_DATA_ERROR 0x0001 /* I/O */
  112. #define MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE 0x0002 /* I/O */
  113. #define MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV 0x0105 /* I/O */
  114. #define MYRB_STATUS_BAD_DATA 0x010C /* I/O */
  115. #define MYRB_STATUS_DEVICE_BUSY 0x0008 /* DCDB */
  116. #define MYRB_STATUS_DEVICE_NONRESPONSIVE 0x000E /* DCDB */
  117. #define MYRB_STATUS_COMMAND_TERMINATED 0x000F /* DCDB */
  118. #define MYRB_STATUS_START_DEVICE_FAILED 0x0002 /* Device */
  119. #define MYRB_STATUS_INVALID_CHANNEL_OR_TARGET 0x0105 /* Device */
  120. #define MYRB_STATUS_CHANNEL_BUSY 0x0106 /* Device */
  121. #define MYRB_STATUS_OUT_OF_MEMORY 0x0107 /* Device */
  122. #define MYRB_STATUS_CHANNEL_NOT_STOPPED 0x0002 /* Device */
  123. #define MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE 0x0002 /* Consistency */
  124. #define MYRB_STATUS_RBLD_BADBLOCKS 0x0003 /* Consistency */
  125. #define MYRB_STATUS_RBLD_NEW_DISK_FAILED 0x0004 /* Consistency */
  126. #define MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS 0x0106 /* Consistency */
  127. #define MYRB_STATUS_DEPENDENT_DISK_DEAD 0x0002 /* Consistency */
  128. #define MYRB_STATUS_INCONSISTENT_BLOCKS 0x0003 /* Consistency */
  129. #define MYRB_STATUS_INVALID_OR_NONREDUNDANT_LDRV 0x0105 /* Consistency */
  130. #define MYRB_STATUS_NO_RBLD_OR_CHECK_INPROGRESS 0x0105 /* Consistency */
  131. #define MYRB_STATUS_RBLD_IN_PROGRESS_DATA_VALID 0x0000 /* Consistency */
  132. #define MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE 0x0002 /* Consistency */
  133. #define MYRB_STATUS_RBLD_FAILED_BADBLOCKS 0x0003 /* Consistency */
  134. #define MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED 0x0004 /* Consistency */
  135. #define MYRB_STATUS_RBLD_SUCCESS 0x0100 /* Consistency */
  136. #define MYRB_STATUS_RBLD_SUCCESS_TERMINATED 0x0107 /* Consistency */
  137. #define MYRB_STATUS_RBLD_NOT_CHECKED 0x0108 /* Consistency */
  138. #define MYRB_STATUS_BGI_SUCCESS 0x0100 /* Consistency */
  139. #define MYRB_STATUS_BGI_ABORTED 0x0005 /* Consistency */
  140. #define MYRB_STATUS_NO_BGI_INPROGRESS 0x0105 /* Consistency */
  141. #define MYRB_STATUS_ADD_CAPACITY_INPROGRESS 0x0004 /* Consistency */
  142. #define MYRB_STATUS_ADD_CAPACITY_FAILED_OR_SUSPENDED 0x00F4 /* Consistency */
  143. #define MYRB_STATUS_CONFIG2_CSUM_ERROR 0x0002 /* Configuration */
  144. #define MYRB_STATUS_CONFIGURATION_SUSPENDED 0x0106 /* Configuration */
  145. #define MYRB_STATUS_FAILED_TO_CONFIGURE_NVRAM 0x0105 /* Configuration */
  146. #define MYRB_STATUS_CONFIGURATION_NOT_SAVED 0x0106 /* Configuration */
  147. #define MYRB_STATUS_SUBSYS_NOTINSTALLED 0x0001 /* Subsystem */
  148. #define MYRB_STATUS_SUBSYS_FAILED 0x0002 /* Subsystem */
  149. #define MYRB_STATUS_SUBSYS_BUSY 0x0106 /* Subsystem */
  150. #define MYRB_STATUS_SUBSYS_TIMEOUT 0x0108 /* Subsystem */
  151. /*
  152. * DAC960 V1 Firmware Enquiry Command reply structure.
  153. */
  154. struct myrb_enquiry {
  155. unsigned char ldev_count; /* Byte 0 */
  156. unsigned int rsvd1:24; /* Bytes 1-3 */
  157. unsigned int ldev_sizes[32]; /* Bytes 4-131 */
  158. unsigned short flash_age; /* Bytes 132-133 */
  159. struct {
  160. unsigned char deferred:1; /* Byte 134 Bit 0 */
  161. unsigned char low_bat:1; /* Byte 134 Bit 1 */
  162. unsigned char rsvd2:6; /* Byte 134 Bits 2-7 */
  163. } status;
  164. unsigned char rsvd3:8; /* Byte 135 */
  165. unsigned char fw_minor_version; /* Byte 136 */
  166. unsigned char fw_major_version; /* Byte 137 */
  167. enum {
  168. MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS = 0x00,
  169. MYRB_STDBY_RBLD_IN_PROGRESS = 0x01,
  170. MYRB_BG_RBLD_IN_PROGRESS = 0x02,
  171. MYRB_BG_CHECK_IN_PROGRESS = 0x03,
  172. MYRB_STDBY_RBLD_COMPLETED_WITH_ERROR = 0xFF,
  173. MYRB_BG_RBLD_OR_CHECK_FAILED_DRIVE_FAILED = 0xF0,
  174. MYRB_BG_RBLD_OR_CHECK_FAILED_LDEV_FAILED = 0xF1,
  175. MYRB_BG_RBLD_OR_CHECK_FAILED_OTHER = 0xF2,
  176. MYRB_BG_RBLD_OR_CHECK_SUCCESS_TERMINATED = 0xF3
  177. } __packed rbld; /* Byte 138 */
  178. unsigned char max_tcq; /* Byte 139 */
  179. unsigned char ldev_offline; /* Byte 140 */
  180. unsigned char rsvd4:8; /* Byte 141 */
  181. unsigned short ev_seq; /* Bytes 142-143 */
  182. unsigned char ldev_critical; /* Byte 144 */
  183. unsigned int rsvd5:24; /* Bytes 145-147 */
  184. unsigned char pdev_dead; /* Byte 148 */
  185. unsigned char rsvd6:8; /* Byte 149 */
  186. unsigned char rbld_count; /* Byte 150 */
  187. struct {
  188. unsigned char rsvd7:3; /* Byte 151 Bits 0-2 */
  189. unsigned char bbu_present:1; /* Byte 151 Bit 3 */
  190. unsigned char rsvd8:4; /* Byte 151 Bits 4-7 */
  191. } misc;
  192. struct {
  193. unsigned char target;
  194. unsigned char channel;
  195. } dead_drives[21]; /* Bytes 152-194 */
  196. unsigned char rsvd9[62]; /* Bytes 195-255 */
  197. } __packed;
  198. /*
  199. * DAC960 V1 Firmware Enquiry2 Command reply structure.
  200. */
  201. struct myrb_enquiry2 {
  202. struct {
  203. enum {
  204. DAC960_V1_P_PD_PU = 0x01,
  205. DAC960_V1_PL = 0x02,
  206. DAC960_V1_PG = 0x10,
  207. DAC960_V1_PJ = 0x11,
  208. DAC960_V1_PR = 0x12,
  209. DAC960_V1_PT = 0x13,
  210. DAC960_V1_PTL0 = 0x14,
  211. DAC960_V1_PRL = 0x15,
  212. DAC960_V1_PTL1 = 0x16,
  213. DAC960_V1_1164P = 0x20
  214. } __packed sub_model; /* Byte 0 */
  215. unsigned char actual_channels; /* Byte 1 */
  216. enum {
  217. MYRB_5_CHANNEL_BOARD = 0x01,
  218. MYRB_3_CHANNEL_BOARD = 0x02,
  219. MYRB_2_CHANNEL_BOARD = 0x03,
  220. MYRB_3_CHANNEL_ASIC_DAC = 0x04
  221. } __packed model; /* Byte 2 */
  222. enum {
  223. MYRB_EISA_CONTROLLER = 0x01,
  224. MYRB_MCA_CONTROLLER = 0x02,
  225. MYRB_PCI_CONTROLLER = 0x03,
  226. MYRB_SCSI_TO_SCSI = 0x08
  227. } __packed controller; /* Byte 3 */
  228. } hw; /* Bytes 0-3 */
  229. /* MajorVersion.MinorVersion-FirmwareType-TurnID */
  230. struct {
  231. unsigned char major_version; /* Byte 4 */
  232. unsigned char minor_version; /* Byte 5 */
  233. unsigned char turn_id; /* Byte 6 */
  234. char firmware_type; /* Byte 7 */
  235. } fw; /* Bytes 4-7 */
  236. unsigned int rsvd1; /* Byte 8-11 */
  237. unsigned char cfg_chan; /* Byte 12 */
  238. unsigned char cur_chan; /* Byte 13 */
  239. unsigned char max_targets; /* Byte 14 */
  240. unsigned char max_tcq; /* Byte 15 */
  241. unsigned char max_ldev; /* Byte 16 */
  242. unsigned char max_arms; /* Byte 17 */
  243. unsigned char max_spans; /* Byte 18 */
  244. unsigned char rsvd2; /* Byte 19 */
  245. unsigned int rsvd3; /* Bytes 20-23 */
  246. unsigned int mem_size; /* Bytes 24-27 */
  247. unsigned int cache_size; /* Bytes 28-31 */
  248. unsigned int flash_size; /* Bytes 32-35 */
  249. unsigned int nvram_size; /* Bytes 36-39 */
  250. struct {
  251. enum {
  252. MYRB_RAM_TYPE_DRAM = 0x0,
  253. MYRB_RAM_TYPE_EDO = 0x1,
  254. MYRB_RAM_TYPE_SDRAM = 0x2,
  255. MYRB_RAM_TYPE_Last = 0x7
  256. } __packed ram:3; /* Byte 40 Bits 0-2 */
  257. enum {
  258. MYRB_ERR_CORR_None = 0x0,
  259. MYRB_ERR_CORR_Parity = 0x1,
  260. MYRB_ERR_CORR_ECC = 0x2,
  261. MYRB_ERR_CORR_Last = 0x7
  262. } __packed ec:3; /* Byte 40 Bits 3-5 */
  263. unsigned char fast_page:1; /* Byte 40 Bit 6 */
  264. unsigned char low_power:1; /* Byte 40 Bit 7 */
  265. unsigned char rsvd4; /* Bytes 41 */
  266. } mem_type;
  267. unsigned short clock_speed; /* Bytes 42-43 */
  268. unsigned short mem_speed; /* Bytes 44-45 */
  269. unsigned short hw_speed; /* Bytes 46-47 */
  270. unsigned char rsvd5[12]; /* Bytes 48-59 */
  271. unsigned short max_cmds; /* Bytes 60-61 */
  272. unsigned short max_sge; /* Bytes 62-63 */
  273. unsigned short max_drv_cmds; /* Bytes 64-65 */
  274. unsigned short max_io_desc; /* Bytes 66-67 */
  275. unsigned short max_sectors; /* Bytes 68-69 */
  276. unsigned char latency; /* Byte 70 */
  277. unsigned char rsvd6; /* Byte 71 */
  278. unsigned char scsi_tmo; /* Byte 72 */
  279. unsigned char rsvd7; /* Byte 73 */
  280. unsigned short min_freelines; /* Bytes 74-75 */
  281. unsigned char rsvd8[8]; /* Bytes 76-83 */
  282. unsigned char rbld_rate_const; /* Byte 84 */
  283. unsigned char rsvd9[11]; /* Byte 85-95 */
  284. unsigned short pdrv_block_size; /* Bytes 96-97 */
  285. unsigned short ldev_block_size; /* Bytes 98-99 */
  286. unsigned short max_blocks_per_cmd; /* Bytes 100-101 */
  287. unsigned short block_factor; /* Bytes 102-103 */
  288. unsigned short cacheline_size; /* Bytes 104-105 */
  289. struct {
  290. enum {
  291. MYRB_WIDTH_NARROW_8BIT = 0x0,
  292. MYRB_WIDTH_WIDE_16BIT = 0x1,
  293. MYRB_WIDTH_WIDE_32BIT = 0x2
  294. } __packed bus_width:2; /* Byte 106 Bits 0-1 */
  295. enum {
  296. MYRB_SCSI_SPEED_FAST = 0x0,
  297. MYRB_SCSI_SPEED_ULTRA = 0x1,
  298. MYRB_SCSI_SPEED_ULTRA2 = 0x2
  299. } __packed bus_speed:2; /* Byte 106 Bits 2-3 */
  300. unsigned char differential:1; /* Byte 106 Bit 4 */
  301. unsigned char rsvd10:3; /* Byte 106 Bits 5-7 */
  302. } scsi_cap;
  303. unsigned char rsvd11[5]; /* Byte 107-111 */
  304. unsigned short fw_build; /* Bytes 112-113 */
  305. enum {
  306. MYRB_FAULT_AEMI = 0x01,
  307. MYRB_FAULT_OEM1 = 0x02,
  308. MYRB_FAULT_OEM2 = 0x04,
  309. MYRB_FAULT_OEM3 = 0x08,
  310. MYRB_FAULT_CONNER = 0x10,
  311. MYRB_FAULT_SAFTE = 0x20
  312. } __packed fault_mgmt; /* Byte 114 */
  313. unsigned char rsvd12; /* Byte 115 */
  314. struct {
  315. unsigned int clustering:1; /* Byte 116 Bit 0 */
  316. unsigned int online_RAID_expansion:1; /* Byte 116 Bit 1 */
  317. unsigned int readahead:1; /* Byte 116 Bit 2 */
  318. unsigned int bgi:1; /* Byte 116 Bit 3 */
  319. unsigned int rsvd13:28; /* Bytes 116-119 */
  320. } fw_features;
  321. unsigned char rsvd14[8]; /* Bytes 120-127 */
  322. } __packed;
  323. /*
  324. * DAC960 V1 Firmware Logical Drive State type.
  325. */
  326. enum myrb_devstate {
  327. MYRB_DEVICE_DEAD = 0x00,
  328. MYRB_DEVICE_WO = 0x02,
  329. MYRB_DEVICE_ONLINE = 0x03,
  330. MYRB_DEVICE_CRITICAL = 0x04,
  331. MYRB_DEVICE_STANDBY = 0x10,
  332. MYRB_DEVICE_OFFLINE = 0xFF
  333. } __packed;
  334. /*
  335. * DAC960 V1 RAID Levels
  336. */
  337. enum myrb_raidlevel {
  338. MYRB_RAID_LEVEL0 = 0x0, /* RAID 0 */
  339. MYRB_RAID_LEVEL1 = 0x1, /* RAID 1 */
  340. MYRB_RAID_LEVEL3 = 0x3, /* RAID 3 */
  341. MYRB_RAID_LEVEL5 = 0x5, /* RAID 5 */
  342. MYRB_RAID_LEVEL6 = 0x6, /* RAID 6 */
  343. MYRB_RAID_JBOD = 0x7, /* RAID 7 (JBOD) */
  344. } __packed;
  345. /*
  346. * DAC960 V1 Firmware Logical Drive Information structure.
  347. */
  348. struct myrb_ldev_info {
  349. unsigned int size; /* Bytes 0-3 */
  350. enum myrb_devstate state; /* Byte 4 */
  351. unsigned int raid_level:7; /* Byte 5 Bits 0-6 */
  352. unsigned int wb_enabled:1; /* Byte 5 Bit 7 */
  353. unsigned int rsvd:16; /* Bytes 6-7 */
  354. };
  355. /*
  356. * DAC960 V1 Firmware Perform Event Log Operation Types.
  357. */
  358. #define DAC960_V1_GetEventLogEntry 0x00
  359. /*
  360. * DAC960 V1 Firmware Get Event Log Entry Command reply structure.
  361. */
  362. struct myrb_log_entry {
  363. unsigned char msg_type; /* Byte 0 */
  364. unsigned char msg_len; /* Byte 1 */
  365. unsigned char target:5; /* Byte 2 Bits 0-4 */
  366. unsigned char channel:3; /* Byte 2 Bits 5-7 */
  367. unsigned char lun:6; /* Byte 3 Bits 0-5 */
  368. unsigned char rsvd1:2; /* Byte 3 Bits 6-7 */
  369. unsigned short seq_num; /* Bytes 4-5 */
  370. unsigned char sense[26]; /* Bytes 6-31 */
  371. };
  372. /*
  373. * DAC960 V1 Firmware Get Device State Command reply structure.
  374. * The structure is padded by 2 bytes for compatibility with Version 2.xx
  375. * Firmware.
  376. */
  377. struct myrb_pdev_state {
  378. unsigned int present:1; /* Byte 0 Bit 0 */
  379. unsigned int :7; /* Byte 0 Bits 1-7 */
  380. enum {
  381. MYRB_TYPE_OTHER = 0x0,
  382. MYRB_TYPE_DISK = 0x1,
  383. MYRB_TYPE_TAPE = 0x2,
  384. MYRB_TYPE_CDROM_OR_WORM = 0x3
  385. } __packed devtype:2; /* Byte 1 Bits 0-1 */
  386. unsigned int rsvd1:1; /* Byte 1 Bit 2 */
  387. unsigned int fast20:1; /* Byte 1 Bit 3 */
  388. unsigned int sync:1; /* Byte 1 Bit 4 */
  389. unsigned int fast:1; /* Byte 1 Bit 5 */
  390. unsigned int wide:1; /* Byte 1 Bit 6 */
  391. unsigned int tcq_supported:1; /* Byte 1 Bit 7 */
  392. enum myrb_devstate state; /* Byte 2 */
  393. unsigned int rsvd2:8; /* Byte 3 */
  394. unsigned int sync_multiplier; /* Byte 4 */
  395. unsigned int sync_offset:5; /* Byte 5 Bits 0-4 */
  396. unsigned int rsvd3:3; /* Byte 5 Bits 5-7 */
  397. unsigned int size; /* Bytes 6-9 */
  398. unsigned int rsvd4:16; /* Bytes 10-11 */
  399. } __packed;
  400. /*
  401. * DAC960 V1 Firmware Get Rebuild Progress Command reply structure.
  402. */
  403. struct myrb_rbld_progress {
  404. unsigned int ldev_num; /* Bytes 0-3 */
  405. unsigned int ldev_size; /* Bytes 4-7 */
  406. unsigned int blocks_left; /* Bytes 8-11 */
  407. };
  408. /*
  409. * DAC960 V1 Firmware Background Initialization Status Command reply structure.
  410. */
  411. struct myrb_bgi_status {
  412. unsigned int ldev_size; /* Bytes 0-3 */
  413. unsigned int blocks_done; /* Bytes 4-7 */
  414. unsigned char rsvd1[12]; /* Bytes 8-19 */
  415. unsigned int ldev_num; /* Bytes 20-23 */
  416. unsigned char raid_level; /* Byte 24 */
  417. enum {
  418. MYRB_BGI_INVALID = 0x00,
  419. MYRB_BGI_STARTED = 0x02,
  420. MYRB_BGI_INPROGRESS = 0x04,
  421. MYRB_BGI_SUSPENDED = 0x05,
  422. MYRB_BGI_CANCELLED = 0x06
  423. } __packed status; /* Byte 25 */
  424. unsigned char rsvd2[6]; /* Bytes 26-31 */
  425. };
  426. /*
  427. * DAC960 V1 Firmware Error Table Entry structure.
  428. */
  429. struct myrb_error_entry {
  430. unsigned char parity_err; /* Byte 0 */
  431. unsigned char soft_err; /* Byte 1 */
  432. unsigned char hard_err; /* Byte 2 */
  433. unsigned char misc_err; /* Byte 3 */
  434. };
  435. /*
  436. * DAC960 V1 Firmware Read Config2 Command reply structure.
  437. */
  438. struct myrb_config2 {
  439. unsigned rsvd1:1; /* Byte 0 Bit 0 */
  440. unsigned active_negation:1; /* Byte 0 Bit 1 */
  441. unsigned rsvd2:5; /* Byte 0 Bits 2-6 */
  442. unsigned no_rescan_on_reset_during_scan:1; /* Byte 0 Bit 7 */
  443. unsigned StorageWorks_support:1; /* Byte 1 Bit 0 */
  444. unsigned HewlettPackard_support:1; /* Byte 1 Bit 1 */
  445. unsigned no_disconnect_on_first_command:1; /* Byte 1 Bit 2 */
  446. unsigned rsvd3:2; /* Byte 1 Bits 3-4 */
  447. unsigned AEMI_ARM:1; /* Byte 1 Bit 5 */
  448. unsigned AEMI_OFM:1; /* Byte 1 Bit 6 */
  449. unsigned rsvd4:1; /* Byte 1 Bit 7 */
  450. enum {
  451. MYRB_OEMID_MYLEX = 0x00,
  452. MYRB_OEMID_IBM = 0x08,
  453. MYRB_OEMID_HP = 0x0A,
  454. MYRB_OEMID_DEC = 0x0C,
  455. MYRB_OEMID_SIEMENS = 0x10,
  456. MYRB_OEMID_INTEL = 0x12
  457. } __packed OEMID; /* Byte 2 */
  458. unsigned char oem_model_number; /* Byte 3 */
  459. unsigned char physical_sector; /* Byte 4 */
  460. unsigned char logical_sector; /* Byte 5 */
  461. unsigned char block_factor; /* Byte 6 */
  462. unsigned readahead_enabled:1; /* Byte 7 Bit 0 */
  463. unsigned low_BIOS_delay:1; /* Byte 7 Bit 1 */
  464. unsigned rsvd5:2; /* Byte 7 Bits 2-3 */
  465. unsigned restrict_reassign_to_one_sector:1; /* Byte 7 Bit 4 */
  466. unsigned rsvd6:1; /* Byte 7 Bit 5 */
  467. unsigned FUA_during_write_recovery:1; /* Byte 7 Bit 6 */
  468. unsigned enable_LeftSymmetricRAID5Algorithm:1; /* Byte 7 Bit 7 */
  469. unsigned char default_rebuild_rate; /* Byte 8 */
  470. unsigned char rsvd7; /* Byte 9 */
  471. unsigned char blocks_per_cacheline; /* Byte 10 */
  472. unsigned char blocks_per_stripe; /* Byte 11 */
  473. struct {
  474. enum {
  475. MYRB_SPEED_ASYNC = 0x0,
  476. MYRB_SPEED_SYNC_8MHz = 0x1,
  477. MYRB_SPEED_SYNC_5MHz = 0x2,
  478. MYRB_SPEED_SYNC_10_OR_20MHz = 0x3
  479. } __packed speed:2; /* Byte 11 Bits 0-1 */
  480. unsigned force_8bit:1; /* Byte 11 Bit 2 */
  481. unsigned disable_fast20:1; /* Byte 11 Bit 3 */
  482. unsigned rsvd8:3; /* Byte 11 Bits 4-6 */
  483. unsigned enable_tcq:1; /* Byte 11 Bit 7 */
  484. } __packed channelparam[6]; /* Bytes 12-17 */
  485. unsigned char SCSIInitiatorID; /* Byte 18 */
  486. unsigned char rsvd9; /* Byte 19 */
  487. enum {
  488. MYRB_STARTUP_CONTROLLER_SPINUP = 0x00,
  489. MYRB_STARTUP_POWERON_SPINUP = 0x01
  490. } __packed startup; /* Byte 20 */
  491. unsigned char simultaneous_device_spinup_count; /* Byte 21 */
  492. unsigned char seconds_delay_between_spinups; /* Byte 22 */
  493. unsigned char rsvd10[29]; /* Bytes 23-51 */
  494. unsigned BIOS_disabled:1; /* Byte 52 Bit 0 */
  495. unsigned CDROM_boot_enabled:1; /* Byte 52 Bit 1 */
  496. unsigned rsvd11:3; /* Byte 52 Bits 2-4 */
  497. enum {
  498. MYRB_GEOM_128_32 = 0x0,
  499. MYRB_GEOM_255_63 = 0x1,
  500. MYRB_GEOM_RESERVED1 = 0x2,
  501. MYRB_GEOM_RESERVED2 = 0x3
  502. } __packed drive_geometry:2; /* Byte 52 Bits 5-6 */
  503. unsigned rsvd12:1; /* Byte 52 Bit 7 */
  504. unsigned char rsvd13[9]; /* Bytes 53-61 */
  505. unsigned short csum; /* Bytes 62-63 */
  506. };
  507. /*
  508. * DAC960 V1 Firmware DCDB request structure.
  509. */
  510. struct myrb_dcdb {
  511. unsigned target:4; /* Byte 0 Bits 0-3 */
  512. unsigned channel:4; /* Byte 0 Bits 4-7 */
  513. enum {
  514. MYRB_DCDB_XFER_NONE = 0,
  515. MYRB_DCDB_XFER_DEVICE_TO_SYSTEM = 1,
  516. MYRB_DCDB_XFER_SYSTEM_TO_DEVICE = 2,
  517. MYRB_DCDB_XFER_ILLEGAL = 3
  518. } __packed data_xfer:2; /* Byte 1 Bits 0-1 */
  519. unsigned early_status:1; /* Byte 1 Bit 2 */
  520. unsigned rsvd1:1; /* Byte 1 Bit 3 */
  521. enum {
  522. MYRB_DCDB_TMO_24_HRS = 0,
  523. MYRB_DCDB_TMO_10_SECS = 1,
  524. MYRB_DCDB_TMO_60_SECS = 2,
  525. MYRB_DCDB_TMO_10_MINS = 3
  526. } __packed timeout:2; /* Byte 1 Bits 4-5 */
  527. unsigned no_autosense:1; /* Byte 1 Bit 6 */
  528. unsigned allow_disconnect:1; /* Byte 1 Bit 7 */
  529. unsigned short xfer_len_lo; /* Bytes 2-3 */
  530. u32 dma_addr; /* Bytes 4-7 */
  531. unsigned char cdb_len:4; /* Byte 8 Bits 0-3 */
  532. unsigned char xfer_len_hi4:4; /* Byte 8 Bits 4-7 */
  533. unsigned char sense_len; /* Byte 9 */
  534. unsigned char cdb[12]; /* Bytes 10-21 */
  535. unsigned char sense[64]; /* Bytes 22-85 */
  536. unsigned char status; /* Byte 86 */
  537. unsigned char rsvd2; /* Byte 87 */
  538. };
  539. /*
  540. * DAC960 V1 Firmware Scatter/Gather List Type 1 32 Bit Address
  541. *32 Bit Byte Count structure.
  542. */
  543. struct myrb_sge {
  544. u32 sge_addr; /* Bytes 0-3 */
  545. u32 sge_count; /* Bytes 4-7 */
  546. };
  547. /*
  548. * 13 Byte DAC960 V1 Firmware Command Mailbox structure.
  549. * Bytes 13-15 are not used. The structure is padded to 16 bytes for
  550. * efficient access.
  551. */
  552. union myrb_cmd_mbox {
  553. unsigned int words[4]; /* Words 0-3 */
  554. unsigned char bytes[16]; /* Bytes 0-15 */
  555. struct {
  556. enum myrb_cmd_opcode opcode; /* Byte 0 */
  557. unsigned char id; /* Byte 1 */
  558. unsigned char rsvd[14]; /* Bytes 2-15 */
  559. } __packed common;
  560. struct {
  561. enum myrb_cmd_opcode opcode; /* Byte 0 */
  562. unsigned char id; /* Byte 1 */
  563. unsigned char rsvd1[6]; /* Bytes 2-7 */
  564. u32 addr; /* Bytes 8-11 */
  565. unsigned char rsvd2[4]; /* Bytes 12-15 */
  566. } __packed type3;
  567. struct {
  568. enum myrb_cmd_opcode opcode; /* Byte 0 */
  569. unsigned char id; /* Byte 1 */
  570. unsigned char optype; /* Byte 2 */
  571. unsigned char rsvd1[5]; /* Bytes 3-7 */
  572. u32 addr; /* Bytes 8-11 */
  573. unsigned char rsvd2[4]; /* Bytes 12-15 */
  574. } __packed type3B;
  575. struct {
  576. enum myrb_cmd_opcode opcode; /* Byte 0 */
  577. unsigned char id; /* Byte 1 */
  578. unsigned char rsvd1[5]; /* Bytes 2-6 */
  579. unsigned char ldev_num:6; /* Byte 7 Bits 0-6 */
  580. unsigned char auto_restore:1; /* Byte 7 Bit 7 */
  581. unsigned char rsvd2[8]; /* Bytes 8-15 */
  582. } __packed type3C;
  583. struct {
  584. enum myrb_cmd_opcode opcode; /* Byte 0 */
  585. unsigned char id; /* Byte 1 */
  586. unsigned char channel; /* Byte 2 */
  587. unsigned char target; /* Byte 3 */
  588. enum myrb_devstate state; /* Byte 4 */
  589. unsigned char rsvd1[3]; /* Bytes 5-7 */
  590. u32 addr; /* Bytes 8-11 */
  591. unsigned char rsvd2[4]; /* Bytes 12-15 */
  592. } __packed type3D;
  593. struct {
  594. enum myrb_cmd_opcode opcode; /* Byte 0 */
  595. unsigned char id; /* Byte 1 */
  596. unsigned char optype; /* Byte 2 */
  597. unsigned char opqual; /* Byte 3 */
  598. unsigned short ev_seq; /* Bytes 4-5 */
  599. unsigned char rsvd1[2]; /* Bytes 6-7 */
  600. u32 addr; /* Bytes 8-11 */
  601. unsigned char rsvd2[4]; /* Bytes 12-15 */
  602. } __packed type3E;
  603. struct {
  604. enum myrb_cmd_opcode opcode; /* Byte 0 */
  605. unsigned char id; /* Byte 1 */
  606. unsigned char rsvd1[2]; /* Bytes 2-3 */
  607. unsigned char rbld_rate; /* Byte 4 */
  608. unsigned char rsvd2[3]; /* Bytes 5-7 */
  609. u32 addr; /* Bytes 8-11 */
  610. unsigned char rsvd3[4]; /* Bytes 12-15 */
  611. } __packed type3R;
  612. struct {
  613. enum myrb_cmd_opcode opcode; /* Byte 0 */
  614. unsigned char id; /* Byte 1 */
  615. unsigned short xfer_len; /* Bytes 2-3 */
  616. unsigned int lba; /* Bytes 4-7 */
  617. u32 addr; /* Bytes 8-11 */
  618. unsigned char ldev_num; /* Byte 12 */
  619. unsigned char rsvd[3]; /* Bytes 13-15 */
  620. } __packed type4;
  621. struct {
  622. enum myrb_cmd_opcode opcode; /* Byte 0 */
  623. unsigned char id; /* Byte 1 */
  624. struct {
  625. unsigned short xfer_len:11; /* Bytes 2-3 */
  626. unsigned char ldev_num:5; /* Byte 3 Bits 3-7 */
  627. } __packed ld;
  628. unsigned int lba; /* Bytes 4-7 */
  629. u32 addr; /* Bytes 8-11 */
  630. unsigned char sg_count:6; /* Byte 12 Bits 0-5 */
  631. enum {
  632. MYRB_SGL_ADDR32_COUNT32 = 0x0,
  633. MYRB_SGL_ADDR32_COUNT16 = 0x1,
  634. MYRB_SGL_COUNT32_ADDR32 = 0x2,
  635. MYRB_SGL_COUNT16_ADDR32 = 0x3
  636. } __packed sg_type:2; /* Byte 12 Bits 6-7 */
  637. unsigned char rsvd[3]; /* Bytes 13-15 */
  638. } __packed type5;
  639. struct {
  640. enum myrb_cmd_opcode opcode; /* Byte 0 */
  641. unsigned char id; /* Byte 1 */
  642. unsigned char opcode2; /* Byte 2 */
  643. unsigned char rsvd1:8; /* Byte 3 */
  644. u32 cmd_mbox_addr; /* Bytes 4-7 */
  645. u32 stat_mbox_addr; /* Bytes 8-11 */
  646. unsigned char rsvd2[4]; /* Bytes 12-15 */
  647. } __packed typeX;
  648. };
  649. /*
  650. * DAC960 V1 Firmware Controller Status Mailbox structure.
  651. */
  652. struct myrb_stat_mbox {
  653. unsigned char id; /* Byte 0 */
  654. unsigned char rsvd:7; /* Byte 1 Bits 0-6 */
  655. unsigned char valid:1; /* Byte 1 Bit 7 */
  656. unsigned short status; /* Bytes 2-3 */
  657. };
  658. struct myrb_cmdblk {
  659. union myrb_cmd_mbox mbox;
  660. unsigned short status;
  661. struct completion *completion;
  662. struct myrb_dcdb *dcdb;
  663. dma_addr_t dcdb_addr;
  664. struct myrb_sge *sgl;
  665. dma_addr_t sgl_addr;
  666. };
  667. struct myrb_hba {
  668. unsigned int ldev_block_size;
  669. unsigned char ldev_geom_heads;
  670. unsigned char ldev_geom_sectors;
  671. unsigned char bus_width;
  672. unsigned short stripe_size;
  673. unsigned short segment_size;
  674. unsigned short new_ev_seq;
  675. unsigned short old_ev_seq;
  676. bool dual_mode_interface;
  677. bool bgi_status_supported;
  678. bool safte_enabled;
  679. bool need_ldev_info;
  680. bool need_err_info;
  681. bool need_rbld;
  682. bool need_cc_status;
  683. bool need_bgi_status;
  684. bool rbld_first;
  685. struct pci_dev *pdev;
  686. struct Scsi_Host *host;
  687. struct workqueue_struct *work_q;
  688. char work_q_name[20];
  689. struct delayed_work monitor_work;
  690. unsigned long primary_monitor_time;
  691. unsigned long secondary_monitor_time;
  692. struct dma_pool *sg_pool;
  693. struct dma_pool *dcdb_pool;
  694. spinlock_t queue_lock;
  695. void (*qcmd)(struct myrb_hba *cs, struct myrb_cmdblk *cmd_blk);
  696. void (*write_cmd_mbox)(union myrb_cmd_mbox *next_mbox,
  697. union myrb_cmd_mbox *cmd_mbox);
  698. void (*get_cmd_mbox)(void __iomem *base);
  699. void (*disable_intr)(void __iomem *base);
  700. void (*reset)(void __iomem *base);
  701. unsigned int ctlr_num;
  702. unsigned char model_name[20];
  703. unsigned char fw_version[12];
  704. unsigned int irq;
  705. phys_addr_t io_addr;
  706. phys_addr_t pci_addr;
  707. void __iomem *io_base;
  708. void __iomem *mmio_base;
  709. size_t cmd_mbox_size;
  710. dma_addr_t cmd_mbox_addr;
  711. union myrb_cmd_mbox *first_cmd_mbox;
  712. union myrb_cmd_mbox *last_cmd_mbox;
  713. union myrb_cmd_mbox *next_cmd_mbox;
  714. union myrb_cmd_mbox *prev_cmd_mbox1;
  715. union myrb_cmd_mbox *prev_cmd_mbox2;
  716. size_t stat_mbox_size;
  717. dma_addr_t stat_mbox_addr;
  718. struct myrb_stat_mbox *first_stat_mbox;
  719. struct myrb_stat_mbox *last_stat_mbox;
  720. struct myrb_stat_mbox *next_stat_mbox;
  721. struct myrb_cmdblk dcmd_blk;
  722. struct myrb_cmdblk mcmd_blk;
  723. struct mutex dcmd_mutex;
  724. struct myrb_enquiry *enquiry;
  725. dma_addr_t enquiry_addr;
  726. struct myrb_error_entry *err_table;
  727. dma_addr_t err_table_addr;
  728. unsigned short last_rbld_status;
  729. struct myrb_ldev_info *ldev_info_buf;
  730. dma_addr_t ldev_info_addr;
  731. struct myrb_bgi_status bgi_status;
  732. struct mutex dma_mutex;
  733. };
  734. /*
  735. * DAC960 LA Series Controller Interface Register Offsets.
  736. */
  737. #define DAC960_LA_mmio_size 0x80
  738. enum DAC960_LA_reg_offset {
  739. DAC960_LA_IRQMASK_OFFSET = 0x34,
  740. DAC960_LA_CMDOP_OFFSET = 0x50,
  741. DAC960_LA_CMDID_OFFSET = 0x51,
  742. DAC960_LA_MBOX2_OFFSET = 0x52,
  743. DAC960_LA_MBOX3_OFFSET = 0x53,
  744. DAC960_LA_MBOX4_OFFSET = 0x54,
  745. DAC960_LA_MBOX5_OFFSET = 0x55,
  746. DAC960_LA_MBOX6_OFFSET = 0x56,
  747. DAC960_LA_MBOX7_OFFSET = 0x57,
  748. DAC960_LA_MBOX8_OFFSET = 0x58,
  749. DAC960_LA_MBOX9_OFFSET = 0x59,
  750. DAC960_LA_MBOX10_OFFSET = 0x5A,
  751. DAC960_LA_MBOX11_OFFSET = 0x5B,
  752. DAC960_LA_MBOX12_OFFSET = 0x5C,
  753. DAC960_LA_STSID_OFFSET = 0x5D,
  754. DAC960_LA_STS_OFFSET = 0x5E,
  755. DAC960_LA_IDB_OFFSET = 0x60,
  756. DAC960_LA_ODB_OFFSET = 0x61,
  757. DAC960_LA_ERRSTS_OFFSET = 0x63,
  758. };
  759. /*
  760. * DAC960 LA Series Inbound Door Bell Register.
  761. */
  762. #define DAC960_LA_IDB_HWMBOX_NEW_CMD 0x01
  763. #define DAC960_LA_IDB_HWMBOX_ACK_STS 0x02
  764. #define DAC960_LA_IDB_GEN_IRQ 0x04
  765. #define DAC960_LA_IDB_CTRL_RESET 0x08
  766. #define DAC960_LA_IDB_MMBOX_NEW_CMD 0x10
  767. #define DAC960_LA_IDB_HWMBOX_EMPTY 0x01
  768. #define DAC960_LA_IDB_INIT_DONE 0x02
  769. /*
  770. * DAC960 LA Series Outbound Door Bell Register.
  771. */
  772. #define DAC960_LA_ODB_HWMBOX_ACK_IRQ 0x01
  773. #define DAC960_LA_ODB_MMBOX_ACK_IRQ 0x02
  774. #define DAC960_LA_ODB_HWMBOX_STS_AVAIL 0x01
  775. #define DAC960_LA_ODB_MMBOX_STS_AVAIL 0x02
  776. /*
  777. * DAC960 LA Series Interrupt Mask Register.
  778. */
  779. #define DAC960_LA_IRQMASK_DISABLE_IRQ 0x04
  780. /*
  781. * DAC960 LA Series Error Status Register.
  782. */
  783. #define DAC960_LA_ERRSTS_PENDING 0x02
  784. /*
  785. * DAC960 PG Series Controller Interface Register Offsets.
  786. */
  787. #define DAC960_PG_mmio_size 0x2000
  788. enum DAC960_PG_reg_offset {
  789. DAC960_PG_IDB_OFFSET = 0x0020,
  790. DAC960_PG_ODB_OFFSET = 0x002C,
  791. DAC960_PG_IRQMASK_OFFSET = 0x0034,
  792. DAC960_PG_CMDOP_OFFSET = 0x1000,
  793. DAC960_PG_CMDID_OFFSET = 0x1001,
  794. DAC960_PG_MBOX2_OFFSET = 0x1002,
  795. DAC960_PG_MBOX3_OFFSET = 0x1003,
  796. DAC960_PG_MBOX4_OFFSET = 0x1004,
  797. DAC960_PG_MBOX5_OFFSET = 0x1005,
  798. DAC960_PG_MBOX6_OFFSET = 0x1006,
  799. DAC960_PG_MBOX7_OFFSET = 0x1007,
  800. DAC960_PG_MBOX8_OFFSET = 0x1008,
  801. DAC960_PG_MBOX9_OFFSET = 0x1009,
  802. DAC960_PG_MBOX10_OFFSET = 0x100A,
  803. DAC960_PG_MBOX11_OFFSET = 0x100B,
  804. DAC960_PG_MBOX12_OFFSET = 0x100C,
  805. DAC960_PG_STSID_OFFSET = 0x1018,
  806. DAC960_PG_STS_OFFSET = 0x101A,
  807. DAC960_PG_ERRSTS_OFFSET = 0x103F,
  808. };
  809. /*
  810. * DAC960 PG Series Inbound Door Bell Register.
  811. */
  812. #define DAC960_PG_IDB_HWMBOX_NEW_CMD 0x01
  813. #define DAC960_PG_IDB_HWMBOX_ACK_STS 0x02
  814. #define DAC960_PG_IDB_GEN_IRQ 0x04
  815. #define DAC960_PG_IDB_CTRL_RESET 0x08
  816. #define DAC960_PG_IDB_MMBOX_NEW_CMD 0x10
  817. #define DAC960_PG_IDB_HWMBOX_FULL 0x01
  818. #define DAC960_PG_IDB_INIT_IN_PROGRESS 0x02
  819. /*
  820. * DAC960 PG Series Outbound Door Bell Register.
  821. */
  822. #define DAC960_PG_ODB_HWMBOX_ACK_IRQ 0x01
  823. #define DAC960_PG_ODB_MMBOX_ACK_IRQ 0x02
  824. #define DAC960_PG_ODB_HWMBOX_STS_AVAIL 0x01
  825. #define DAC960_PG_ODB_MMBOX_STS_AVAIL 0x02
  826. /*
  827. * DAC960 PG Series Interrupt Mask Register.
  828. */
  829. #define DAC960_PG_IRQMASK_MSI_MASK1 0x03
  830. #define DAC960_PG_IRQMASK_DISABLE_IRQ 0x04
  831. #define DAC960_PG_IRQMASK_MSI_MASK2 0xF8
  832. /*
  833. * DAC960 PG Series Error Status Register.
  834. */
  835. #define DAC960_PG_ERRSTS_PENDING 0x04
  836. /*
  837. * DAC960 PD Series Controller Interface Register Offsets.
  838. */
  839. #define DAC960_PD_mmio_size 0x80
  840. enum DAC960_PD_reg_offset {
  841. DAC960_PD_CMDOP_OFFSET = 0x00,
  842. DAC960_PD_CMDID_OFFSET = 0x01,
  843. DAC960_PD_MBOX2_OFFSET = 0x02,
  844. DAC960_PD_MBOX3_OFFSET = 0x03,
  845. DAC960_PD_MBOX4_OFFSET = 0x04,
  846. DAC960_PD_MBOX5_OFFSET = 0x05,
  847. DAC960_PD_MBOX6_OFFSET = 0x06,
  848. DAC960_PD_MBOX7_OFFSET = 0x07,
  849. DAC960_PD_MBOX8_OFFSET = 0x08,
  850. DAC960_PD_MBOX9_OFFSET = 0x09,
  851. DAC960_PD_MBOX10_OFFSET = 0x0A,
  852. DAC960_PD_MBOX11_OFFSET = 0x0B,
  853. DAC960_PD_MBOX12_OFFSET = 0x0C,
  854. DAC960_PD_STSID_OFFSET = 0x0D,
  855. DAC960_PD_STS_OFFSET = 0x0E,
  856. DAC960_PD_ERRSTS_OFFSET = 0x3F,
  857. DAC960_PD_IDB_OFFSET = 0x40,
  858. DAC960_PD_ODB_OFFSET = 0x41,
  859. DAC960_PD_IRQEN_OFFSET = 0x43,
  860. };
  861. /*
  862. * DAC960 PD Series Inbound Door Bell Register.
  863. */
  864. #define DAC960_PD_IDB_HWMBOX_NEW_CMD 0x01
  865. #define DAC960_PD_IDB_HWMBOX_ACK_STS 0x02
  866. #define DAC960_PD_IDB_GEN_IRQ 0x04
  867. #define DAC960_PD_IDB_CTRL_RESET 0x08
  868. #define DAC960_PD_IDB_HWMBOX_FULL 0x01
  869. #define DAC960_PD_IDB_INIT_IN_PROGRESS 0x02
  870. /*
  871. * DAC960 PD Series Outbound Door Bell Register.
  872. */
  873. #define DAC960_PD_ODB_HWMBOX_ACK_IRQ 0x01
  874. #define DAC960_PD_ODB_HWMBOX_STS_AVAIL 0x01
  875. /*
  876. * DAC960 PD Series Interrupt Enable Register.
  877. */
  878. #define DAC960_PD_IRQMASK_ENABLE_IRQ 0x01
  879. /*
  880. * DAC960 PD Series Error Status Register.
  881. */
  882. #define DAC960_PD_ERRSTS_PENDING 0x04
  883. typedef int (*myrb_hw_init_t)(struct pci_dev *pdev,
  884. struct myrb_hba *cb, void __iomem *base);
  885. typedef unsigned short (*mbox_mmio_init_t)(struct pci_dev *pdev,
  886. void __iomem *base,
  887. union myrb_cmd_mbox *mbox);
  888. struct myrb_privdata {
  889. myrb_hw_init_t hw_init;
  890. irq_handler_t irq_handler;
  891. unsigned int mmio_size;
  892. };
  893. #endif /* MYRB_H */