mesh.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * mesh.h: definitions for the driver for the MESH SCSI bus adaptor
  4. * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
  5. *
  6. * Copyright (C) 1996 Paul Mackerras.
  7. */
  8. #ifndef _MESH_H
  9. #define _MESH_H
  10. /*
  11. * Registers in the MESH controller.
  12. */
  13. struct mesh_regs {
  14. unsigned char count_lo;
  15. char pad0[15];
  16. unsigned char count_hi;
  17. char pad1[15];
  18. unsigned char fifo;
  19. char pad2[15];
  20. unsigned char sequence;
  21. char pad3[15];
  22. unsigned char bus_status0;
  23. char pad4[15];
  24. unsigned char bus_status1;
  25. char pad5[15];
  26. unsigned char fifo_count;
  27. char pad6[15];
  28. unsigned char exception;
  29. char pad7[15];
  30. unsigned char error;
  31. char pad8[15];
  32. unsigned char intr_mask;
  33. char pad9[15];
  34. unsigned char interrupt;
  35. char pad10[15];
  36. unsigned char source_id;
  37. char pad11[15];
  38. unsigned char dest_id;
  39. char pad12[15];
  40. unsigned char sync_params;
  41. char pad13[15];
  42. unsigned char mesh_id;
  43. char pad14[15];
  44. unsigned char sel_timeout;
  45. char pad15[15];
  46. };
  47. /* Bits in the sequence register. */
  48. #define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */
  49. #define SEQ_TARGET 0x40 /* put the controller into target mode */
  50. #define SEQ_ATN 0x20 /* assert ATN signal */
  51. #define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */
  52. #define SEQ_CMD 0x0f /* command bits: */
  53. #define SEQ_ARBITRATE 1 /* get the bus */
  54. #define SEQ_SELECT 2 /* select a target */
  55. #define SEQ_COMMAND 3 /* send a command */
  56. #define SEQ_STATUS 4 /* receive status */
  57. #define SEQ_DATAOUT 5 /* send data */
  58. #define SEQ_DATAIN 6 /* receive data */
  59. #define SEQ_MSGOUT 7 /* send a message */
  60. #define SEQ_MSGIN 8 /* receive a message */
  61. #define SEQ_BUSFREE 9 /* look for bus free */
  62. #define SEQ_ENBPARITY 0x0a /* enable parity checking */
  63. #define SEQ_DISPARITY 0x0b /* disable parity checking */
  64. #define SEQ_ENBRESEL 0x0c /* enable reselection */
  65. #define SEQ_DISRESEL 0x0d /* disable reselection */
  66. #define SEQ_RESETMESH 0x0e /* reset the controller */
  67. #define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */
  68. /* Bits in the bus_status0 and bus_status1 registers:
  69. these correspond directly to the SCSI bus control signals. */
  70. #define BS0_REQ 0x20
  71. #define BS0_ACK 0x10
  72. #define BS0_ATN 0x08
  73. #define BS0_MSG 0x04
  74. #define BS0_CD 0x02
  75. #define BS0_IO 0x01
  76. #define BS1_RST 0x80
  77. #define BS1_BSY 0x40
  78. #define BS1_SEL 0x20
  79. /* Bus phases defined by the bits in bus_status0 */
  80. #define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO)
  81. #define BP_DATAOUT 0
  82. #define BP_DATAIN BS0_IO
  83. #define BP_COMMAND BS0_CD
  84. #define BP_STATUS (BS0_CD+BS0_IO)
  85. #define BP_MSGOUT (BS0_MSG+BS0_CD)
  86. #define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO)
  87. /* Bits in the exception register. */
  88. #define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */
  89. #define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */
  90. #define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */
  91. #define EXC_ARBLOST 0x04 /* we lost arbitration */
  92. #define EXC_PHASEMM 0x02 /* SCSI phase mismatch */
  93. #define EXC_SELTO 0x01 /* selection timeout */
  94. /* Bits in the error register */
  95. #define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */
  96. #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
  97. #define ERR_SEQERR 0x10 /* we did something the chip didn't like */
  98. #define ERR_PARITY 0x01 /* parity error was detected */
  99. /* Bits in the interrupt and intr_mask registers */
  100. #define INT_ERROR 0x04 /* error interrupt */
  101. #define INT_EXCEPTION 0x02 /* exception interrupt */
  102. #define INT_CMDDONE 0x01 /* command done interrupt */
  103. /* Fields in the sync_params register */
  104. #define SYNC_OFF(x) ((x) >> 4) /* offset field */
  105. #define SYNC_PER(x) ((x) & 0xf) /* period field */
  106. #define SYNC_PARAMS(o, p) (((o) << 4) | (p))
  107. #define ASYNC_PARAMS 2 /* sync_params value for async xfers */
  108. /*
  109. * Assuming a clock frequency of 50MHz:
  110. *
  111. * The transfer period with SYNC_PER(sync_params) == x
  112. * is (x + 2) * 40ns, except that x == 0 gives 100ns.
  113. *
  114. * The units of the sel_timeout register are 10ms.
  115. */
  116. #endif /* _MESH_H */