mesh.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
  4. * bus adaptor found on Power Macintosh computers.
  5. * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
  6. * controller.
  7. *
  8. * Paul Mackerras, August 1996.
  9. * Copyright (C) 1996 Paul Mackerras.
  10. *
  11. * Apr. 21 2002 - BenH Rework bus reset code for new error handler
  12. * Add delay after initial bus reset
  13. * Add module parameters
  14. *
  15. * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
  16. * issues
  17. * To do:
  18. * - handle aborts correctly
  19. * - retry arbitration if lost (unless higher levels do this for us)
  20. * - power down the chip when no device is detected
  21. */
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/types.h>
  26. #include <linux/string.h>
  27. #include <linux/blkdev.h>
  28. #include <linux/proc_fs.h>
  29. #include <linux/stat.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/reboot.h>
  32. #include <linux/spinlock.h>
  33. #include <linux/pci.h>
  34. #include <linux/pgtable.h>
  35. #include <asm/dbdma.h>
  36. #include <asm/io.h>
  37. #include <asm/prom.h>
  38. #include <asm/irq.h>
  39. #include <asm/hydra.h>
  40. #include <asm/processor.h>
  41. #include <asm/machdep.h>
  42. #include <asm/pmac_feature.h>
  43. #include <asm/macio.h>
  44. #include <scsi/scsi.h>
  45. #include <scsi/scsi_cmnd.h>
  46. #include <scsi/scsi_device.h>
  47. #include <scsi/scsi_host.h>
  48. #include "mesh.h"
  49. #if 1
  50. #undef KERN_DEBUG
  51. #define KERN_DEBUG KERN_WARNING
  52. #endif
  53. MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
  54. MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
  55. MODULE_LICENSE("GPL");
  56. static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
  57. static int sync_targets = 0xff;
  58. static int resel_targets = 0xff;
  59. static int debug_targets = 0; /* print debug for these targets */
  60. static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
  61. module_param(sync_rate, int, 0);
  62. MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
  63. module_param(sync_targets, int, 0);
  64. MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
  65. module_param(resel_targets, int, 0);
  66. MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
  67. module_param(debug_targets, int, 0644);
  68. MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
  69. module_param(init_reset_delay, int, 0);
  70. MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
  71. static int mesh_sync_period = 100;
  72. static int mesh_sync_offset = 0;
  73. static unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
  74. #define ALLOW_SYNC(tgt) ((sync_targets >> (tgt)) & 1)
  75. #define ALLOW_RESEL(tgt) ((resel_targets >> (tgt)) & 1)
  76. #define ALLOW_DEBUG(tgt) ((debug_targets >> (tgt)) & 1)
  77. #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
  78. #undef MESH_DBG
  79. #define N_DBG_LOG 50
  80. #define N_DBG_SLOG 20
  81. #define NUM_DBG_EVENTS 13
  82. #undef DBG_USE_TB /* bombs on 601 */
  83. struct dbglog {
  84. char *fmt;
  85. u32 tb;
  86. u8 phase;
  87. u8 bs0;
  88. u8 bs1;
  89. u8 tgt;
  90. int d;
  91. };
  92. enum mesh_phase {
  93. idle,
  94. arbitrating,
  95. selecting,
  96. commanding,
  97. dataing,
  98. statusing,
  99. busfreeing,
  100. disconnecting,
  101. reselecting,
  102. sleeping
  103. };
  104. enum msg_phase {
  105. msg_none,
  106. msg_out,
  107. msg_out_xxx,
  108. msg_out_last,
  109. msg_in,
  110. msg_in_bad,
  111. };
  112. enum sdtr_phase {
  113. do_sdtr,
  114. sdtr_sent,
  115. sdtr_done
  116. };
  117. struct mesh_target {
  118. enum sdtr_phase sdtr_state;
  119. int sync_params;
  120. int data_goes_out; /* guess as to data direction */
  121. struct scsi_cmnd *current_req;
  122. u32 saved_ptr;
  123. #ifdef MESH_DBG
  124. int log_ix;
  125. int n_log;
  126. struct dbglog log[N_DBG_LOG];
  127. #endif
  128. };
  129. struct mesh_state {
  130. volatile struct mesh_regs __iomem *mesh;
  131. int meshintr;
  132. volatile struct dbdma_regs __iomem *dma;
  133. int dmaintr;
  134. struct Scsi_Host *host;
  135. struct mesh_state *next;
  136. struct scsi_cmnd *request_q;
  137. struct scsi_cmnd *request_qtail;
  138. enum mesh_phase phase; /* what we're currently trying to do */
  139. enum msg_phase msgphase;
  140. int conn_tgt; /* target we're connected to */
  141. struct scsi_cmnd *current_req; /* req we're currently working on */
  142. int data_ptr;
  143. int dma_started;
  144. int dma_count;
  145. int stat;
  146. int aborting;
  147. int expect_reply;
  148. int n_msgin;
  149. u8 msgin[16];
  150. int n_msgout;
  151. int last_n_msgout;
  152. u8 msgout[16];
  153. struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
  154. dma_addr_t dma_cmd_bus;
  155. void *dma_cmd_space;
  156. int dma_cmd_size;
  157. int clk_freq;
  158. struct mesh_target tgts[8];
  159. struct macio_dev *mdev;
  160. struct pci_dev* pdev;
  161. #ifdef MESH_DBG
  162. int log_ix;
  163. int n_log;
  164. struct dbglog log[N_DBG_SLOG];
  165. #endif
  166. };
  167. /*
  168. * Driver is too messy, we need a few prototypes...
  169. */
  170. static void mesh_done(struct mesh_state *ms, int start_next);
  171. static void mesh_interrupt(struct mesh_state *ms);
  172. static void cmd_complete(struct mesh_state *ms);
  173. static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
  174. static void halt_dma(struct mesh_state *ms);
  175. static void phase_mismatch(struct mesh_state *ms);
  176. /*
  177. * Some debugging & logging routines
  178. */
  179. #ifdef MESH_DBG
  180. static inline u32 readtb(void)
  181. {
  182. u32 tb;
  183. #ifdef DBG_USE_TB
  184. /* Beware: if you enable this, it will crash on 601s. */
  185. asm ("mftb %0" : "=r" (tb) : );
  186. #else
  187. tb = 0;
  188. #endif
  189. return tb;
  190. }
  191. static void dlog(struct mesh_state *ms, char *fmt, int a)
  192. {
  193. struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
  194. struct dbglog *tlp, *slp;
  195. tlp = &tp->log[tp->log_ix];
  196. slp = &ms->log[ms->log_ix];
  197. tlp->fmt = fmt;
  198. tlp->tb = readtb();
  199. tlp->phase = (ms->msgphase << 4) + ms->phase;
  200. tlp->bs0 = ms->mesh->bus_status0;
  201. tlp->bs1 = ms->mesh->bus_status1;
  202. tlp->tgt = ms->conn_tgt;
  203. tlp->d = a;
  204. *slp = *tlp;
  205. if (++tp->log_ix >= N_DBG_LOG)
  206. tp->log_ix = 0;
  207. if (tp->n_log < N_DBG_LOG)
  208. ++tp->n_log;
  209. if (++ms->log_ix >= N_DBG_SLOG)
  210. ms->log_ix = 0;
  211. if (ms->n_log < N_DBG_SLOG)
  212. ++ms->n_log;
  213. }
  214. static void dumplog(struct mesh_state *ms, int t)
  215. {
  216. struct mesh_target *tp = &ms->tgts[t];
  217. struct dbglog *lp;
  218. int i;
  219. if (tp->n_log == 0)
  220. return;
  221. i = tp->log_ix - tp->n_log;
  222. if (i < 0)
  223. i += N_DBG_LOG;
  224. tp->n_log = 0;
  225. do {
  226. lp = &tp->log[i];
  227. printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
  228. t, lp->bs1, lp->bs0, lp->phase);
  229. #ifdef DBG_USE_TB
  230. printk("tb=%10u ", lp->tb);
  231. #endif
  232. printk(lp->fmt, lp->d);
  233. printk("\n");
  234. if (++i >= N_DBG_LOG)
  235. i = 0;
  236. } while (i != tp->log_ix);
  237. }
  238. static void dumpslog(struct mesh_state *ms)
  239. {
  240. struct dbglog *lp;
  241. int i;
  242. if (ms->n_log == 0)
  243. return;
  244. i = ms->log_ix - ms->n_log;
  245. if (i < 0)
  246. i += N_DBG_SLOG;
  247. ms->n_log = 0;
  248. do {
  249. lp = &ms->log[i];
  250. printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
  251. lp->bs1, lp->bs0, lp->phase, lp->tgt);
  252. #ifdef DBG_USE_TB
  253. printk("tb=%10u ", lp->tb);
  254. #endif
  255. printk(lp->fmt, lp->d);
  256. printk("\n");
  257. if (++i >= N_DBG_SLOG)
  258. i = 0;
  259. } while (i != ms->log_ix);
  260. }
  261. #else
  262. static inline void dlog(struct mesh_state *ms, char *fmt, int a)
  263. {}
  264. static inline void dumplog(struct mesh_state *ms, int tgt)
  265. {}
  266. static inline void dumpslog(struct mesh_state *ms)
  267. {}
  268. #endif /* MESH_DBG */
  269. #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
  270. static void
  271. mesh_dump_regs(struct mesh_state *ms)
  272. {
  273. volatile struct mesh_regs __iomem *mr = ms->mesh;
  274. volatile struct dbdma_regs __iomem *md = ms->dma;
  275. int t;
  276. struct mesh_target *tp;
  277. printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
  278. ms, mr, md);
  279. printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
  280. "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
  281. (mr->count_hi << 8) + mr->count_lo, mr->sequence,
  282. (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
  283. mr->exception, mr->error, mr->intr_mask, mr->interrupt,
  284. mr->sync_params);
  285. while(in_8(&mr->fifo_count))
  286. printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
  287. printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
  288. in_le32(&md->status), in_le32(&md->cmdptr));
  289. printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
  290. ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
  291. printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
  292. ms->dma_started, ms->dma_count, ms->n_msgout);
  293. for (t = 0; t < 8; ++t) {
  294. tp = &ms->tgts[t];
  295. if (tp->current_req == NULL)
  296. continue;
  297. printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
  298. t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
  299. }
  300. }
  301. /*
  302. * Flush write buffers on the bus path to the mesh
  303. */
  304. static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
  305. {
  306. (void)in_8(&mr->mesh_id);
  307. }
  308. /*
  309. * Complete a SCSI command
  310. */
  311. static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
  312. {
  313. (*cmd->scsi_done)(cmd);
  314. }
  315. /* Called with meshinterrupt disabled, initialize the chipset
  316. * and eventually do the initial bus reset. The lock must not be
  317. * held since we can schedule.
  318. */
  319. static void mesh_init(struct mesh_state *ms)
  320. {
  321. volatile struct mesh_regs __iomem *mr = ms->mesh;
  322. volatile struct dbdma_regs __iomem *md = ms->dma;
  323. mesh_flush_io(mr);
  324. udelay(100);
  325. /* Reset controller */
  326. out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
  327. out_8(&mr->exception, 0xff); /* clear all exception bits */
  328. out_8(&mr->error, 0xff); /* clear all error bits */
  329. out_8(&mr->sequence, SEQ_RESETMESH);
  330. mesh_flush_io(mr);
  331. udelay(10);
  332. out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  333. out_8(&mr->source_id, ms->host->this_id);
  334. out_8(&mr->sel_timeout, 25); /* 250ms */
  335. out_8(&mr->sync_params, ASYNC_PARAMS);
  336. if (init_reset_delay) {
  337. printk(KERN_INFO "mesh: performing initial bus reset...\n");
  338. /* Reset bus */
  339. out_8(&mr->bus_status1, BS1_RST); /* assert RST */
  340. mesh_flush_io(mr);
  341. udelay(30); /* leave it on for >= 25us */
  342. out_8(&mr->bus_status1, 0); /* negate RST */
  343. mesh_flush_io(mr);
  344. /* Wait for bus to come back */
  345. msleep(init_reset_delay);
  346. }
  347. /* Reconfigure controller */
  348. out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
  349. out_8(&mr->sequence, SEQ_FLUSHFIFO);
  350. mesh_flush_io(mr);
  351. udelay(1);
  352. out_8(&mr->sync_params, ASYNC_PARAMS);
  353. out_8(&mr->sequence, SEQ_ENBRESEL);
  354. ms->phase = idle;
  355. ms->msgphase = msg_none;
  356. }
  357. static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
  358. {
  359. volatile struct mesh_regs __iomem *mr = ms->mesh;
  360. int t, id;
  361. id = cmd->device->id;
  362. ms->current_req = cmd;
  363. ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
  364. ms->tgts[id].current_req = cmd;
  365. #if 1
  366. if (DEBUG_TARGET(cmd)) {
  367. int i;
  368. printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
  369. for (i = 0; i < cmd->cmd_len; ++i)
  370. printk(" %x", cmd->cmnd[i]);
  371. printk(" use_sg=%d buffer=%p bufflen=%u\n",
  372. scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
  373. }
  374. #endif
  375. if (ms->dma_started)
  376. panic("mesh: double DMA start !\n");
  377. ms->phase = arbitrating;
  378. ms->msgphase = msg_none;
  379. ms->data_ptr = 0;
  380. ms->dma_started = 0;
  381. ms->n_msgout = 0;
  382. ms->last_n_msgout = 0;
  383. ms->expect_reply = 0;
  384. ms->conn_tgt = id;
  385. ms->tgts[id].saved_ptr = 0;
  386. ms->stat = DID_OK;
  387. ms->aborting = 0;
  388. #ifdef MESH_DBG
  389. ms->tgts[id].n_log = 0;
  390. dlog(ms, "start cmd=%x", (int) cmd);
  391. #endif
  392. /* Off we go */
  393. dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
  394. MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
  395. out_8(&mr->interrupt, INT_CMDDONE);
  396. out_8(&mr->sequence, SEQ_ENBRESEL);
  397. mesh_flush_io(mr);
  398. udelay(1);
  399. if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
  400. /*
  401. * Some other device has the bus or is arbitrating for it -
  402. * probably a target which is about to reselect us.
  403. */
  404. dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
  405. MKWORD(mr->interrupt, mr->exception,
  406. mr->error, mr->fifo_count));
  407. for (t = 100; t > 0; --t) {
  408. if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
  409. break;
  410. if (in_8(&mr->interrupt) != 0) {
  411. dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
  412. MKWORD(mr->interrupt, mr->exception,
  413. mr->error, mr->fifo_count));
  414. mesh_interrupt(ms);
  415. if (ms->phase != arbitrating)
  416. return;
  417. }
  418. udelay(1);
  419. }
  420. if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
  421. /* XXX should try again in a little while */
  422. ms->stat = DID_BUS_BUSY;
  423. ms->phase = idle;
  424. mesh_done(ms, 0);
  425. return;
  426. }
  427. }
  428. /*
  429. * Apparently the mesh has a bug where it will assert both its
  430. * own bit and the target's bit on the bus during arbitration.
  431. */
  432. out_8(&mr->dest_id, mr->source_id);
  433. /*
  434. * There appears to be a race with reselection sometimes,
  435. * where a target reselects us just as we issue the
  436. * arbitrate command. It seems that then the arbitrate
  437. * command just hangs waiting for the bus to be free
  438. * without giving us a reselection exception.
  439. * The only way I have found to get it to respond correctly
  440. * is this: disable reselection before issuing the arbitrate
  441. * command, then after issuing it, if it looks like a target
  442. * is trying to reselect us, reset the mesh and then enable
  443. * reselection.
  444. */
  445. out_8(&mr->sequence, SEQ_DISRESEL);
  446. if (in_8(&mr->interrupt) != 0) {
  447. dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
  448. MKWORD(mr->interrupt, mr->exception,
  449. mr->error, mr->fifo_count));
  450. mesh_interrupt(ms);
  451. if (ms->phase != arbitrating)
  452. return;
  453. dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
  454. MKWORD(mr->interrupt, mr->exception,
  455. mr->error, mr->fifo_count));
  456. }
  457. out_8(&mr->sequence, SEQ_ARBITRATE);
  458. for (t = 230; t > 0; --t) {
  459. if (in_8(&mr->interrupt) != 0)
  460. break;
  461. udelay(1);
  462. }
  463. dlog(ms, "after arb, intr/exc/err/fc=%.8x",
  464. MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
  465. if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
  466. && (in_8(&mr->bus_status0) & BS0_IO)) {
  467. /* looks like a reselection - try resetting the mesh */
  468. dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
  469. MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
  470. out_8(&mr->sequence, SEQ_RESETMESH);
  471. mesh_flush_io(mr);
  472. udelay(10);
  473. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  474. out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  475. out_8(&mr->sequence, SEQ_ENBRESEL);
  476. mesh_flush_io(mr);
  477. for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
  478. udelay(1);
  479. dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
  480. MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
  481. #ifndef MESH_MULTIPLE_HOSTS
  482. if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
  483. && (in_8(&mr->bus_status0) & BS0_IO)) {
  484. printk(KERN_ERR "mesh: controller not responding"
  485. " to reselection!\n");
  486. /*
  487. * If this is a target reselecting us, and the
  488. * mesh isn't responding, the higher levels of
  489. * the scsi code will eventually time out and
  490. * reset the bus.
  491. */
  492. }
  493. #endif
  494. }
  495. }
  496. /*
  497. * Start the next command for a MESH.
  498. * Should be called with interrupts disabled.
  499. */
  500. static void mesh_start(struct mesh_state *ms)
  501. {
  502. struct scsi_cmnd *cmd, *prev, *next;
  503. if (ms->phase != idle || ms->current_req != NULL) {
  504. printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
  505. ms->phase, ms);
  506. return;
  507. }
  508. while (ms->phase == idle) {
  509. prev = NULL;
  510. for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
  511. if (cmd == NULL)
  512. return;
  513. if (ms->tgts[cmd->device->id].current_req == NULL)
  514. break;
  515. prev = cmd;
  516. }
  517. next = (struct scsi_cmnd *) cmd->host_scribble;
  518. if (prev == NULL)
  519. ms->request_q = next;
  520. else
  521. prev->host_scribble = (void *) next;
  522. if (next == NULL)
  523. ms->request_qtail = prev;
  524. mesh_start_cmd(ms, cmd);
  525. }
  526. }
  527. static void mesh_done(struct mesh_state *ms, int start_next)
  528. {
  529. struct scsi_cmnd *cmd;
  530. struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
  531. cmd = ms->current_req;
  532. ms->current_req = NULL;
  533. tp->current_req = NULL;
  534. if (cmd) {
  535. cmd->result = (ms->stat << 16) | cmd->SCp.Status;
  536. if (ms->stat == DID_OK)
  537. cmd->result |= cmd->SCp.Message << 8;
  538. if (DEBUG_TARGET(cmd)) {
  539. printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
  540. cmd->result, ms->data_ptr, scsi_bufflen(cmd));
  541. #if 0
  542. /* needs to use sg? */
  543. if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
  544. && cmd->request_buffer != 0) {
  545. unsigned char *b = cmd->request_buffer;
  546. printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
  547. b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
  548. }
  549. #endif
  550. }
  551. cmd->SCp.this_residual -= ms->data_ptr;
  552. mesh_completed(ms, cmd);
  553. }
  554. if (start_next) {
  555. out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
  556. mesh_flush_io(ms->mesh);
  557. udelay(1);
  558. ms->phase = idle;
  559. mesh_start(ms);
  560. }
  561. }
  562. static inline void add_sdtr_msg(struct mesh_state *ms)
  563. {
  564. int i = ms->n_msgout;
  565. ms->msgout[i] = EXTENDED_MESSAGE;
  566. ms->msgout[i+1] = 3;
  567. ms->msgout[i+2] = EXTENDED_SDTR;
  568. ms->msgout[i+3] = mesh_sync_period/4;
  569. ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
  570. ms->n_msgout = i + 5;
  571. }
  572. static void set_sdtr(struct mesh_state *ms, int period, int offset)
  573. {
  574. struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
  575. volatile struct mesh_regs __iomem *mr = ms->mesh;
  576. int v, tr;
  577. tp->sdtr_state = sdtr_done;
  578. if (offset == 0) {
  579. /* asynchronous */
  580. if (SYNC_OFF(tp->sync_params))
  581. printk(KERN_INFO "mesh: target %d now asynchronous\n",
  582. ms->conn_tgt);
  583. tp->sync_params = ASYNC_PARAMS;
  584. out_8(&mr->sync_params, ASYNC_PARAMS);
  585. return;
  586. }
  587. /*
  588. * We need to compute ceil(clk_freq * period / 500e6) - 2
  589. * without incurring overflow.
  590. */
  591. v = (ms->clk_freq / 5000) * period;
  592. if (v <= 250000) {
  593. /* special case: sync_period == 5 * clk_period */
  594. v = 0;
  595. /* units of tr are 100kB/s */
  596. tr = (ms->clk_freq + 250000) / 500000;
  597. } else {
  598. /* sync_period == (v + 2) * 2 * clk_period */
  599. v = (v + 99999) / 100000 - 2;
  600. if (v > 15)
  601. v = 15; /* oops */
  602. tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
  603. }
  604. if (offset > 15)
  605. offset = 15; /* can't happen */
  606. tp->sync_params = SYNC_PARAMS(offset, v);
  607. out_8(&mr->sync_params, tp->sync_params);
  608. printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
  609. ms->conn_tgt, tr/10, tr%10);
  610. }
  611. static void start_phase(struct mesh_state *ms)
  612. {
  613. int i, seq, nb;
  614. volatile struct mesh_regs __iomem *mr = ms->mesh;
  615. volatile struct dbdma_regs __iomem *md = ms->dma;
  616. struct scsi_cmnd *cmd = ms->current_req;
  617. struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
  618. dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
  619. MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
  620. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  621. seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
  622. switch (ms->msgphase) {
  623. case msg_none:
  624. break;
  625. case msg_in:
  626. out_8(&mr->count_hi, 0);
  627. out_8(&mr->count_lo, 1);
  628. out_8(&mr->sequence, SEQ_MSGIN + seq);
  629. ms->n_msgin = 0;
  630. return;
  631. case msg_out:
  632. /*
  633. * To make sure ATN drops before we assert ACK for
  634. * the last byte of the message, we have to do the
  635. * last byte specially.
  636. */
  637. if (ms->n_msgout <= 0) {
  638. printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
  639. ms->n_msgout);
  640. mesh_dump_regs(ms);
  641. ms->msgphase = msg_none;
  642. break;
  643. }
  644. if (ALLOW_DEBUG(ms->conn_tgt)) {
  645. printk(KERN_DEBUG "mesh: sending %d msg bytes:",
  646. ms->n_msgout);
  647. for (i = 0; i < ms->n_msgout; ++i)
  648. printk(" %x", ms->msgout[i]);
  649. printk("\n");
  650. }
  651. dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
  652. ms->msgout[1], ms->msgout[2]));
  653. out_8(&mr->count_hi, 0);
  654. out_8(&mr->sequence, SEQ_FLUSHFIFO);
  655. mesh_flush_io(mr);
  656. udelay(1);
  657. /*
  658. * If ATN is not already asserted, we assert it, then
  659. * issue a SEQ_MSGOUT to get the mesh to drop ACK.
  660. */
  661. if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
  662. dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
  663. out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
  664. mesh_flush_io(mr);
  665. udelay(1);
  666. out_8(&mr->count_lo, 1);
  667. out_8(&mr->sequence, SEQ_MSGOUT + seq);
  668. out_8(&mr->bus_status0, 0); /* release explicit ATN */
  669. dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
  670. }
  671. if (ms->n_msgout == 1) {
  672. /*
  673. * We can't issue the SEQ_MSGOUT without ATN
  674. * until the target has asserted REQ. The logic
  675. * in cmd_complete handles both situations:
  676. * REQ already asserted or not.
  677. */
  678. cmd_complete(ms);
  679. } else {
  680. out_8(&mr->count_lo, ms->n_msgout - 1);
  681. out_8(&mr->sequence, SEQ_MSGOUT + seq);
  682. for (i = 0; i < ms->n_msgout - 1; ++i)
  683. out_8(&mr->fifo, ms->msgout[i]);
  684. }
  685. return;
  686. default:
  687. printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
  688. ms->msgphase);
  689. }
  690. switch (ms->phase) {
  691. case selecting:
  692. out_8(&mr->dest_id, ms->conn_tgt);
  693. out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
  694. break;
  695. case commanding:
  696. out_8(&mr->sync_params, tp->sync_params);
  697. out_8(&mr->count_hi, 0);
  698. if (cmd) {
  699. out_8(&mr->count_lo, cmd->cmd_len);
  700. out_8(&mr->sequence, SEQ_COMMAND + seq);
  701. for (i = 0; i < cmd->cmd_len; ++i)
  702. out_8(&mr->fifo, cmd->cmnd[i]);
  703. } else {
  704. out_8(&mr->count_lo, 6);
  705. out_8(&mr->sequence, SEQ_COMMAND + seq);
  706. for (i = 0; i < 6; ++i)
  707. out_8(&mr->fifo, 0);
  708. }
  709. break;
  710. case dataing:
  711. /* transfer data, if any */
  712. if (!ms->dma_started) {
  713. set_dma_cmds(ms, cmd);
  714. out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
  715. out_le32(&md->control, (RUN << 16) | RUN);
  716. ms->dma_started = 1;
  717. }
  718. nb = ms->dma_count;
  719. if (nb > 0xfff0)
  720. nb = 0xfff0;
  721. ms->dma_count -= nb;
  722. ms->data_ptr += nb;
  723. out_8(&mr->count_lo, nb);
  724. out_8(&mr->count_hi, nb >> 8);
  725. out_8(&mr->sequence, (tp->data_goes_out?
  726. SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
  727. break;
  728. case statusing:
  729. out_8(&mr->count_hi, 0);
  730. out_8(&mr->count_lo, 1);
  731. out_8(&mr->sequence, SEQ_STATUS + seq);
  732. break;
  733. case busfreeing:
  734. case disconnecting:
  735. out_8(&mr->sequence, SEQ_ENBRESEL);
  736. mesh_flush_io(mr);
  737. udelay(1);
  738. dlog(ms, "enbresel intr/exc/err/fc=%.8x",
  739. MKWORD(mr->interrupt, mr->exception, mr->error,
  740. mr->fifo_count));
  741. out_8(&mr->sequence, SEQ_BUSFREE);
  742. break;
  743. default:
  744. printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
  745. ms->phase);
  746. dumpslog(ms);
  747. }
  748. }
  749. static inline void get_msgin(struct mesh_state *ms)
  750. {
  751. volatile struct mesh_regs __iomem *mr = ms->mesh;
  752. int i, n;
  753. n = mr->fifo_count;
  754. if (n != 0) {
  755. i = ms->n_msgin;
  756. ms->n_msgin = i + n;
  757. for (; n > 0; --n)
  758. ms->msgin[i++] = in_8(&mr->fifo);
  759. }
  760. }
  761. static inline int msgin_length(struct mesh_state *ms)
  762. {
  763. int b, n;
  764. n = 1;
  765. if (ms->n_msgin > 0) {
  766. b = ms->msgin[0];
  767. if (b == 1) {
  768. /* extended message */
  769. n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
  770. } else if (0x20 <= b && b <= 0x2f) {
  771. /* 2-byte message */
  772. n = 2;
  773. }
  774. }
  775. return n;
  776. }
  777. static void reselected(struct mesh_state *ms)
  778. {
  779. volatile struct mesh_regs __iomem *mr = ms->mesh;
  780. struct scsi_cmnd *cmd;
  781. struct mesh_target *tp;
  782. int b, t, prev;
  783. switch (ms->phase) {
  784. case idle:
  785. break;
  786. case arbitrating:
  787. if ((cmd = ms->current_req) != NULL) {
  788. /* put the command back on the queue */
  789. cmd->host_scribble = (void *) ms->request_q;
  790. if (ms->request_q == NULL)
  791. ms->request_qtail = cmd;
  792. ms->request_q = cmd;
  793. tp = &ms->tgts[cmd->device->id];
  794. tp->current_req = NULL;
  795. }
  796. break;
  797. case busfreeing:
  798. ms->phase = reselecting;
  799. mesh_done(ms, 0);
  800. break;
  801. case disconnecting:
  802. break;
  803. default:
  804. printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
  805. ms->msgphase, ms->phase, ms->conn_tgt);
  806. dumplog(ms, ms->conn_tgt);
  807. dumpslog(ms);
  808. }
  809. if (ms->dma_started) {
  810. printk(KERN_ERR "mesh: reselected with DMA started !\n");
  811. halt_dma(ms);
  812. }
  813. ms->current_req = NULL;
  814. ms->phase = dataing;
  815. ms->msgphase = msg_in;
  816. ms->n_msgout = 0;
  817. ms->last_n_msgout = 0;
  818. prev = ms->conn_tgt;
  819. /*
  820. * We seem to get abortive reselections sometimes.
  821. */
  822. while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
  823. static int mesh_aborted_resels;
  824. mesh_aborted_resels++;
  825. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  826. mesh_flush_io(mr);
  827. udelay(1);
  828. out_8(&mr->sequence, SEQ_ENBRESEL);
  829. mesh_flush_io(mr);
  830. udelay(5);
  831. dlog(ms, "extra resel err/exc/fc = %.6x",
  832. MKWORD(0, mr->error, mr->exception, mr->fifo_count));
  833. }
  834. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  835. mesh_flush_io(mr);
  836. udelay(1);
  837. out_8(&mr->sequence, SEQ_ENBRESEL);
  838. mesh_flush_io(mr);
  839. udelay(1);
  840. out_8(&mr->sync_params, ASYNC_PARAMS);
  841. /*
  842. * Find out who reselected us.
  843. */
  844. if (in_8(&mr->fifo_count) == 0) {
  845. printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
  846. ms->conn_tgt = ms->host->this_id;
  847. goto bogus;
  848. }
  849. /* get the last byte in the fifo */
  850. do {
  851. b = in_8(&mr->fifo);
  852. dlog(ms, "reseldata %x", b);
  853. } while (in_8(&mr->fifo_count));
  854. for (t = 0; t < 8; ++t)
  855. if ((b & (1 << t)) != 0 && t != ms->host->this_id)
  856. break;
  857. if (b != (1 << t) + (1 << ms->host->this_id)) {
  858. printk(KERN_ERR "mesh: bad reselection data %x\n", b);
  859. ms->conn_tgt = ms->host->this_id;
  860. goto bogus;
  861. }
  862. /*
  863. * Set up to continue with that target's transfer.
  864. */
  865. ms->conn_tgt = t;
  866. tp = &ms->tgts[t];
  867. out_8(&mr->sync_params, tp->sync_params);
  868. if (ALLOW_DEBUG(t)) {
  869. printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
  870. printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
  871. tp->saved_ptr, tp->data_goes_out, tp->current_req);
  872. }
  873. ms->current_req = tp->current_req;
  874. if (tp->current_req == NULL) {
  875. printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
  876. goto bogus;
  877. }
  878. ms->data_ptr = tp->saved_ptr;
  879. dlog(ms, "resel prev tgt=%d", prev);
  880. dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
  881. start_phase(ms);
  882. return;
  883. bogus:
  884. dumplog(ms, ms->conn_tgt);
  885. dumpslog(ms);
  886. ms->data_ptr = 0;
  887. ms->aborting = 1;
  888. start_phase(ms);
  889. }
  890. static void do_abort(struct mesh_state *ms)
  891. {
  892. ms->msgout[0] = ABORT;
  893. ms->n_msgout = 1;
  894. ms->aborting = 1;
  895. ms->stat = DID_ABORT;
  896. dlog(ms, "abort", 0);
  897. }
  898. static void handle_reset(struct mesh_state *ms)
  899. {
  900. int tgt;
  901. struct mesh_target *tp;
  902. struct scsi_cmnd *cmd;
  903. volatile struct mesh_regs __iomem *mr = ms->mesh;
  904. for (tgt = 0; tgt < 8; ++tgt) {
  905. tp = &ms->tgts[tgt];
  906. if ((cmd = tp->current_req) != NULL) {
  907. cmd->result = DID_RESET << 16;
  908. tp->current_req = NULL;
  909. mesh_completed(ms, cmd);
  910. }
  911. ms->tgts[tgt].sdtr_state = do_sdtr;
  912. ms->tgts[tgt].sync_params = ASYNC_PARAMS;
  913. }
  914. ms->current_req = NULL;
  915. while ((cmd = ms->request_q) != NULL) {
  916. ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
  917. cmd->result = DID_RESET << 16;
  918. mesh_completed(ms, cmd);
  919. }
  920. ms->phase = idle;
  921. ms->msgphase = msg_none;
  922. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  923. out_8(&mr->sequence, SEQ_FLUSHFIFO);
  924. mesh_flush_io(mr);
  925. udelay(1);
  926. out_8(&mr->sync_params, ASYNC_PARAMS);
  927. out_8(&mr->sequence, SEQ_ENBRESEL);
  928. }
  929. static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
  930. {
  931. unsigned long flags;
  932. struct mesh_state *ms = dev_id;
  933. struct Scsi_Host *dev = ms->host;
  934. spin_lock_irqsave(dev->host_lock, flags);
  935. mesh_interrupt(ms);
  936. spin_unlock_irqrestore(dev->host_lock, flags);
  937. return IRQ_HANDLED;
  938. }
  939. static void handle_error(struct mesh_state *ms)
  940. {
  941. int err, exc, count;
  942. volatile struct mesh_regs __iomem *mr = ms->mesh;
  943. err = in_8(&mr->error);
  944. exc = in_8(&mr->exception);
  945. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  946. dlog(ms, "error err/exc/fc/cl=%.8x",
  947. MKWORD(err, exc, mr->fifo_count, mr->count_lo));
  948. if (err & ERR_SCSIRESET) {
  949. /* SCSI bus was reset */
  950. printk(KERN_INFO "mesh: SCSI bus reset detected: "
  951. "waiting for end...");
  952. while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
  953. udelay(1);
  954. printk("done\n");
  955. if (ms->dma_started)
  956. halt_dma(ms);
  957. handle_reset(ms);
  958. /* request_q is empty, no point in mesh_start() */
  959. return;
  960. }
  961. if (err & ERR_UNEXPDISC) {
  962. /* Unexpected disconnect */
  963. if (exc & EXC_RESELECTED) {
  964. reselected(ms);
  965. return;
  966. }
  967. if (!ms->aborting) {
  968. printk(KERN_WARNING "mesh: target %d aborted\n",
  969. ms->conn_tgt);
  970. dumplog(ms, ms->conn_tgt);
  971. dumpslog(ms);
  972. }
  973. out_8(&mr->interrupt, INT_CMDDONE);
  974. ms->stat = DID_ABORT;
  975. mesh_done(ms, 1);
  976. return;
  977. }
  978. if (err & ERR_PARITY) {
  979. if (ms->msgphase == msg_in) {
  980. printk(KERN_ERR "mesh: msg parity error, target %d\n",
  981. ms->conn_tgt);
  982. ms->msgout[0] = MSG_PARITY_ERROR;
  983. ms->n_msgout = 1;
  984. ms->msgphase = msg_in_bad;
  985. cmd_complete(ms);
  986. return;
  987. }
  988. if (ms->stat == DID_OK) {
  989. printk(KERN_ERR "mesh: parity error, target %d\n",
  990. ms->conn_tgt);
  991. ms->stat = DID_PARITY;
  992. }
  993. count = (mr->count_hi << 8) + mr->count_lo;
  994. if (count == 0) {
  995. cmd_complete(ms);
  996. } else {
  997. /* reissue the data transfer command */
  998. out_8(&mr->sequence, mr->sequence);
  999. }
  1000. return;
  1001. }
  1002. if (err & ERR_SEQERR) {
  1003. if (exc & EXC_RESELECTED) {
  1004. /* This can happen if we issue a command to
  1005. get the bus just after the target reselects us. */
  1006. static int mesh_resel_seqerr;
  1007. mesh_resel_seqerr++;
  1008. reselected(ms);
  1009. return;
  1010. }
  1011. if (exc == EXC_PHASEMM) {
  1012. static int mesh_phasemm_seqerr;
  1013. mesh_phasemm_seqerr++;
  1014. phase_mismatch(ms);
  1015. return;
  1016. }
  1017. printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
  1018. err, exc);
  1019. } else {
  1020. printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
  1021. }
  1022. mesh_dump_regs(ms);
  1023. dumplog(ms, ms->conn_tgt);
  1024. if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
  1025. /* try to do what the target wants */
  1026. do_abort(ms);
  1027. phase_mismatch(ms);
  1028. return;
  1029. }
  1030. ms->stat = DID_ERROR;
  1031. mesh_done(ms, 1);
  1032. }
  1033. static void handle_exception(struct mesh_state *ms)
  1034. {
  1035. int exc;
  1036. volatile struct mesh_regs __iomem *mr = ms->mesh;
  1037. exc = in_8(&mr->exception);
  1038. out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
  1039. if (exc & EXC_RESELECTED) {
  1040. static int mesh_resel_exc;
  1041. mesh_resel_exc++;
  1042. reselected(ms);
  1043. } else if (exc == EXC_ARBLOST) {
  1044. printk(KERN_DEBUG "mesh: lost arbitration\n");
  1045. ms->stat = DID_BUS_BUSY;
  1046. mesh_done(ms, 1);
  1047. } else if (exc == EXC_SELTO) {
  1048. /* selection timed out */
  1049. ms->stat = DID_BAD_TARGET;
  1050. mesh_done(ms, 1);
  1051. } else if (exc == EXC_PHASEMM) {
  1052. /* target wants to do something different:
  1053. find out what it wants and do it. */
  1054. phase_mismatch(ms);
  1055. } else {
  1056. printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
  1057. mesh_dump_regs(ms);
  1058. dumplog(ms, ms->conn_tgt);
  1059. do_abort(ms);
  1060. phase_mismatch(ms);
  1061. }
  1062. }
  1063. static void handle_msgin(struct mesh_state *ms)
  1064. {
  1065. int i, code;
  1066. struct scsi_cmnd *cmd = ms->current_req;
  1067. struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
  1068. if (ms->n_msgin == 0)
  1069. return;
  1070. code = ms->msgin[0];
  1071. if (ALLOW_DEBUG(ms->conn_tgt)) {
  1072. printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
  1073. for (i = 0; i < ms->n_msgin; ++i)
  1074. printk(" %x", ms->msgin[i]);
  1075. printk("\n");
  1076. }
  1077. dlog(ms, "msgin msg=%.8x",
  1078. MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
  1079. ms->expect_reply = 0;
  1080. ms->n_msgout = 0;
  1081. if (ms->n_msgin < msgin_length(ms))
  1082. goto reject;
  1083. if (cmd)
  1084. cmd->SCp.Message = code;
  1085. switch (code) {
  1086. case COMMAND_COMPLETE:
  1087. break;
  1088. case EXTENDED_MESSAGE:
  1089. switch (ms->msgin[2]) {
  1090. case EXTENDED_MODIFY_DATA_POINTER:
  1091. ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
  1092. + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
  1093. break;
  1094. case EXTENDED_SDTR:
  1095. if (tp->sdtr_state != sdtr_sent) {
  1096. /* reply with an SDTR */
  1097. add_sdtr_msg(ms);
  1098. /* limit period to at least his value,
  1099. offset to no more than his */
  1100. if (ms->msgout[3] < ms->msgin[3])
  1101. ms->msgout[3] = ms->msgin[3];
  1102. if (ms->msgout[4] > ms->msgin[4])
  1103. ms->msgout[4] = ms->msgin[4];
  1104. set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
  1105. ms->msgphase = msg_out;
  1106. } else {
  1107. set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
  1108. }
  1109. break;
  1110. default:
  1111. goto reject;
  1112. }
  1113. break;
  1114. case SAVE_POINTERS:
  1115. tp->saved_ptr = ms->data_ptr;
  1116. break;
  1117. case RESTORE_POINTERS:
  1118. ms->data_ptr = tp->saved_ptr;
  1119. break;
  1120. case DISCONNECT:
  1121. ms->phase = disconnecting;
  1122. break;
  1123. case ABORT:
  1124. break;
  1125. case MESSAGE_REJECT:
  1126. if (tp->sdtr_state == sdtr_sent)
  1127. set_sdtr(ms, 0, 0);
  1128. break;
  1129. case NOP:
  1130. break;
  1131. default:
  1132. if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
  1133. if (cmd == NULL) {
  1134. do_abort(ms);
  1135. ms->msgphase = msg_out;
  1136. } else if (code != cmd->device->lun + IDENTIFY_BASE) {
  1137. printk(KERN_WARNING "mesh: lun mismatch "
  1138. "(%d != %llu) on reselection from "
  1139. "target %d\n", code - IDENTIFY_BASE,
  1140. cmd->device->lun, ms->conn_tgt);
  1141. }
  1142. break;
  1143. }
  1144. goto reject;
  1145. }
  1146. return;
  1147. reject:
  1148. printk(KERN_WARNING "mesh: rejecting message from target %d:",
  1149. ms->conn_tgt);
  1150. for (i = 0; i < ms->n_msgin; ++i)
  1151. printk(" %x", ms->msgin[i]);
  1152. printk("\n");
  1153. ms->msgout[0] = MESSAGE_REJECT;
  1154. ms->n_msgout = 1;
  1155. ms->msgphase = msg_out;
  1156. }
  1157. /*
  1158. * Set up DMA commands for transferring data.
  1159. */
  1160. static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
  1161. {
  1162. int i, dma_cmd, total, off, dtot;
  1163. struct scatterlist *scl;
  1164. struct dbdma_cmd *dcmds;
  1165. dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
  1166. OUTPUT_MORE: INPUT_MORE;
  1167. dcmds = ms->dma_cmds;
  1168. dtot = 0;
  1169. if (cmd) {
  1170. int nseg;
  1171. cmd->SCp.this_residual = scsi_bufflen(cmd);
  1172. nseg = scsi_dma_map(cmd);
  1173. BUG_ON(nseg < 0);
  1174. if (nseg) {
  1175. total = 0;
  1176. off = ms->data_ptr;
  1177. scsi_for_each_sg(cmd, scl, nseg, i) {
  1178. u32 dma_addr = sg_dma_address(scl);
  1179. u32 dma_len = sg_dma_len(scl);
  1180. total += scl->length;
  1181. if (off >= dma_len) {
  1182. off -= dma_len;
  1183. continue;
  1184. }
  1185. if (dma_len > 0xffff)
  1186. panic("mesh: scatterlist element >= 64k");
  1187. dcmds->req_count = cpu_to_le16(dma_len - off);
  1188. dcmds->command = cpu_to_le16(dma_cmd);
  1189. dcmds->phy_addr = cpu_to_le32(dma_addr + off);
  1190. dcmds->xfer_status = 0;
  1191. ++dcmds;
  1192. dtot += dma_len - off;
  1193. off = 0;
  1194. }
  1195. }
  1196. }
  1197. if (dtot == 0) {
  1198. /* Either the target has overrun our buffer,
  1199. or the caller didn't provide a buffer. */
  1200. static char mesh_extra_buf[64];
  1201. dtot = sizeof(mesh_extra_buf);
  1202. dcmds->req_count = cpu_to_le16(dtot);
  1203. dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
  1204. dcmds->xfer_status = 0;
  1205. ++dcmds;
  1206. }
  1207. dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
  1208. dcmds[-1].command = cpu_to_le16(dma_cmd);
  1209. memset(dcmds, 0, sizeof(*dcmds));
  1210. dcmds->command = cpu_to_le16(DBDMA_STOP);
  1211. ms->dma_count = dtot;
  1212. }
  1213. static void halt_dma(struct mesh_state *ms)
  1214. {
  1215. volatile struct dbdma_regs __iomem *md = ms->dma;
  1216. volatile struct mesh_regs __iomem *mr = ms->mesh;
  1217. struct scsi_cmnd *cmd = ms->current_req;
  1218. int t, nb;
  1219. if (!ms->tgts[ms->conn_tgt].data_goes_out) {
  1220. /* wait a little while until the fifo drains */
  1221. t = 50;
  1222. while (t > 0 && in_8(&mr->fifo_count) != 0
  1223. && (in_le32(&md->status) & ACTIVE) != 0) {
  1224. --t;
  1225. udelay(1);
  1226. }
  1227. }
  1228. out_le32(&md->control, RUN << 16); /* turn off RUN bit */
  1229. nb = (mr->count_hi << 8) + mr->count_lo;
  1230. dlog(ms, "halt_dma fc/count=%.6x",
  1231. MKWORD(0, mr->fifo_count, 0, nb));
  1232. if (ms->tgts[ms->conn_tgt].data_goes_out)
  1233. nb += mr->fifo_count;
  1234. /* nb is the number of bytes not yet transferred
  1235. to/from the target. */
  1236. ms->data_ptr -= nb;
  1237. dlog(ms, "data_ptr %x", ms->data_ptr);
  1238. if (ms->data_ptr < 0) {
  1239. printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
  1240. ms->data_ptr, nb, ms);
  1241. ms->data_ptr = 0;
  1242. #ifdef MESH_DBG
  1243. dumplog(ms, ms->conn_tgt);
  1244. dumpslog(ms);
  1245. #endif /* MESH_DBG */
  1246. } else if (cmd && scsi_bufflen(cmd) &&
  1247. ms->data_ptr > scsi_bufflen(cmd)) {
  1248. printk(KERN_DEBUG "mesh: target %d overrun, "
  1249. "data_ptr=%x total=%x goes_out=%d\n",
  1250. ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
  1251. ms->tgts[ms->conn_tgt].data_goes_out);
  1252. }
  1253. if (cmd)
  1254. scsi_dma_unmap(cmd);
  1255. ms->dma_started = 0;
  1256. }
  1257. static void phase_mismatch(struct mesh_state *ms)
  1258. {
  1259. volatile struct mesh_regs __iomem *mr = ms->mesh;
  1260. int phase;
  1261. dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
  1262. MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
  1263. phase = in_8(&mr->bus_status0) & BS0_PHASE;
  1264. if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
  1265. /* output the last byte of the message, without ATN */
  1266. out_8(&mr->count_lo, 1);
  1267. out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
  1268. mesh_flush_io(mr);
  1269. udelay(1);
  1270. out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
  1271. ms->msgphase = msg_out_last;
  1272. return;
  1273. }
  1274. if (ms->msgphase == msg_in) {
  1275. get_msgin(ms);
  1276. if (ms->n_msgin)
  1277. handle_msgin(ms);
  1278. }
  1279. if (ms->dma_started)
  1280. halt_dma(ms);
  1281. if (mr->fifo_count) {
  1282. out_8(&mr->sequence, SEQ_FLUSHFIFO);
  1283. mesh_flush_io(mr);
  1284. udelay(1);
  1285. }
  1286. ms->msgphase = msg_none;
  1287. switch (phase) {
  1288. case BP_DATAIN:
  1289. ms->tgts[ms->conn_tgt].data_goes_out = 0;
  1290. ms->phase = dataing;
  1291. break;
  1292. case BP_DATAOUT:
  1293. ms->tgts[ms->conn_tgt].data_goes_out = 1;
  1294. ms->phase = dataing;
  1295. break;
  1296. case BP_COMMAND:
  1297. ms->phase = commanding;
  1298. break;
  1299. case BP_STATUS:
  1300. ms->phase = statusing;
  1301. break;
  1302. case BP_MSGIN:
  1303. ms->msgphase = msg_in;
  1304. ms->n_msgin = 0;
  1305. break;
  1306. case BP_MSGOUT:
  1307. ms->msgphase = msg_out;
  1308. if (ms->n_msgout == 0) {
  1309. if (ms->aborting) {
  1310. do_abort(ms);
  1311. } else {
  1312. if (ms->last_n_msgout == 0) {
  1313. printk(KERN_DEBUG
  1314. "mesh: no msg to repeat\n");
  1315. ms->msgout[0] = NOP;
  1316. ms->last_n_msgout = 1;
  1317. }
  1318. ms->n_msgout = ms->last_n_msgout;
  1319. }
  1320. }
  1321. break;
  1322. default:
  1323. printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
  1324. ms->stat = DID_ERROR;
  1325. mesh_done(ms, 1);
  1326. return;
  1327. }
  1328. start_phase(ms);
  1329. }
  1330. static void cmd_complete(struct mesh_state *ms)
  1331. {
  1332. volatile struct mesh_regs __iomem *mr = ms->mesh;
  1333. struct scsi_cmnd *cmd = ms->current_req;
  1334. struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
  1335. int seq, n, t;
  1336. dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
  1337. seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
  1338. switch (ms->msgphase) {
  1339. case msg_out_xxx:
  1340. /* huh? we expected a phase mismatch */
  1341. ms->n_msgin = 0;
  1342. ms->msgphase = msg_in;
  1343. fallthrough;
  1344. case msg_in:
  1345. /* should have some message bytes in fifo */
  1346. get_msgin(ms);
  1347. n = msgin_length(ms);
  1348. if (ms->n_msgin < n) {
  1349. out_8(&mr->count_lo, n - ms->n_msgin);
  1350. out_8(&mr->sequence, SEQ_MSGIN + seq);
  1351. } else {
  1352. ms->msgphase = msg_none;
  1353. handle_msgin(ms);
  1354. start_phase(ms);
  1355. }
  1356. break;
  1357. case msg_in_bad:
  1358. out_8(&mr->sequence, SEQ_FLUSHFIFO);
  1359. mesh_flush_io(mr);
  1360. udelay(1);
  1361. out_8(&mr->count_lo, 1);
  1362. out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
  1363. break;
  1364. case msg_out:
  1365. /*
  1366. * To get the right timing on ATN wrt ACK, we have
  1367. * to get the MESH to drop ACK, wait until REQ gets
  1368. * asserted, then drop ATN. To do this we first
  1369. * issue a SEQ_MSGOUT with ATN and wait for REQ,
  1370. * then change the command to a SEQ_MSGOUT w/o ATN.
  1371. * If we don't see REQ in a reasonable time, we
  1372. * change the command to SEQ_MSGIN with ATN,
  1373. * wait for the phase mismatch interrupt, then
  1374. * issue the SEQ_MSGOUT without ATN.
  1375. */
  1376. out_8(&mr->count_lo, 1);
  1377. out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
  1378. t = 30; /* wait up to 30us */
  1379. while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
  1380. udelay(1);
  1381. dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
  1382. MKWORD(mr->error, mr->exception,
  1383. mr->fifo_count, mr->count_lo));
  1384. if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
  1385. /* whoops, target didn't do what we expected */
  1386. ms->last_n_msgout = ms->n_msgout;
  1387. ms->n_msgout = 0;
  1388. if (in_8(&mr->interrupt) & INT_ERROR) {
  1389. printk(KERN_ERR "mesh: error %x in msg_out\n",
  1390. in_8(&mr->error));
  1391. handle_error(ms);
  1392. return;
  1393. }
  1394. if (in_8(&mr->exception) != EXC_PHASEMM)
  1395. printk(KERN_ERR "mesh: exc %x in msg_out\n",
  1396. in_8(&mr->exception));
  1397. else
  1398. printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
  1399. in_8(&mr->bus_status0));
  1400. handle_exception(ms);
  1401. return;
  1402. }
  1403. if (in_8(&mr->bus_status0) & BS0_REQ) {
  1404. out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
  1405. mesh_flush_io(mr);
  1406. udelay(1);
  1407. out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
  1408. ms->msgphase = msg_out_last;
  1409. } else {
  1410. out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
  1411. ms->msgphase = msg_out_xxx;
  1412. }
  1413. break;
  1414. case msg_out_last:
  1415. ms->last_n_msgout = ms->n_msgout;
  1416. ms->n_msgout = 0;
  1417. ms->msgphase = ms->expect_reply? msg_in: msg_none;
  1418. start_phase(ms);
  1419. break;
  1420. case msg_none:
  1421. switch (ms->phase) {
  1422. case idle:
  1423. printk(KERN_ERR "mesh: interrupt in idle phase?\n");
  1424. dumpslog(ms);
  1425. return;
  1426. case selecting:
  1427. dlog(ms, "Selecting phase at command completion",0);
  1428. ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
  1429. (cmd? cmd->device->lun: 0));
  1430. ms->n_msgout = 1;
  1431. ms->expect_reply = 0;
  1432. if (ms->aborting) {
  1433. ms->msgout[0] = ABORT;
  1434. ms->n_msgout++;
  1435. } else if (tp->sdtr_state == do_sdtr) {
  1436. /* add SDTR message */
  1437. add_sdtr_msg(ms);
  1438. ms->expect_reply = 1;
  1439. tp->sdtr_state = sdtr_sent;
  1440. }
  1441. ms->msgphase = msg_out;
  1442. /*
  1443. * We need to wait for REQ before dropping ATN.
  1444. * We wait for at most 30us, then fall back to
  1445. * a scheme where we issue a SEQ_COMMAND with ATN,
  1446. * which will give us a phase mismatch interrupt
  1447. * when REQ does come, and then we send the message.
  1448. */
  1449. t = 230; /* wait up to 230us */
  1450. while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
  1451. if (--t < 0) {
  1452. dlog(ms, "impatient for req", ms->n_msgout);
  1453. ms->msgphase = msg_none;
  1454. break;
  1455. }
  1456. udelay(1);
  1457. }
  1458. break;
  1459. case dataing:
  1460. if (ms->dma_count != 0) {
  1461. start_phase(ms);
  1462. return;
  1463. }
  1464. /*
  1465. * We can get a phase mismatch here if the target
  1466. * changes to the status phase, even though we have
  1467. * had a command complete interrupt. Then, if we
  1468. * issue the SEQ_STATUS command, we'll get a sequence
  1469. * error interrupt. Which isn't so bad except that
  1470. * occasionally the mesh actually executes the
  1471. * SEQ_STATUS *as well as* giving us the sequence
  1472. * error and phase mismatch exception.
  1473. */
  1474. out_8(&mr->sequence, 0);
  1475. out_8(&mr->interrupt,
  1476. INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  1477. halt_dma(ms);
  1478. break;
  1479. case statusing:
  1480. if (cmd) {
  1481. cmd->SCp.Status = mr->fifo;
  1482. if (DEBUG_TARGET(cmd))
  1483. printk(KERN_DEBUG "mesh: status is %x\n",
  1484. cmd->SCp.Status);
  1485. }
  1486. ms->msgphase = msg_in;
  1487. break;
  1488. case busfreeing:
  1489. mesh_done(ms, 1);
  1490. return;
  1491. case disconnecting:
  1492. ms->current_req = NULL;
  1493. ms->phase = idle;
  1494. mesh_start(ms);
  1495. return;
  1496. default:
  1497. break;
  1498. }
  1499. ++ms->phase;
  1500. start_phase(ms);
  1501. break;
  1502. }
  1503. }
  1504. /*
  1505. * Called by midlayer with host locked to queue a new
  1506. * request
  1507. */
  1508. static int mesh_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  1509. {
  1510. struct mesh_state *ms;
  1511. cmd->scsi_done = done;
  1512. cmd->host_scribble = NULL;
  1513. ms = (struct mesh_state *) cmd->device->host->hostdata;
  1514. if (ms->request_q == NULL)
  1515. ms->request_q = cmd;
  1516. else
  1517. ms->request_qtail->host_scribble = (void *) cmd;
  1518. ms->request_qtail = cmd;
  1519. if (ms->phase == idle)
  1520. mesh_start(ms);
  1521. return 0;
  1522. }
  1523. static DEF_SCSI_QCMD(mesh_queue)
  1524. /*
  1525. * Called to handle interrupts, either call by the interrupt
  1526. * handler (do_mesh_interrupt) or by other functions in
  1527. * exceptional circumstances
  1528. */
  1529. static void mesh_interrupt(struct mesh_state *ms)
  1530. {
  1531. volatile struct mesh_regs __iomem *mr = ms->mesh;
  1532. int intr;
  1533. #if 0
  1534. if (ALLOW_DEBUG(ms->conn_tgt))
  1535. printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
  1536. "phase=%d msgphase=%d\n", mr->bus_status0,
  1537. mr->interrupt, mr->exception, mr->error,
  1538. ms->phase, ms->msgphase);
  1539. #endif
  1540. while ((intr = in_8(&mr->interrupt)) != 0) {
  1541. dlog(ms, "interrupt intr/err/exc/seq=%.8x",
  1542. MKWORD(intr, mr->error, mr->exception, mr->sequence));
  1543. if (intr & INT_ERROR) {
  1544. handle_error(ms);
  1545. } else if (intr & INT_EXCEPTION) {
  1546. handle_exception(ms);
  1547. } else if (intr & INT_CMDDONE) {
  1548. out_8(&mr->interrupt, INT_CMDDONE);
  1549. cmd_complete(ms);
  1550. }
  1551. }
  1552. }
  1553. /* Todo: here we can at least try to remove the command from the
  1554. * queue if it isn't connected yet, and for pending command, assert
  1555. * ATN until the bus gets freed.
  1556. */
  1557. static int mesh_abort(struct scsi_cmnd *cmd)
  1558. {
  1559. struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
  1560. printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
  1561. mesh_dump_regs(ms);
  1562. dumplog(ms, cmd->device->id);
  1563. dumpslog(ms);
  1564. return FAILED;
  1565. }
  1566. /*
  1567. * Called by the midlayer with the lock held to reset the
  1568. * SCSI host and bus.
  1569. * The midlayer will wait for devices to come back, we don't need
  1570. * to do that ourselves
  1571. */
  1572. static int mesh_host_reset(struct scsi_cmnd *cmd)
  1573. {
  1574. struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
  1575. volatile struct mesh_regs __iomem *mr = ms->mesh;
  1576. volatile struct dbdma_regs __iomem *md = ms->dma;
  1577. unsigned long flags;
  1578. printk(KERN_DEBUG "mesh_host_reset\n");
  1579. spin_lock_irqsave(ms->host->host_lock, flags);
  1580. if (ms->dma_started)
  1581. halt_dma(ms);
  1582. /* Reset the controller & dbdma channel */
  1583. out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
  1584. out_8(&mr->exception, 0xff); /* clear all exception bits */
  1585. out_8(&mr->error, 0xff); /* clear all error bits */
  1586. out_8(&mr->sequence, SEQ_RESETMESH);
  1587. mesh_flush_io(mr);
  1588. udelay(1);
  1589. out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  1590. out_8(&mr->source_id, ms->host->this_id);
  1591. out_8(&mr->sel_timeout, 25); /* 250ms */
  1592. out_8(&mr->sync_params, ASYNC_PARAMS);
  1593. /* Reset the bus */
  1594. out_8(&mr->bus_status1, BS1_RST); /* assert RST */
  1595. mesh_flush_io(mr);
  1596. udelay(30); /* leave it on for >= 25us */
  1597. out_8(&mr->bus_status1, 0); /* negate RST */
  1598. /* Complete pending commands */
  1599. handle_reset(ms);
  1600. spin_unlock_irqrestore(ms->host->host_lock, flags);
  1601. return SUCCESS;
  1602. }
  1603. static void set_mesh_power(struct mesh_state *ms, int state)
  1604. {
  1605. if (!machine_is(powermac))
  1606. return;
  1607. if (state) {
  1608. pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
  1609. msleep(200);
  1610. } else {
  1611. pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
  1612. msleep(10);
  1613. }
  1614. }
  1615. #ifdef CONFIG_PM
  1616. static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
  1617. {
  1618. struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
  1619. unsigned long flags;
  1620. switch (mesg.event) {
  1621. case PM_EVENT_SUSPEND:
  1622. case PM_EVENT_HIBERNATE:
  1623. case PM_EVENT_FREEZE:
  1624. break;
  1625. default:
  1626. return 0;
  1627. }
  1628. if (ms->phase == sleeping)
  1629. return 0;
  1630. scsi_block_requests(ms->host);
  1631. spin_lock_irqsave(ms->host->host_lock, flags);
  1632. while(ms->phase != idle) {
  1633. spin_unlock_irqrestore(ms->host->host_lock, flags);
  1634. msleep(10);
  1635. spin_lock_irqsave(ms->host->host_lock, flags);
  1636. }
  1637. ms->phase = sleeping;
  1638. spin_unlock_irqrestore(ms->host->host_lock, flags);
  1639. disable_irq(ms->meshintr);
  1640. set_mesh_power(ms, 0);
  1641. return 0;
  1642. }
  1643. static int mesh_resume(struct macio_dev *mdev)
  1644. {
  1645. struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
  1646. unsigned long flags;
  1647. if (ms->phase != sleeping)
  1648. return 0;
  1649. set_mesh_power(ms, 1);
  1650. mesh_init(ms);
  1651. spin_lock_irqsave(ms->host->host_lock, flags);
  1652. mesh_start(ms);
  1653. spin_unlock_irqrestore(ms->host->host_lock, flags);
  1654. enable_irq(ms->meshintr);
  1655. scsi_unblock_requests(ms->host);
  1656. return 0;
  1657. }
  1658. #endif /* CONFIG_PM */
  1659. /*
  1660. * If we leave drives set for synchronous transfers (especially
  1661. * CDROMs), and reboot to MacOS, it gets confused, poor thing.
  1662. * So, on reboot we reset the SCSI bus.
  1663. */
  1664. static int mesh_shutdown(struct macio_dev *mdev)
  1665. {
  1666. struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
  1667. volatile struct mesh_regs __iomem *mr;
  1668. unsigned long flags;
  1669. printk(KERN_INFO "resetting MESH scsi bus(es)\n");
  1670. spin_lock_irqsave(ms->host->host_lock, flags);
  1671. mr = ms->mesh;
  1672. out_8(&mr->intr_mask, 0);
  1673. out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
  1674. out_8(&mr->bus_status1, BS1_RST);
  1675. mesh_flush_io(mr);
  1676. udelay(30);
  1677. out_8(&mr->bus_status1, 0);
  1678. spin_unlock_irqrestore(ms->host->host_lock, flags);
  1679. return 0;
  1680. }
  1681. static struct scsi_host_template mesh_template = {
  1682. .proc_name = "mesh",
  1683. .name = "MESH",
  1684. .queuecommand = mesh_queue,
  1685. .eh_abort_handler = mesh_abort,
  1686. .eh_host_reset_handler = mesh_host_reset,
  1687. .can_queue = 20,
  1688. .this_id = 7,
  1689. .sg_tablesize = SG_ALL,
  1690. .cmd_per_lun = 2,
  1691. .max_segment_size = 65535,
  1692. };
  1693. static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
  1694. {
  1695. struct device_node *mesh = macio_get_of_node(mdev);
  1696. struct pci_dev* pdev = macio_get_pci_dev(mdev);
  1697. int tgt, minper;
  1698. const int *cfp;
  1699. struct mesh_state *ms;
  1700. struct Scsi_Host *mesh_host;
  1701. void *dma_cmd_space;
  1702. dma_addr_t dma_cmd_bus;
  1703. switch (mdev->bus->chip->type) {
  1704. case macio_heathrow:
  1705. case macio_gatwick:
  1706. case macio_paddington:
  1707. use_active_neg = 0;
  1708. break;
  1709. default:
  1710. use_active_neg = SEQ_ACTIVE_NEG;
  1711. }
  1712. if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
  1713. printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
  1714. " (got %d,%d)\n", macio_resource_count(mdev),
  1715. macio_irq_count(mdev));
  1716. return -ENODEV;
  1717. }
  1718. if (macio_request_resources(mdev, "mesh") != 0) {
  1719. printk(KERN_ERR "mesh: unable to request memory resources");
  1720. return -EBUSY;
  1721. }
  1722. mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
  1723. if (mesh_host == NULL) {
  1724. printk(KERN_ERR "mesh: couldn't register host");
  1725. goto out_release;
  1726. }
  1727. /* Old junk for root discovery, that will die ultimately */
  1728. #if !defined(MODULE)
  1729. note_scsi_host(mesh, mesh_host);
  1730. #endif
  1731. mesh_host->base = macio_resource_start(mdev, 0);
  1732. mesh_host->irq = macio_irq(mdev, 0);
  1733. ms = (struct mesh_state *) mesh_host->hostdata;
  1734. macio_set_drvdata(mdev, ms);
  1735. ms->host = mesh_host;
  1736. ms->mdev = mdev;
  1737. ms->pdev = pdev;
  1738. ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
  1739. if (ms->mesh == NULL) {
  1740. printk(KERN_ERR "mesh: can't map registers\n");
  1741. goto out_free;
  1742. }
  1743. ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
  1744. if (ms->dma == NULL) {
  1745. printk(KERN_ERR "mesh: can't map registers\n");
  1746. iounmap(ms->mesh);
  1747. goto out_free;
  1748. }
  1749. ms->meshintr = macio_irq(mdev, 0);
  1750. ms->dmaintr = macio_irq(mdev, 1);
  1751. /* Space for dma command list: +1 for stop command,
  1752. * +1 to allow for aligning.
  1753. */
  1754. ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
  1755. /* We use the PCI APIs for now until the generic one gets fixed
  1756. * enough or until we get some macio-specific versions
  1757. */
  1758. dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
  1759. ms->dma_cmd_size, &dma_cmd_bus,
  1760. GFP_KERNEL);
  1761. if (dma_cmd_space == NULL) {
  1762. printk(KERN_ERR "mesh: can't allocate DMA table\n");
  1763. goto out_unmap;
  1764. }
  1765. ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
  1766. ms->dma_cmd_space = dma_cmd_space;
  1767. ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
  1768. - (unsigned long)dma_cmd_space;
  1769. ms->current_req = NULL;
  1770. for (tgt = 0; tgt < 8; ++tgt) {
  1771. ms->tgts[tgt].sdtr_state = do_sdtr;
  1772. ms->tgts[tgt].sync_params = ASYNC_PARAMS;
  1773. ms->tgts[tgt].current_req = NULL;
  1774. }
  1775. if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
  1776. ms->clk_freq = *cfp;
  1777. else {
  1778. printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
  1779. ms->clk_freq = 50000000;
  1780. }
  1781. /* The maximum sync rate is clock / 5; increase
  1782. * mesh_sync_period if necessary.
  1783. */
  1784. minper = 1000000000 / (ms->clk_freq / 5); /* ns */
  1785. if (mesh_sync_period < minper)
  1786. mesh_sync_period = minper;
  1787. /* Power up the chip */
  1788. set_mesh_power(ms, 1);
  1789. /* Set it up */
  1790. mesh_init(ms);
  1791. /* Request interrupt */
  1792. if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
  1793. printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
  1794. goto out_shutdown;
  1795. }
  1796. /* Add scsi host & scan */
  1797. if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
  1798. goto out_release_irq;
  1799. scsi_scan_host(mesh_host);
  1800. return 0;
  1801. out_release_irq:
  1802. free_irq(ms->meshintr, ms);
  1803. out_shutdown:
  1804. /* shutdown & reset bus in case of error or macos can be confused
  1805. * at reboot if the bus was set to synchronous mode already
  1806. */
  1807. mesh_shutdown(mdev);
  1808. set_mesh_power(ms, 0);
  1809. dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
  1810. ms->dma_cmd_space, ms->dma_cmd_bus);
  1811. out_unmap:
  1812. iounmap(ms->dma);
  1813. iounmap(ms->mesh);
  1814. out_free:
  1815. scsi_host_put(mesh_host);
  1816. out_release:
  1817. macio_release_resources(mdev);
  1818. return -ENODEV;
  1819. }
  1820. static int mesh_remove(struct macio_dev *mdev)
  1821. {
  1822. struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
  1823. struct Scsi_Host *mesh_host = ms->host;
  1824. scsi_remove_host(mesh_host);
  1825. free_irq(ms->meshintr, ms);
  1826. /* Reset scsi bus */
  1827. mesh_shutdown(mdev);
  1828. /* Shut down chip & termination */
  1829. set_mesh_power(ms, 0);
  1830. /* Unmap registers & dma controller */
  1831. iounmap(ms->mesh);
  1832. iounmap(ms->dma);
  1833. /* Free DMA commands memory */
  1834. dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
  1835. ms->dma_cmd_space, ms->dma_cmd_bus);
  1836. /* Release memory resources */
  1837. macio_release_resources(mdev);
  1838. scsi_host_put(mesh_host);
  1839. return 0;
  1840. }
  1841. static struct of_device_id mesh_match[] =
  1842. {
  1843. {
  1844. .name = "mesh",
  1845. },
  1846. {
  1847. .type = "scsi",
  1848. .compatible = "chrp,mesh0"
  1849. },
  1850. {},
  1851. };
  1852. MODULE_DEVICE_TABLE (of, mesh_match);
  1853. static struct macio_driver mesh_driver =
  1854. {
  1855. .driver = {
  1856. .name = "mesh",
  1857. .owner = THIS_MODULE,
  1858. .of_match_table = mesh_match,
  1859. },
  1860. .probe = mesh_probe,
  1861. .remove = mesh_remove,
  1862. .shutdown = mesh_shutdown,
  1863. #ifdef CONFIG_PM
  1864. .suspend = mesh_suspend,
  1865. .resume = mesh_resume,
  1866. #endif
  1867. };
  1868. static int __init init_mesh(void)
  1869. {
  1870. /* Calculate sync rate from module parameters */
  1871. if (sync_rate > 10)
  1872. sync_rate = 10;
  1873. if (sync_rate > 0) {
  1874. printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
  1875. mesh_sync_period = 1000 / sync_rate; /* ns */
  1876. mesh_sync_offset = 15;
  1877. } else
  1878. printk(KERN_INFO "mesh: configured for asynchronous\n");
  1879. return macio_register_driver(&mesh_driver);
  1880. }
  1881. static void __exit exit_mesh(void)
  1882. {
  1883. return macio_unregister_driver(&mesh_driver);
  1884. }
  1885. module_init(init_mesh);
  1886. module_exit(exit_mesh);