ips.h 41 KB

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  1. /*****************************************************************************/
  2. /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
  3. /* */
  4. /* Written By: Keith Mitchell, IBM Corporation */
  5. /* Jack Hammer, Adaptec, Inc. */
  6. /* David Jeffery, Adaptec, Inc. */
  7. /* */
  8. /* Copyright (C) 1999 IBM Corporation */
  9. /* Copyright (C) 2003 Adaptec, Inc. */
  10. /* */
  11. /* This program is free software; you can redistribute it and/or modify */
  12. /* it under the terms of the GNU General Public License as published by */
  13. /* the Free Software Foundation; either version 2 of the License, or */
  14. /* (at your option) any later version. */
  15. /* */
  16. /* This program is distributed in the hope that it will be useful, */
  17. /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
  18. /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
  19. /* GNU General Public License for more details. */
  20. /* */
  21. /* NO WARRANTY */
  22. /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
  23. /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
  24. /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
  25. /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
  26. /* solely responsible for determining the appropriateness of using and */
  27. /* distributing the Program and assumes all risks associated with its */
  28. /* exercise of rights under this Agreement, including but not limited to */
  29. /* the risks and costs of program errors, damage to or loss of data, */
  30. /* programs or equipment, and unavailability or interruption of operations. */
  31. /* */
  32. /* DISCLAIMER OF LIABILITY */
  33. /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
  34. /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
  35. /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
  36. /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
  37. /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
  38. /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
  39. /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
  40. /* */
  41. /* You should have received a copy of the GNU General Public License */
  42. /* along with this program; if not, write to the Free Software */
  43. /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
  44. /* */
  45. /* Bugs/Comments/Suggestions should be mailed to: */
  46. /* ipslinux@adaptec.com */
  47. /* */
  48. /*****************************************************************************/
  49. #ifndef _IPS_H_
  50. #define _IPS_H_
  51. #include <linux/nmi.h>
  52. #include <linux/uaccess.h>
  53. #include <asm/io.h>
  54. /*
  55. * Some handy macros
  56. */
  57. #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
  58. #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
  59. #define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
  60. (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
  61. (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
  62. #define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
  63. (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
  64. (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
  65. #define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
  66. #define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO)
  67. #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
  68. (IPS_IS_TROMBONE(ha) && \
  69. (ips_force_i2o))) ? 1 : 0)
  70. #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
  71. ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
  72. (ips_force_memio))) ? 1 : 0)
  73. #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
  74. #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
  75. #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
  76. sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
  77. #define IPS_PRINTK(level, pcidev, format, arg...) \
  78. dev_printk(level , &((pcidev)->dev) , format , ## arg)
  79. #define MDELAY(n) \
  80. do { \
  81. mdelay(n); \
  82. touch_nmi_watchdog(); \
  83. } while (0)
  84. #ifndef min
  85. #define min(x,y) ((x) < (y) ? x : y)
  86. #endif
  87. #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
  88. #define __iomem
  89. #endif
  90. /*
  91. * Adapter address map equates
  92. */
  93. #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
  94. #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
  95. #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
  96. #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
  97. #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
  98. #define IPS_REG_SQER 0x28 /* Status Q End Reg */
  99. #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
  100. #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
  101. #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
  102. #define IPS_REG_CBSP 0x07 /* CBSP register */
  103. #define IPS_REG_FLAP 0x18 /* Flash address port */
  104. #define IPS_REG_FLDP 0x1C /* Flash data port */
  105. #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
  106. #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
  107. #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
  108. #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
  109. #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
  110. #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
  111. #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
  112. #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
  113. /*
  114. * Adapter register bit equates
  115. */
  116. #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
  117. #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
  118. #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
  119. #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
  120. #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
  121. #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
  122. #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
  123. #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
  124. #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
  125. #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
  126. #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
  127. #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
  128. #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
  129. #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
  130. /*
  131. * Adapter Command ID Equates
  132. */
  133. #define IPS_CMD_GET_LD_INFO 0x19
  134. #define IPS_CMD_GET_SUBSYS 0x40
  135. #define IPS_CMD_READ_CONF 0x38
  136. #define IPS_CMD_RW_NVRAM_PAGE 0xBC
  137. #define IPS_CMD_READ 0x02
  138. #define IPS_CMD_WRITE 0x03
  139. #define IPS_CMD_FFDC 0xD7
  140. #define IPS_CMD_ENQUIRY 0x05
  141. #define IPS_CMD_FLUSH 0x0A
  142. #define IPS_CMD_READ_SG 0x82
  143. #define IPS_CMD_WRITE_SG 0x83
  144. #define IPS_CMD_DCDB 0x04
  145. #define IPS_CMD_DCDB_SG 0x84
  146. #define IPS_CMD_EXTENDED_DCDB 0x95
  147. #define IPS_CMD_EXTENDED_DCDB_SG 0x96
  148. #define IPS_CMD_CONFIG_SYNC 0x58
  149. #define IPS_CMD_ERROR_TABLE 0x17
  150. #define IPS_CMD_DOWNLOAD 0x20
  151. #define IPS_CMD_RW_BIOSFW 0x22
  152. #define IPS_CMD_GET_VERSION_INFO 0xC6
  153. #define IPS_CMD_RESET_CHANNEL 0x1A
  154. /*
  155. * Adapter Equates
  156. */
  157. #define IPS_CSL 0xFF
  158. #define IPS_POCL 0x30
  159. #define IPS_NORM_STATE 0x00
  160. #define IPS_MAX_ADAPTER_TYPES 3
  161. #define IPS_MAX_ADAPTERS 16
  162. #define IPS_MAX_IOCTL 1
  163. #define IPS_MAX_IOCTL_QUEUE 8
  164. #define IPS_MAX_QUEUE 128
  165. #define IPS_BLKSIZE 512
  166. #define IPS_MAX_SG 17
  167. #define IPS_MAX_LD 8
  168. #define IPS_MAX_CHANNELS 4
  169. #define IPS_MAX_TARGETS 15
  170. #define IPS_MAX_CHUNKS 16
  171. #define IPS_MAX_CMDS 128
  172. #define IPS_MAX_XFER 0x10000
  173. #define IPS_NVRAM_P5_SIG 0xFFDDBB99
  174. #define IPS_MAX_POST_BYTES 0x02
  175. #define IPS_MAX_CONFIG_BYTES 0x02
  176. #define IPS_GOOD_POST_STATUS 0x80
  177. #define IPS_SEM_TIMEOUT 2000
  178. #define IPS_IOCTL_COMMAND 0x0D
  179. #define IPS_INTR_ON 0
  180. #define IPS_INTR_IORL 1
  181. #define IPS_FFDC 99
  182. #define IPS_ADAPTER_ID 0xF
  183. #define IPS_VENDORID_IBM 0x1014
  184. #define IPS_VENDORID_ADAPTEC 0x9005
  185. #define IPS_DEVICEID_COPPERHEAD 0x002E
  186. #define IPS_DEVICEID_MORPHEUS 0x01BD
  187. #define IPS_DEVICEID_MARCO 0x0250
  188. #define IPS_SUBDEVICEID_4M 0x01BE
  189. #define IPS_SUBDEVICEID_4L 0x01BF
  190. #define IPS_SUBDEVICEID_4MX 0x0208
  191. #define IPS_SUBDEVICEID_4LX 0x020E
  192. #define IPS_SUBDEVICEID_5I2 0x0259
  193. #define IPS_SUBDEVICEID_5I1 0x0258
  194. #define IPS_SUBDEVICEID_6M 0x0279
  195. #define IPS_SUBDEVICEID_6I 0x028C
  196. #define IPS_SUBDEVICEID_7k 0x028E
  197. #define IPS_SUBDEVICEID_7M 0x028F
  198. #define IPS_IOCTL_SIZE 8192
  199. #define IPS_STATUS_SIZE 4
  200. #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
  201. #define IPS_IMAGE_SIZE 500 * 1024
  202. #define IPS_MEMMAP_SIZE 128
  203. #define IPS_ONE_MSEC 1
  204. #define IPS_ONE_SEC 1000
  205. /*
  206. * Geometry Settings
  207. */
  208. #define IPS_COMP_HEADS 128
  209. #define IPS_COMP_SECTORS 32
  210. #define IPS_NORM_HEADS 254
  211. #define IPS_NORM_SECTORS 63
  212. /*
  213. * Adapter Basic Status Codes
  214. */
  215. #define IPS_BASIC_STATUS_MASK 0xFF
  216. #define IPS_GSC_STATUS_MASK 0x0F
  217. #define IPS_CMD_SUCCESS 0x00
  218. #define IPS_CMD_RECOVERED_ERROR 0x01
  219. #define IPS_INVAL_OPCO 0x03
  220. #define IPS_INVAL_CMD_BLK 0x04
  221. #define IPS_INVAL_PARM_BLK 0x05
  222. #define IPS_BUSY 0x08
  223. #define IPS_CMD_CMPLT_WERROR 0x0C
  224. #define IPS_LD_ERROR 0x0D
  225. #define IPS_CMD_TIMEOUT 0x0E
  226. #define IPS_PHYS_DRV_ERROR 0x0F
  227. /*
  228. * Adapter Extended Status Equates
  229. */
  230. #define IPS_ERR_SEL_TO 0xF0
  231. #define IPS_ERR_OU_RUN 0xF2
  232. #define IPS_ERR_HOST_RESET 0xF7
  233. #define IPS_ERR_DEV_RESET 0xF8
  234. #define IPS_ERR_RECOVERY 0xFC
  235. #define IPS_ERR_CKCOND 0xFF
  236. /*
  237. * Operating System Defines
  238. */
  239. #define IPS_OS_WINDOWS_NT 0x01
  240. #define IPS_OS_NETWARE 0x02
  241. #define IPS_OS_OPENSERVER 0x03
  242. #define IPS_OS_UNIXWARE 0x04
  243. #define IPS_OS_SOLARIS 0x05
  244. #define IPS_OS_OS2 0x06
  245. #define IPS_OS_LINUX 0x07
  246. #define IPS_OS_FREEBSD 0x08
  247. /*
  248. * Adapter Revision ID's
  249. */
  250. #define IPS_REVID_SERVERAID 0x02
  251. #define IPS_REVID_NAVAJO 0x03
  252. #define IPS_REVID_SERVERAID2 0x04
  253. #define IPS_REVID_CLARINETP1 0x05
  254. #define IPS_REVID_CLARINETP2 0x07
  255. #define IPS_REVID_CLARINETP3 0x0D
  256. #define IPS_REVID_TROMBONE32 0x0F
  257. #define IPS_REVID_TROMBONE64 0x10
  258. /*
  259. * NVRAM Page 5 Adapter Defines
  260. */
  261. #define IPS_ADTYPE_SERVERAID 0x01
  262. #define IPS_ADTYPE_SERVERAID2 0x02
  263. #define IPS_ADTYPE_NAVAJO 0x03
  264. #define IPS_ADTYPE_KIOWA 0x04
  265. #define IPS_ADTYPE_SERVERAID3 0x05
  266. #define IPS_ADTYPE_SERVERAID3L 0x06
  267. #define IPS_ADTYPE_SERVERAID4H 0x07
  268. #define IPS_ADTYPE_SERVERAID4M 0x08
  269. #define IPS_ADTYPE_SERVERAID4L 0x09
  270. #define IPS_ADTYPE_SERVERAID4MX 0x0A
  271. #define IPS_ADTYPE_SERVERAID4LX 0x0B
  272. #define IPS_ADTYPE_SERVERAID5I2 0x0C
  273. #define IPS_ADTYPE_SERVERAID5I1 0x0D
  274. #define IPS_ADTYPE_SERVERAID6M 0x0E
  275. #define IPS_ADTYPE_SERVERAID6I 0x0F
  276. #define IPS_ADTYPE_SERVERAID7t 0x10
  277. #define IPS_ADTYPE_SERVERAID7k 0x11
  278. #define IPS_ADTYPE_SERVERAID7M 0x12
  279. /*
  280. * Adapter Command/Status Packet Definitions
  281. */
  282. #define IPS_SUCCESS 0x01 /* Successfully completed */
  283. #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
  284. #define IPS_FAILURE 0x04 /* Completed with Error */
  285. /*
  286. * Logical Drive Equates
  287. */
  288. #define IPS_LD_OFFLINE 0x02
  289. #define IPS_LD_OKAY 0x03
  290. #define IPS_LD_FREE 0x00
  291. #define IPS_LD_SYS 0x06
  292. #define IPS_LD_CRS 0x24
  293. /*
  294. * DCDB Table Equates
  295. */
  296. #define IPS_NO_DISCONNECT 0x00
  297. #define IPS_DISCONNECT_ALLOWED 0x80
  298. #define IPS_NO_AUTO_REQSEN 0x40
  299. #define IPS_DATA_NONE 0x00
  300. #define IPS_DATA_UNK 0x00
  301. #define IPS_DATA_IN 0x01
  302. #define IPS_DATA_OUT 0x02
  303. #define IPS_TRANSFER64K 0x08
  304. #define IPS_NOTIMEOUT 0x00
  305. #define IPS_TIMEOUT10 0x10
  306. #define IPS_TIMEOUT60 0x20
  307. #define IPS_TIMEOUT20M 0x30
  308. /*
  309. * SCSI Inquiry Data Flags
  310. */
  311. #define IPS_SCSI_INQ_TYPE_DASD 0x00
  312. #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
  313. #define IPS_SCSI_INQ_LU_CONNECTED 0x00
  314. #define IPS_SCSI_INQ_RD_REV2 0x02
  315. #define IPS_SCSI_INQ_REV2 0x02
  316. #define IPS_SCSI_INQ_REV3 0x03
  317. #define IPS_SCSI_INQ_Address16 0x01
  318. #define IPS_SCSI_INQ_Address32 0x02
  319. #define IPS_SCSI_INQ_MedChanger 0x08
  320. #define IPS_SCSI_INQ_MultiPort 0x10
  321. #define IPS_SCSI_INQ_EncServ 0x40
  322. #define IPS_SCSI_INQ_SoftReset 0x01
  323. #define IPS_SCSI_INQ_CmdQue 0x02
  324. #define IPS_SCSI_INQ_Linked 0x08
  325. #define IPS_SCSI_INQ_Sync 0x10
  326. #define IPS_SCSI_INQ_WBus16 0x20
  327. #define IPS_SCSI_INQ_WBus32 0x40
  328. #define IPS_SCSI_INQ_RelAdr 0x80
  329. /*
  330. * SCSI Request Sense Data Flags
  331. */
  332. #define IPS_SCSI_REQSEN_VALID 0x80
  333. #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
  334. #define IPS_SCSI_REQSEN_NO_SENSE 0x00
  335. /*
  336. * SCSI Mode Page Equates
  337. */
  338. #define IPS_SCSI_MP3_SoftSector 0x01
  339. #define IPS_SCSI_MP3_HardSector 0x02
  340. #define IPS_SCSI_MP3_Removeable 0x04
  341. #define IPS_SCSI_MP3_AllocateSurface 0x08
  342. /*
  343. * HA Flags
  344. */
  345. #define IPS_HA_ENH_SG 0x1
  346. /*
  347. * SCB Flags
  348. */
  349. #define IPS_SCB_MAP_SG 0x00008
  350. #define IPS_SCB_MAP_SINGLE 0X00010
  351. /*
  352. * Passthru stuff
  353. */
  354. #define IPS_COPPUSRCMD (('C'<<8) | 65)
  355. #define IPS_COPPIOCCMD (('C'<<8) | 66)
  356. #define IPS_NUMCTRLS (('C'<<8) | 68)
  357. #define IPS_CTRLINFO (('C'<<8) | 69)
  358. /* flashing defines */
  359. #define IPS_FW_IMAGE 0x00
  360. #define IPS_BIOS_IMAGE 0x01
  361. #define IPS_WRITE_FW 0x01
  362. #define IPS_WRITE_BIOS 0x02
  363. #define IPS_ERASE_BIOS 0x03
  364. #define IPS_BIOS_HEADER 0xC0
  365. /* time oriented stuff */
  366. #define IPS_SECS_8HOURS 28800
  367. /*
  368. * Scsi_Host Template
  369. */
  370. static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
  371. sector_t capacity, int geom[]);
  372. static int ips_slave_configure(struct scsi_device *SDptr);
  373. /*
  374. * Raid Command Formats
  375. */
  376. typedef struct {
  377. uint8_t op_code;
  378. uint8_t command_id;
  379. uint8_t log_drv;
  380. uint8_t sg_count;
  381. uint32_t lba;
  382. uint32_t sg_addr;
  383. uint16_t sector_count;
  384. uint8_t segment_4G;
  385. uint8_t enhanced_sg;
  386. uint32_t ccsar;
  387. uint32_t cccr;
  388. } IPS_IO_CMD, *PIPS_IO_CMD;
  389. typedef struct {
  390. uint8_t op_code;
  391. uint8_t command_id;
  392. uint16_t reserved;
  393. uint32_t reserved2;
  394. uint32_t buffer_addr;
  395. uint32_t reserved3;
  396. uint32_t ccsar;
  397. uint32_t cccr;
  398. } IPS_LD_CMD, *PIPS_LD_CMD;
  399. typedef struct {
  400. uint8_t op_code;
  401. uint8_t command_id;
  402. uint8_t reserved;
  403. uint8_t reserved2;
  404. uint32_t reserved3;
  405. uint32_t buffer_addr;
  406. uint32_t reserved4;
  407. } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
  408. typedef struct {
  409. uint8_t op_code;
  410. uint8_t command_id;
  411. uint8_t channel;
  412. uint8_t reserved3;
  413. uint8_t reserved4;
  414. uint8_t reserved5;
  415. uint8_t reserved6;
  416. uint8_t reserved7;
  417. uint8_t reserved8;
  418. uint8_t reserved9;
  419. uint8_t reserved10;
  420. uint8_t reserved11;
  421. uint8_t reserved12;
  422. uint8_t reserved13;
  423. uint8_t reserved14;
  424. uint8_t adapter_flag;
  425. } IPS_RESET_CMD, *PIPS_RESET_CMD;
  426. typedef struct {
  427. uint8_t op_code;
  428. uint8_t command_id;
  429. uint16_t reserved;
  430. uint32_t reserved2;
  431. uint32_t dcdb_address;
  432. uint16_t reserved3;
  433. uint8_t segment_4G;
  434. uint8_t enhanced_sg;
  435. uint32_t ccsar;
  436. uint32_t cccr;
  437. } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
  438. typedef struct {
  439. uint8_t op_code;
  440. uint8_t command_id;
  441. uint8_t channel;
  442. uint8_t source_target;
  443. uint32_t reserved;
  444. uint32_t reserved2;
  445. uint32_t reserved3;
  446. uint32_t ccsar;
  447. uint32_t cccr;
  448. } IPS_CS_CMD, *PIPS_CS_CMD;
  449. typedef struct {
  450. uint8_t op_code;
  451. uint8_t command_id;
  452. uint8_t log_drv;
  453. uint8_t control;
  454. uint32_t reserved;
  455. uint32_t reserved2;
  456. uint32_t reserved3;
  457. uint32_t ccsar;
  458. uint32_t cccr;
  459. } IPS_US_CMD, *PIPS_US_CMD;
  460. typedef struct {
  461. uint8_t op_code;
  462. uint8_t command_id;
  463. uint8_t reserved;
  464. uint8_t state;
  465. uint32_t reserved2;
  466. uint32_t reserved3;
  467. uint32_t reserved4;
  468. uint32_t ccsar;
  469. uint32_t cccr;
  470. } IPS_FC_CMD, *PIPS_FC_CMD;
  471. typedef struct {
  472. uint8_t op_code;
  473. uint8_t command_id;
  474. uint8_t reserved;
  475. uint8_t desc;
  476. uint32_t reserved2;
  477. uint32_t buffer_addr;
  478. uint32_t reserved3;
  479. uint32_t ccsar;
  480. uint32_t cccr;
  481. } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
  482. typedef struct {
  483. uint8_t op_code;
  484. uint8_t command_id;
  485. uint8_t page;
  486. uint8_t write;
  487. uint32_t reserved;
  488. uint32_t buffer_addr;
  489. uint32_t reserved2;
  490. uint32_t ccsar;
  491. uint32_t cccr;
  492. } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
  493. typedef struct
  494. {
  495. uint8_t op_code;
  496. uint8_t command_id;
  497. uint16_t reserved;
  498. uint32_t count;
  499. uint32_t buffer_addr;
  500. uint32_t reserved2;
  501. } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
  502. typedef struct {
  503. uint8_t op_code;
  504. uint8_t command_id;
  505. uint8_t reset_count;
  506. uint8_t reset_type;
  507. uint8_t second;
  508. uint8_t minute;
  509. uint8_t hour;
  510. uint8_t day;
  511. uint8_t reserved1[4];
  512. uint8_t month;
  513. uint8_t yearH;
  514. uint8_t yearL;
  515. uint8_t reserved2;
  516. } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
  517. typedef struct {
  518. uint8_t op_code;
  519. uint8_t command_id;
  520. uint8_t type;
  521. uint8_t direction;
  522. uint32_t count;
  523. uint32_t buffer_addr;
  524. uint8_t total_packets;
  525. uint8_t packet_num;
  526. uint16_t reserved;
  527. } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
  528. typedef struct {
  529. uint8_t op_code;
  530. uint8_t command_id;
  531. uint8_t type;
  532. uint8_t direction;
  533. uint32_t count;
  534. uint32_t buffer_addr;
  535. uint32_t offset;
  536. } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
  537. typedef union {
  538. IPS_IO_CMD basic_io;
  539. IPS_LD_CMD logical_info;
  540. IPS_IOCTL_CMD ioctl_info;
  541. IPS_DCDB_CMD dcdb;
  542. IPS_CS_CMD config_sync;
  543. IPS_US_CMD unlock_stripe;
  544. IPS_FC_CMD flush_cache;
  545. IPS_STATUS_CMD status;
  546. IPS_NVRAM_CMD nvram;
  547. IPS_FFDC_CMD ffdc;
  548. IPS_FLASHFW_CMD flashfw;
  549. IPS_FLASHBIOS_CMD flashbios;
  550. IPS_VERSION_INFO version_info;
  551. IPS_RESET_CMD reset;
  552. } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
  553. typedef struct {
  554. uint8_t logical_id;
  555. uint8_t reserved;
  556. uint8_t raid_level;
  557. uint8_t state;
  558. uint32_t sector_count;
  559. } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
  560. typedef struct {
  561. uint8_t no_of_log_drive;
  562. uint8_t reserved[3];
  563. IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
  564. } IPS_LD_INFO, *PIPS_LD_INFO;
  565. typedef struct {
  566. uint8_t device_address;
  567. uint8_t cmd_attribute;
  568. uint16_t transfer_length;
  569. uint32_t buffer_pointer;
  570. uint8_t cdb_length;
  571. uint8_t sense_length;
  572. uint8_t sg_count;
  573. uint8_t reserved;
  574. uint8_t scsi_cdb[12];
  575. uint8_t sense_info[64];
  576. uint8_t scsi_status;
  577. uint8_t reserved2[3];
  578. } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
  579. typedef struct {
  580. uint8_t device_address;
  581. uint8_t cmd_attribute;
  582. uint8_t cdb_length;
  583. uint8_t reserved_for_LUN;
  584. uint32_t transfer_length;
  585. uint32_t buffer_pointer;
  586. uint16_t sg_count;
  587. uint8_t sense_length;
  588. uint8_t scsi_status;
  589. uint32_t reserved;
  590. uint8_t scsi_cdb[16];
  591. uint8_t sense_info[56];
  592. } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
  593. typedef union {
  594. struct {
  595. volatile uint8_t reserved;
  596. volatile uint8_t command_id;
  597. volatile uint8_t basic_status;
  598. volatile uint8_t extended_status;
  599. } fields;
  600. volatile uint32_t value;
  601. } IPS_STATUS, *PIPS_STATUS;
  602. typedef struct {
  603. IPS_STATUS status[IPS_MAX_CMDS + 1];
  604. volatile PIPS_STATUS p_status_start;
  605. volatile PIPS_STATUS p_status_end;
  606. volatile PIPS_STATUS p_status_tail;
  607. volatile uint32_t hw_status_start;
  608. volatile uint32_t hw_status_tail;
  609. } IPS_ADAPTER, *PIPS_ADAPTER;
  610. typedef struct {
  611. uint8_t ucLogDriveCount;
  612. uint8_t ucMiscFlag;
  613. uint8_t ucSLTFlag;
  614. uint8_t ucBSTFlag;
  615. uint8_t ucPwrChgCnt;
  616. uint8_t ucWrongAdrCnt;
  617. uint8_t ucUnidentCnt;
  618. uint8_t ucNVramDevChgCnt;
  619. uint8_t CodeBlkVersion[8];
  620. uint8_t BootBlkVersion[8];
  621. uint32_t ulDriveSize[IPS_MAX_LD];
  622. uint8_t ucConcurrentCmdCount;
  623. uint8_t ucMaxPhysicalDevices;
  624. uint16_t usFlashRepgmCount;
  625. uint8_t ucDefunctDiskCount;
  626. uint8_t ucRebuildFlag;
  627. uint8_t ucOfflineLogDrvCount;
  628. uint8_t ucCriticalDrvCount;
  629. uint16_t usConfigUpdateCount;
  630. uint8_t ucBlkFlag;
  631. uint8_t reserved;
  632. uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
  633. } IPS_ENQ, *PIPS_ENQ;
  634. typedef struct {
  635. uint8_t ucInitiator;
  636. uint8_t ucParameters;
  637. uint8_t ucMiscFlag;
  638. uint8_t ucState;
  639. uint32_t ulBlockCount;
  640. uint8_t ucDeviceId[28];
  641. } IPS_DEVSTATE, *PIPS_DEVSTATE;
  642. typedef struct {
  643. uint8_t ucChn;
  644. uint8_t ucTgt;
  645. uint16_t ucReserved;
  646. uint32_t ulStartSect;
  647. uint32_t ulNoOfSects;
  648. } IPS_CHUNK, *PIPS_CHUNK;
  649. typedef struct {
  650. uint16_t ucUserField;
  651. uint8_t ucState;
  652. uint8_t ucRaidCacheParam;
  653. uint8_t ucNoOfChunkUnits;
  654. uint8_t ucStripeSize;
  655. uint8_t ucParams;
  656. uint8_t ucReserved;
  657. uint32_t ulLogDrvSize;
  658. IPS_CHUNK chunk[IPS_MAX_CHUNKS];
  659. } IPS_LD, *PIPS_LD;
  660. typedef struct {
  661. uint8_t board_disc[8];
  662. uint8_t processor[8];
  663. uint8_t ucNoChanType;
  664. uint8_t ucNoHostIntType;
  665. uint8_t ucCompression;
  666. uint8_t ucNvramType;
  667. uint32_t ulNvramSize;
  668. } IPS_HARDWARE, *PIPS_HARDWARE;
  669. typedef struct {
  670. uint8_t ucLogDriveCount;
  671. uint8_t ucDateD;
  672. uint8_t ucDateM;
  673. uint8_t ucDateY;
  674. uint8_t init_id[4];
  675. uint8_t host_id[12];
  676. uint8_t time_sign[8];
  677. uint32_t UserOpt;
  678. uint16_t user_field;
  679. uint8_t ucRebuildRate;
  680. uint8_t ucReserve;
  681. IPS_HARDWARE hardware_disc;
  682. IPS_LD logical_drive[IPS_MAX_LD];
  683. IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
  684. uint8_t reserved[512];
  685. } IPS_CONF, *PIPS_CONF;
  686. typedef struct {
  687. uint32_t signature;
  688. uint8_t reserved1;
  689. uint8_t adapter_slot;
  690. uint16_t adapter_type;
  691. uint8_t ctrl_bios[8];
  692. uint8_t versioning; /* 1 = Versioning Supported, else 0 */
  693. uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */
  694. uint8_t reserved2;
  695. uint8_t operating_system;
  696. uint8_t driver_high[4];
  697. uint8_t driver_low[4];
  698. uint8_t BiosCompatibilityID[8];
  699. uint8_t ReservedForOS2[8];
  700. uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */
  701. uint8_t bios_low[4];
  702. uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */
  703. uint8_t Filler[60];
  704. } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
  705. /*--------------------------------------------------------------------------*/
  706. /* Data returned from a GetVersion Command */
  707. /*--------------------------------------------------------------------------*/
  708. /* SubSystem Parameter[4] */
  709. #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
  710. typedef struct
  711. {
  712. uint32_t revision;
  713. uint8_t bootBlkVersion[32];
  714. uint8_t bootBlkAttributes[4];
  715. uint8_t codeBlkVersion[32];
  716. uint8_t biosVersion[32];
  717. uint8_t biosAttributes[4];
  718. uint8_t compatibilityId[32];
  719. uint8_t reserved[4];
  720. } IPS_VERSION_DATA;
  721. typedef struct _IPS_SUBSYS {
  722. uint32_t param[128];
  723. } IPS_SUBSYS, *PIPS_SUBSYS;
  724. /**
  725. ** SCSI Structures
  726. **/
  727. /*
  728. * Inquiry Data Format
  729. */
  730. typedef struct {
  731. uint8_t DeviceType;
  732. uint8_t DeviceTypeQualifier;
  733. uint8_t Version;
  734. uint8_t ResponseDataFormat;
  735. uint8_t AdditionalLength;
  736. uint8_t Reserved;
  737. uint8_t Flags[2];
  738. uint8_t VendorId[8];
  739. uint8_t ProductId[16];
  740. uint8_t ProductRevisionLevel[4];
  741. uint8_t Reserved2; /* Provides NULL terminator to name */
  742. } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
  743. /*
  744. * Read Capacity Data Format
  745. */
  746. typedef struct {
  747. uint32_t lba;
  748. uint32_t len;
  749. } IPS_SCSI_CAPACITY;
  750. /*
  751. * Request Sense Data Format
  752. */
  753. typedef struct {
  754. uint8_t ResponseCode;
  755. uint8_t SegmentNumber;
  756. uint8_t Flags;
  757. uint8_t Information[4];
  758. uint8_t AdditionalLength;
  759. uint8_t CommandSpecific[4];
  760. uint8_t AdditionalSenseCode;
  761. uint8_t AdditionalSenseCodeQual;
  762. uint8_t FRUCode;
  763. uint8_t SenseKeySpecific[3];
  764. } IPS_SCSI_REQSEN;
  765. /*
  766. * Sense Data Format - Page 3
  767. */
  768. typedef struct {
  769. uint8_t PageCode;
  770. uint8_t PageLength;
  771. uint16_t TracksPerZone;
  772. uint16_t AltSectorsPerZone;
  773. uint16_t AltTracksPerZone;
  774. uint16_t AltTracksPerVolume;
  775. uint16_t SectorsPerTrack;
  776. uint16_t BytesPerSector;
  777. uint16_t Interleave;
  778. uint16_t TrackSkew;
  779. uint16_t CylinderSkew;
  780. uint8_t flags;
  781. uint8_t reserved[3];
  782. } IPS_SCSI_MODE_PAGE3;
  783. /*
  784. * Sense Data Format - Page 4
  785. */
  786. typedef struct {
  787. uint8_t PageCode;
  788. uint8_t PageLength;
  789. uint16_t CylindersHigh;
  790. uint8_t CylindersLow;
  791. uint8_t Heads;
  792. uint16_t WritePrecompHigh;
  793. uint8_t WritePrecompLow;
  794. uint16_t ReducedWriteCurrentHigh;
  795. uint8_t ReducedWriteCurrentLow;
  796. uint16_t StepRate;
  797. uint16_t LandingZoneHigh;
  798. uint8_t LandingZoneLow;
  799. uint8_t flags;
  800. uint8_t RotationalOffset;
  801. uint8_t Reserved;
  802. uint16_t MediumRotationRate;
  803. uint8_t Reserved2[2];
  804. } IPS_SCSI_MODE_PAGE4;
  805. /*
  806. * Sense Data Format - Page 8
  807. */
  808. typedef struct {
  809. uint8_t PageCode;
  810. uint8_t PageLength;
  811. uint8_t flags;
  812. uint8_t RetentPrio;
  813. uint16_t DisPrefetchLen;
  814. uint16_t MinPrefetchLen;
  815. uint16_t MaxPrefetchLen;
  816. uint16_t MaxPrefetchCeiling;
  817. } IPS_SCSI_MODE_PAGE8;
  818. /*
  819. * Sense Data Format - Block Descriptor (DASD)
  820. */
  821. typedef struct {
  822. uint32_t NumberOfBlocks;
  823. uint8_t DensityCode;
  824. uint16_t BlockLengthHigh;
  825. uint8_t BlockLengthLow;
  826. } IPS_SCSI_MODE_PAGE_BLKDESC;
  827. /*
  828. * Sense Data Format - Mode Page Header
  829. */
  830. typedef struct {
  831. uint8_t DataLength;
  832. uint8_t MediumType;
  833. uint8_t Reserved;
  834. uint8_t BlockDescLength;
  835. } IPS_SCSI_MODE_PAGE_HEADER;
  836. typedef struct {
  837. IPS_SCSI_MODE_PAGE_HEADER hdr;
  838. IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
  839. union {
  840. IPS_SCSI_MODE_PAGE3 pg3;
  841. IPS_SCSI_MODE_PAGE4 pg4;
  842. IPS_SCSI_MODE_PAGE8 pg8;
  843. } pdata;
  844. } IPS_SCSI_MODE_PAGE_DATA;
  845. /*
  846. * Scatter Gather list format
  847. */
  848. typedef struct ips_sglist {
  849. uint32_t address;
  850. uint32_t length;
  851. } IPS_STD_SG_LIST;
  852. typedef struct ips_enh_sglist {
  853. uint32_t address_lo;
  854. uint32_t address_hi;
  855. uint32_t length;
  856. uint32_t reserved;
  857. } IPS_ENH_SG_LIST;
  858. typedef union {
  859. void *list;
  860. IPS_STD_SG_LIST *std_list;
  861. IPS_ENH_SG_LIST *enh_list;
  862. } IPS_SG_LIST;
  863. typedef struct {
  864. char *option_name;
  865. int *option_flag;
  866. int option_value;
  867. } IPS_OPTION;
  868. /*
  869. * Status Info
  870. */
  871. typedef struct ips_stat {
  872. uint32_t residue_len;
  873. void *scb_addr;
  874. uint8_t padding[12 - sizeof(void *)];
  875. } ips_stat_t;
  876. /*
  877. * SCB Queue Format
  878. */
  879. typedef struct ips_scb_queue {
  880. struct ips_scb *head;
  881. struct ips_scb *tail;
  882. int count;
  883. } ips_scb_queue_t;
  884. /*
  885. * Wait queue_format
  886. */
  887. typedef struct ips_wait_queue {
  888. struct scsi_cmnd *head;
  889. struct scsi_cmnd *tail;
  890. int count;
  891. } ips_wait_queue_entry_t;
  892. typedef struct ips_copp_wait_item {
  893. struct scsi_cmnd *scsi_cmd;
  894. struct ips_copp_wait_item *next;
  895. } ips_copp_wait_item_t;
  896. typedef struct ips_copp_queue {
  897. struct ips_copp_wait_item *head;
  898. struct ips_copp_wait_item *tail;
  899. int count;
  900. } ips_copp_queue_t;
  901. /* forward decl for host structure */
  902. struct ips_ha;
  903. typedef struct {
  904. int (*reset)(struct ips_ha *);
  905. int (*issue)(struct ips_ha *, struct ips_scb *);
  906. int (*isinit)(struct ips_ha *);
  907. int (*isintr)(struct ips_ha *);
  908. int (*init)(struct ips_ha *);
  909. int (*erasebios)(struct ips_ha *);
  910. int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
  911. int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
  912. void (*statinit)(struct ips_ha *);
  913. int (*intr)(struct ips_ha *);
  914. void (*enableint)(struct ips_ha *);
  915. uint32_t (*statupd)(struct ips_ha *);
  916. } ips_hw_func_t;
  917. typedef struct ips_ha {
  918. uint8_t ha_id[IPS_MAX_CHANNELS+1];
  919. uint32_t dcdb_active[IPS_MAX_CHANNELS];
  920. uint32_t io_addr; /* Base I/O address */
  921. uint8_t ntargets; /* Number of targets */
  922. uint8_t nbus; /* Number of buses */
  923. uint8_t nlun; /* Number of Luns */
  924. uint16_t ad_type; /* Adapter type */
  925. uint16_t host_num; /* Adapter number */
  926. uint32_t max_xfer; /* Maximum Xfer size */
  927. uint32_t max_cmds; /* Max concurrent commands */
  928. uint32_t num_ioctl; /* Number of Ioctls */
  929. ips_stat_t sp; /* Status packer pointer */
  930. struct ips_scb *scbs; /* Array of all CCBS */
  931. struct ips_scb *scb_freelist; /* SCB free list */
  932. ips_wait_queue_entry_t scb_waitlist; /* Pending SCB list */
  933. ips_copp_queue_t copp_waitlist; /* Pending PT list */
  934. ips_scb_queue_t scb_activelist; /* Active SCB list */
  935. IPS_IO_CMD *dummy; /* dummy command */
  936. IPS_ADAPTER *adapt; /* Adapter status area */
  937. IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */
  938. dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
  939. IPS_ENQ *enq; /* Adapter Enquiry data */
  940. IPS_CONF *conf; /* Adapter config data */
  941. IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
  942. IPS_SUBSYS *subsys; /* Subsystem parameters */
  943. char *ioctl_data; /* IOCTL data area */
  944. uint32_t ioctl_datasize; /* IOCTL data size */
  945. uint32_t cmd_in_progress; /* Current command in progress*/
  946. int flags; /* */
  947. uint8_t waitflag; /* are we waiting for cmd */
  948. uint8_t active;
  949. int ioctl_reset; /* IOCTL Requested Reset Flag */
  950. uint16_t reset_count; /* number of resets */
  951. time64_t last_ffdc; /* last time we sent ffdc info*/
  952. uint8_t slot_num; /* PCI Slot Number */
  953. int ioctl_len; /* size of ioctl buffer */
  954. dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/
  955. uint8_t bios_version[8]; /* BIOS Revision */
  956. uint32_t mem_addr; /* Memory mapped address */
  957. uint32_t io_len; /* Size of IO Address */
  958. uint32_t mem_len; /* Size of memory address */
  959. char __iomem *mem_ptr; /* Memory mapped Ptr */
  960. char __iomem *ioremap_ptr;/* ioremapped memory pointer */
  961. ips_hw_func_t func; /* hw function pointers */
  962. struct pci_dev *pcidev; /* PCI device handle */
  963. char *flash_data; /* Save Area for flash data */
  964. int flash_len; /* length of flash buffer */
  965. u32 flash_datasize; /* Save Area for flash data size */
  966. dma_addr_t flash_busaddr; /* dma address of flash buffer*/
  967. dma_addr_t enq_busaddr; /* dma address of enq struct */
  968. uint8_t requires_esl; /* Requires an EraseStripeLock */
  969. } ips_ha_t;
  970. typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
  971. /*
  972. * SCB Format
  973. */
  974. typedef struct ips_scb {
  975. IPS_HOST_COMMAND cmd;
  976. IPS_DCDB_TABLE dcdb;
  977. uint8_t target_id;
  978. uint8_t bus;
  979. uint8_t lun;
  980. uint8_t cdb[12];
  981. uint32_t scb_busaddr;
  982. uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility
  983. uint32_t timeout;
  984. uint8_t basic_status;
  985. uint8_t extended_status;
  986. uint8_t breakup;
  987. uint8_t sg_break;
  988. uint32_t data_len;
  989. uint32_t sg_len;
  990. uint32_t flags;
  991. uint32_t op_code;
  992. IPS_SG_LIST sg_list;
  993. struct scsi_cmnd *scsi_cmd;
  994. struct ips_scb *q_next;
  995. ips_scb_callback callback;
  996. uint32_t sg_busaddr;
  997. int sg_count;
  998. dma_addr_t data_busaddr;
  999. } ips_scb_t;
  1000. typedef struct ips_scb_pt {
  1001. IPS_HOST_COMMAND cmd;
  1002. IPS_DCDB_TABLE dcdb;
  1003. uint8_t target_id;
  1004. uint8_t bus;
  1005. uint8_t lun;
  1006. uint8_t cdb[12];
  1007. uint32_t scb_busaddr;
  1008. uint32_t data_busaddr;
  1009. uint32_t timeout;
  1010. uint8_t basic_status;
  1011. uint8_t extended_status;
  1012. uint16_t breakup;
  1013. uint32_t data_len;
  1014. uint32_t sg_len;
  1015. uint32_t flags;
  1016. uint32_t op_code;
  1017. IPS_SG_LIST *sg_list;
  1018. struct scsi_cmnd *scsi_cmd;
  1019. struct ips_scb *q_next;
  1020. ips_scb_callback callback;
  1021. } ips_scb_pt_t;
  1022. /*
  1023. * Passthru Command Format
  1024. */
  1025. typedef struct {
  1026. uint8_t CoppID[4];
  1027. uint32_t CoppCmd;
  1028. uint32_t PtBuffer;
  1029. uint8_t *CmdBuffer;
  1030. uint32_t CmdBSize;
  1031. ips_scb_pt_t CoppCP;
  1032. uint32_t TimeOut;
  1033. uint8_t BasicStatus;
  1034. uint8_t ExtendedStatus;
  1035. uint8_t AdapterType;
  1036. uint8_t reserved;
  1037. } ips_passthru_t;
  1038. #endif
  1039. /* The Version Information below gets created by SED during the build process. */
  1040. /* Do not modify the next line; it's what SED is looking for to do the insert. */
  1041. /* Version Info */
  1042. /*************************************************************************
  1043. *
  1044. * VERSION.H -- version numbers and copyright notices in various formats
  1045. *
  1046. *************************************************************************/
  1047. #define IPS_VER_MAJOR 7
  1048. #define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
  1049. #define IPS_VER_MINOR 12
  1050. #define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
  1051. #define IPS_VER_BUILD 05
  1052. #define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
  1053. #define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
  1054. IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
  1055. #define IPS_RELEASE_ID 0x00020000
  1056. #define IPS_BUILD_IDENT 761
  1057. #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
  1058. #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
  1059. #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
  1060. #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
  1061. /* Version numbers for various adapters */
  1062. #define IPS_VER_SERVERAID1 "2.25.01"
  1063. #define IPS_VER_SERVERAID2 "2.88.13"
  1064. #define IPS_VER_NAVAJO "2.88.13"
  1065. #define IPS_VER_SERVERAID3 "6.10.24"
  1066. #define IPS_VER_SERVERAID4H "7.12.02"
  1067. #define IPS_VER_SERVERAID4MLx "7.12.02"
  1068. #define IPS_VER_SARASOTA "7.12.02"
  1069. #define IPS_VER_MARCO "7.12.02"
  1070. #define IPS_VER_SEBRING "7.12.02"
  1071. #define IPS_VER_KEYWEST "7.12.02"
  1072. /* Compatibility IDs for various adapters */
  1073. #define IPS_COMPAT_UNKNOWN ""
  1074. #define IPS_COMPAT_CURRENT "KW710"
  1075. #define IPS_COMPAT_SERVERAID1 "2.25.01"
  1076. #define IPS_COMPAT_SERVERAID2 "2.88.13"
  1077. #define IPS_COMPAT_NAVAJO "2.88.13"
  1078. #define IPS_COMPAT_KIOWA "2.88.13"
  1079. #define IPS_COMPAT_SERVERAID3H "SB610"
  1080. #define IPS_COMPAT_SERVERAID3L "SB610"
  1081. #define IPS_COMPAT_SERVERAID4H "KW710"
  1082. #define IPS_COMPAT_SERVERAID4M "KW710"
  1083. #define IPS_COMPAT_SERVERAID4L "KW710"
  1084. #define IPS_COMPAT_SERVERAID4Mx "KW710"
  1085. #define IPS_COMPAT_SERVERAID4Lx "KW710"
  1086. #define IPS_COMPAT_SARASOTA "KW710"
  1087. #define IPS_COMPAT_MARCO "KW710"
  1088. #define IPS_COMPAT_SEBRING "KW710"
  1089. #define IPS_COMPAT_TAMPA "KW710"
  1090. #define IPS_COMPAT_KEYWEST "KW710"
  1091. #define IPS_COMPAT_BIOS "KW710"
  1092. #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
  1093. #define IPS_COMPAT_ID_LENGTH 8
  1094. #define IPS_DEFINE_COMPAT_TABLE(tablename) \
  1095. char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
  1096. IPS_COMPAT_UNKNOWN, \
  1097. IPS_COMPAT_SERVERAID1, \
  1098. IPS_COMPAT_SERVERAID2, \
  1099. IPS_COMPAT_NAVAJO, \
  1100. IPS_COMPAT_KIOWA, \
  1101. IPS_COMPAT_SERVERAID3H, \
  1102. IPS_COMPAT_SERVERAID3L, \
  1103. IPS_COMPAT_SERVERAID4H, \
  1104. IPS_COMPAT_SERVERAID4M, \
  1105. IPS_COMPAT_SERVERAID4L, \
  1106. IPS_COMPAT_SERVERAID4Mx, \
  1107. IPS_COMPAT_SERVERAID4Lx, \
  1108. IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
  1109. IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
  1110. IPS_COMPAT_MARCO, \
  1111. IPS_COMPAT_SEBRING, \
  1112. IPS_COMPAT_TAMPA, \
  1113. IPS_COMPAT_KEYWEST \
  1114. }
  1115. /*
  1116. * Overrides for Emacs so that we almost follow Linus's tabbing style.
  1117. * Emacs will notice this stuff at the end of the file and automatically
  1118. * adjust the settings for this buffer only. This must remain at the end
  1119. * of the file.
  1120. * ---------------------------------------------------------------------------
  1121. * Local variables:
  1122. * c-indent-level: 2
  1123. * c-brace-imaginary-offset: 0
  1124. * c-brace-offset: -2
  1125. * c-argdecl-indent: 2
  1126. * c-label-offset: -2
  1127. * c-continued-statement-offset: 2
  1128. * c-continued-brace-offset: 0
  1129. * indent-tabs-mode: nil
  1130. * tab-width: 8
  1131. * End:
  1132. */