hpsa_cmd.h 28 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
  4. * Copyright 2016 Microsemi Corporation
  5. * Copyright 2014-2015 PMC-Sierra, Inc.
  6. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  15. * NON INFRINGEMENT. See the GNU General Public License for more details.
  16. *
  17. * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  18. *
  19. */
  20. #ifndef HPSA_CMD_H
  21. #define HPSA_CMD_H
  22. /* general boundary defintions */
  23. #define SENSEINFOBYTES 32 /* may vary between hbas */
  24. #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
  25. #define HPSA_SG_CHAIN 0x80000000
  26. #define HPSA_SG_LAST 0x40000000
  27. #define MAXREPLYQS 256
  28. /* Command Status value */
  29. #define CMD_SUCCESS 0x0000
  30. #define CMD_TARGET_STATUS 0x0001
  31. #define CMD_DATA_UNDERRUN 0x0002
  32. #define CMD_DATA_OVERRUN 0x0003
  33. #define CMD_INVALID 0x0004
  34. #define CMD_PROTOCOL_ERR 0x0005
  35. #define CMD_HARDWARE_ERR 0x0006
  36. #define CMD_CONNECTION_LOST 0x0007
  37. #define CMD_ABORTED 0x0008
  38. #define CMD_ABORT_FAILED 0x0009
  39. #define CMD_UNSOLICITED_ABORT 0x000A
  40. #define CMD_TIMEOUT 0x000B
  41. #define CMD_UNABORTABLE 0x000C
  42. #define CMD_TMF_STATUS 0x000D
  43. #define CMD_IOACCEL_DISABLED 0x000E
  44. #define CMD_CTLR_LOCKUP 0xffff
  45. /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
  46. * it is a value defined by the driver that commands can be marked
  47. * with when a controller lockup has been detected by the driver
  48. */
  49. /* TMF function status values */
  50. #define CISS_TMF_COMPLETE 0x00
  51. #define CISS_TMF_INVALID_FRAME 0x02
  52. #define CISS_TMF_NOT_SUPPORTED 0x04
  53. #define CISS_TMF_FAILED 0x05
  54. #define CISS_TMF_SUCCESS 0x08
  55. #define CISS_TMF_WRONG_LUN 0x09
  56. #define CISS_TMF_OVERLAPPED_TAG 0x0a
  57. /* Unit Attentions ASC's as defined for the MSA2012sa */
  58. #define POWER_OR_RESET 0x29
  59. #define STATE_CHANGED 0x2a
  60. #define UNIT_ATTENTION_CLEARED 0x2f
  61. #define LUN_FAILED 0x3e
  62. #define REPORT_LUNS_CHANGED 0x3f
  63. /* Unit Attentions ASCQ's as defined for the MSA2012sa */
  64. /* These ASCQ's defined for ASC = POWER_OR_RESET */
  65. #define POWER_ON_RESET 0x00
  66. #define POWER_ON_REBOOT 0x01
  67. #define SCSI_BUS_RESET 0x02
  68. #define MSA_TARGET_RESET 0x03
  69. #define CONTROLLER_FAILOVER 0x04
  70. #define TRANSCEIVER_SE 0x05
  71. #define TRANSCEIVER_LVD 0x06
  72. /* These ASCQ's defined for ASC = STATE_CHANGED */
  73. #define RESERVATION_PREEMPTED 0x03
  74. #define ASYM_ACCESS_CHANGED 0x06
  75. #define LUN_CAPACITY_CHANGED 0x09
  76. /* transfer direction */
  77. #define XFER_NONE 0x00
  78. #define XFER_WRITE 0x01
  79. #define XFER_READ 0x02
  80. #define XFER_RSVD 0x03
  81. /* task attribute */
  82. #define ATTR_UNTAGGED 0x00
  83. #define ATTR_SIMPLE 0x04
  84. #define ATTR_HEADOFQUEUE 0x05
  85. #define ATTR_ORDERED 0x06
  86. #define ATTR_ACA 0x07
  87. /* cdb type */
  88. #define TYPE_CMD 0x00
  89. #define TYPE_MSG 0x01
  90. #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */
  91. /* Message Types */
  92. #define HPSA_TASK_MANAGEMENT 0x00
  93. #define HPSA_RESET 0x01
  94. #define HPSA_SCAN 0x02
  95. #define HPSA_NOOP 0x03
  96. #define HPSA_CTLR_RESET_TYPE 0x00
  97. #define HPSA_BUS_RESET_TYPE 0x01
  98. #define HPSA_TARGET_RESET_TYPE 0x03
  99. #define HPSA_LUN_RESET_TYPE 0x04
  100. #define HPSA_NEXUS_RESET_TYPE 0x05
  101. /* Task Management Functions */
  102. #define HPSA_TMF_ABORT_TASK 0x00
  103. #define HPSA_TMF_ABORT_TASK_SET 0x01
  104. #define HPSA_TMF_CLEAR_ACA 0x02
  105. #define HPSA_TMF_CLEAR_TASK_SET 0x03
  106. #define HPSA_TMF_QUERY_TASK 0x04
  107. #define HPSA_TMF_QUERY_TASK_SET 0x05
  108. #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
  109. /* config space register offsets */
  110. #define CFG_VENDORID 0x00
  111. #define CFG_DEVICEID 0x02
  112. #define CFG_I2OBAR 0x10
  113. #define CFG_MEM1BAR 0x14
  114. /* i2o space register offsets */
  115. #define I2O_IBDB_SET 0x20
  116. #define I2O_IBDB_CLEAR 0x70
  117. #define I2O_INT_STATUS 0x30
  118. #define I2O_INT_MASK 0x34
  119. #define I2O_IBPOST_Q 0x40
  120. #define I2O_OBPOST_Q 0x44
  121. #define I2O_DMA1_CFG 0x214
  122. /* Configuration Table */
  123. #define CFGTBL_ChangeReq 0x00000001l
  124. #define CFGTBL_AccCmds 0x00000001l
  125. #define DOORBELL_CTLR_RESET 0x00000004l
  126. #define DOORBELL_CTLR_RESET2 0x00000020l
  127. #define DOORBELL_CLEAR_EVENTS 0x00000040l
  128. #define DOORBELL_GENERATE_CHKPT 0x00000080l
  129. #define CFGTBL_Trans_Simple 0x00000002l
  130. #define CFGTBL_Trans_Performant 0x00000004l
  131. #define CFGTBL_Trans_io_accel1 0x00000080l
  132. #define CFGTBL_Trans_io_accel2 0x00000100l
  133. #define CFGTBL_Trans_use_short_tags 0x20000000l
  134. #define CFGTBL_Trans_enable_directed_msix (1 << 30)
  135. #define CFGTBL_BusType_Ultra2 0x00000001l
  136. #define CFGTBL_BusType_Ultra3 0x00000002l
  137. #define CFGTBL_BusType_Fibre1G 0x00000100l
  138. #define CFGTBL_BusType_Fibre2G 0x00000200l
  139. /* VPD Inquiry types */
  140. #define HPSA_INQUIRY_FAILED 0x02
  141. #define HPSA_VPD_SUPPORTED_PAGES 0x00
  142. #define HPSA_VPD_LV_DEVICE_ID 0x83
  143. #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
  144. #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
  145. #define HPSA_VPD_LV_STATUS 0xC3
  146. #define HPSA_VPD_HEADER_SZ 4
  147. /* Logical volume states */
  148. #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff
  149. #define HPSA_LV_OK 0x0
  150. #define HPSA_LV_FAILED 0x01
  151. #define HPSA_LV_NOT_AVAILABLE 0x0b
  152. #define HPSA_LV_UNDERGOING_ERASE 0x0F
  153. #define HPSA_LV_UNDERGOING_RPI 0x12
  154. #define HPSA_LV_PENDING_RPI 0x13
  155. #define HPSA_LV_ENCRYPTED_NO_KEY 0x14
  156. #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
  157. #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16
  158. #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
  159. #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
  160. #define HPSA_LV_PENDING_ENCRYPTION 0x19
  161. #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A
  162. struct vals32 {
  163. u32 lower;
  164. u32 upper;
  165. };
  166. union u64bit {
  167. struct vals32 val32;
  168. u64 val;
  169. };
  170. /* FIXME this is a per controller value (barf!) */
  171. #define HPSA_MAX_LUN 1024
  172. #define HPSA_MAX_PHYS_LUN 1024
  173. #define MAX_EXT_TARGETS 32
  174. #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
  175. MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
  176. /* SCSI-3 Commands */
  177. #pragma pack(1)
  178. #define HPSA_INQUIRY 0x12
  179. struct InquiryData {
  180. u8 data_byte[36];
  181. };
  182. #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
  183. #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
  184. #define HPSA_REPORT_PHYS_EXTENDED 0x02
  185. #define HPSA_CISS_READ 0xc0 /* CISS Read */
  186. #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
  187. #define RAID_MAP_MAX_ENTRIES 256
  188. struct raid_map_disk_data {
  189. u32 ioaccel_handle; /**< Handle to access this disk via the
  190. * I/O accelerator */
  191. u8 xor_mult[2]; /**< XOR multipliers for this position,
  192. * valid for data disks only */
  193. u8 reserved[2];
  194. };
  195. struct raid_map_data {
  196. __le32 structure_size; /* Size of entire structure in bytes */
  197. __le32 volume_blk_size; /* bytes / block in the volume */
  198. __le64 volume_blk_cnt; /* logical blocks on the volume */
  199. u8 phys_blk_shift; /* Shift factor to convert between
  200. * units of logical blocks and physical
  201. * disk blocks */
  202. u8 parity_rotation_shift; /* Shift factor to convert between units
  203. * of logical stripes and physical
  204. * stripes */
  205. __le16 strip_size; /* blocks used on each disk / stripe */
  206. __le64 disk_starting_blk; /* First disk block used in volume */
  207. __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
  208. __le16 data_disks_per_row; /* data disk entries / row in the map */
  209. __le16 metadata_disks_per_row;/* mirror/parity disk entries / row
  210. * in the map */
  211. __le16 row_cnt; /* rows in each layout map */
  212. __le16 layout_map_count; /* layout maps (1 map per mirror/parity
  213. * group) */
  214. __le16 flags; /* Bit 0 set if encryption enabled */
  215. #define RAID_MAP_FLAG_ENCRYPT_ON 0x01
  216. __le16 dekindex; /* Data encryption key index. */
  217. u8 reserved[16];
  218. struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
  219. };
  220. struct ReportLUNdata {
  221. u8 LUNListLength[4];
  222. u8 extended_response_flag;
  223. u8 reserved[3];
  224. u8 LUN[HPSA_MAX_LUN][8];
  225. };
  226. struct ext_report_lun_entry {
  227. u8 lunid[8];
  228. #define MASKED_DEVICE(x) ((x)[3] & 0xC0)
  229. #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
  230. #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
  231. #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
  232. GET_BMIC_LEVEL_TWO_TARGET((lunid)))
  233. u8 wwid[8];
  234. u8 device_type;
  235. u8 device_flags;
  236. u8 lun_count; /* multi-lun device, how many luns */
  237. u8 redundant_paths;
  238. u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
  239. };
  240. struct ReportExtendedLUNdata {
  241. u8 LUNListLength[4];
  242. u8 extended_response_flag;
  243. u8 reserved[3];
  244. struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
  245. };
  246. struct SenseSubsystem_info {
  247. u8 reserved[36];
  248. u8 portname[8];
  249. u8 reserved1[1108];
  250. };
  251. /* BMIC commands */
  252. #define BMIC_READ 0x26
  253. #define BMIC_WRITE 0x27
  254. #define BMIC_CACHE_FLUSH 0xc2
  255. #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
  256. #define BMIC_FLASH_FIRMWARE 0xF7
  257. #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
  258. #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
  259. #define BMIC_IDENTIFY_CONTROLLER 0x11
  260. #define BMIC_SET_DIAG_OPTIONS 0xF4
  261. #define BMIC_SENSE_DIAG_OPTIONS 0xF5
  262. #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000
  263. #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
  264. #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65
  265. /* Command List Structure */
  266. union SCSI3Addr {
  267. struct {
  268. u8 Dev;
  269. u8 Bus:6;
  270. u8 Mode:2; /* b00 */
  271. } PeripDev;
  272. struct {
  273. u8 DevLSB;
  274. u8 DevMSB:6;
  275. u8 Mode:2; /* b01 */
  276. } LogDev;
  277. struct {
  278. u8 Dev:5;
  279. u8 Bus:3;
  280. u8 Targ:6;
  281. u8 Mode:2; /* b10 */
  282. } LogUnit;
  283. };
  284. struct PhysDevAddr {
  285. u32 TargetId:24;
  286. u32 Bus:6;
  287. u32 Mode:2;
  288. /* 2 level target device addr */
  289. union SCSI3Addr Target[2];
  290. };
  291. struct LogDevAddr {
  292. u32 VolId:30;
  293. u32 Mode:2;
  294. u8 reserved[4];
  295. };
  296. union LUNAddr {
  297. u8 LunAddrBytes[8];
  298. union SCSI3Addr SCSI3Lun[4];
  299. struct PhysDevAddr PhysDev;
  300. struct LogDevAddr LogDev;
  301. };
  302. struct CommandListHeader {
  303. u8 ReplyQueue;
  304. u8 SGList;
  305. __le16 SGTotal;
  306. __le64 tag;
  307. union LUNAddr LUN;
  308. };
  309. struct RequestBlock {
  310. u8 CDBLen;
  311. /*
  312. * type_attr_dir:
  313. * type: low 3 bits
  314. * attr: middle 3 bits
  315. * dir: high 2 bits
  316. */
  317. u8 type_attr_dir;
  318. #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
  319. (((a) & 0x07) << 3) |\
  320. ((t) & 0x07))
  321. #define GET_TYPE(tad) ((tad) & 0x07)
  322. #define GET_ATTR(tad) (((tad) >> 3) & 0x07)
  323. #define GET_DIR(tad) (((tad) >> 6) & 0x03)
  324. u16 Timeout;
  325. u8 CDB[16];
  326. };
  327. struct ErrDescriptor {
  328. __le64 Addr;
  329. __le32 Len;
  330. };
  331. struct SGDescriptor {
  332. __le64 Addr;
  333. __le32 Len;
  334. __le32 Ext;
  335. };
  336. union MoreErrInfo {
  337. struct {
  338. u8 Reserved[3];
  339. u8 Type;
  340. u32 ErrorInfo;
  341. } Common_Info;
  342. struct {
  343. u8 Reserved[2];
  344. u8 offense_size; /* size of offending entry */
  345. u8 offense_num; /* byte # of offense 0-base */
  346. u32 offense_value;
  347. } Invalid_Cmd;
  348. };
  349. struct ErrorInfo {
  350. u8 ScsiStatus;
  351. u8 SenseLen;
  352. u16 CommandStatus;
  353. u32 ResidualCnt;
  354. union MoreErrInfo MoreErrInfo;
  355. u8 SenseInfo[SENSEINFOBYTES];
  356. };
  357. /* Command types */
  358. #define CMD_IOCTL_PEND 0x01
  359. #define CMD_SCSI 0x03
  360. #define CMD_IOACCEL1 0x04
  361. #define CMD_IOACCEL2 0x05
  362. #define IOACCEL2_TMF 0x06
  363. #define DIRECT_LOOKUP_SHIFT 4
  364. #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
  365. #define HPSA_ERROR_BIT 0x02
  366. struct ctlr_info; /* defined in hpsa.h */
  367. /* The size of this structure needs to be divisible by 128
  368. * on all architectures. The low 4 bits of the addresses
  369. * are used as follows:
  370. *
  371. * bit 0: to device, used to indicate "performant mode" command
  372. * from device, indidcates error status.
  373. * bit 1-3: to device, indicates block fetch table entry for
  374. * reducing DMA in fetching commands from host memory.
  375. */
  376. #define COMMANDLIST_ALIGNMENT 128
  377. struct CommandList {
  378. struct CommandListHeader Header;
  379. struct RequestBlock Request;
  380. struct ErrDescriptor ErrDesc;
  381. struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
  382. /* information associated with the command */
  383. u32 busaddr; /* physical addr of this record */
  384. struct ErrorInfo *err_info; /* pointer to the allocated mem */
  385. struct ctlr_info *h;
  386. int cmd_type;
  387. long cmdindex;
  388. struct completion *waiting;
  389. struct scsi_cmnd *scsi_cmd;
  390. struct work_struct work;
  391. /*
  392. * For commands using either of the two "ioaccel" paths to
  393. * bypass the RAID stack and go directly to the physical disk
  394. * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
  395. * i/o is destined. We need to store that here because the command
  396. * may potentially encounter TASK SET FULL and need to be resubmitted
  397. * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
  398. * not used.
  399. */
  400. struct hpsa_scsi_dev_t *phys_disk;
  401. int abort_pending;
  402. struct hpsa_scsi_dev_t *device;
  403. atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
  404. } __aligned(COMMANDLIST_ALIGNMENT);
  405. /* Max S/G elements in I/O accelerator command */
  406. #define IOACCEL1_MAXSGENTRIES 24
  407. #define IOACCEL2_MAXSGENTRIES 28
  408. /*
  409. * Structure for I/O accelerator (mode 1) commands.
  410. * Note that this structure must be 128-byte aligned in size.
  411. */
  412. #define IOACCEL1_COMMANDLIST_ALIGNMENT 128
  413. struct io_accel1_cmd {
  414. __le16 dev_handle; /* 0x00 - 0x01 */
  415. u8 reserved1; /* 0x02 */
  416. u8 function; /* 0x03 */
  417. u8 reserved2[8]; /* 0x04 - 0x0B */
  418. u32 err_info; /* 0x0C - 0x0F */
  419. u8 reserved3[2]; /* 0x10 - 0x11 */
  420. u8 err_info_len; /* 0x12 */
  421. u8 reserved4; /* 0x13 */
  422. u8 sgl_offset; /* 0x14 */
  423. u8 reserved5[7]; /* 0x15 - 0x1B */
  424. __le32 transfer_len; /* 0x1C - 0x1F */
  425. u8 reserved6[4]; /* 0x20 - 0x23 */
  426. __le16 io_flags; /* 0x24 - 0x25 */
  427. u8 reserved7[14]; /* 0x26 - 0x33 */
  428. u8 LUN[8]; /* 0x34 - 0x3B */
  429. __le32 control; /* 0x3C - 0x3F */
  430. u8 CDB[16]; /* 0x40 - 0x4F */
  431. u8 reserved8[16]; /* 0x50 - 0x5F */
  432. __le16 host_context_flags; /* 0x60 - 0x61 */
  433. __le16 timeout_sec; /* 0x62 - 0x63 */
  434. u8 ReplyQueue; /* 0x64 */
  435. u8 reserved9[3]; /* 0x65 - 0x67 */
  436. __le64 tag; /* 0x68 - 0x6F */
  437. __le64 host_addr; /* 0x70 - 0x77 */
  438. u8 CISS_LUN[8]; /* 0x78 - 0x7F */
  439. struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
  440. } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
  441. #define IOACCEL1_FUNCTION_SCSIIO 0x00
  442. #define IOACCEL1_SGLOFFSET 32
  443. #define IOACCEL1_IOFLAGS_IO_REQ 0x4000
  444. #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
  445. #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
  446. #define IOACCEL1_CONTROL_NODATAXFER 0x00000000
  447. #define IOACCEL1_CONTROL_DATA_OUT 0x01000000
  448. #define IOACCEL1_CONTROL_DATA_IN 0x02000000
  449. #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
  450. #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
  451. #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
  452. #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
  453. #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
  454. #define IOACCEL1_CONTROL_ACA 0x00000400
  455. #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
  456. #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
  457. struct ioaccel2_sg_element {
  458. __le64 address;
  459. __le32 length;
  460. u8 reserved[3];
  461. u8 chain_indicator;
  462. #define IOACCEL2_CHAIN 0x80
  463. #define IOACCEL2_LAST_SG 0x40
  464. };
  465. /*
  466. * SCSI Response Format structure for IO Accelerator Mode 2
  467. */
  468. struct io_accel2_scsi_response {
  469. u8 IU_type;
  470. #define IOACCEL2_IU_TYPE_SRF 0x60
  471. u8 reserved1[3];
  472. u8 req_id[4]; /* request identifier */
  473. u8 reserved2[4];
  474. u8 serv_response; /* service response */
  475. #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
  476. #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
  477. #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
  478. #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
  479. #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
  480. #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
  481. u8 status; /* status */
  482. #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
  483. #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
  484. #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
  485. #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
  486. #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
  487. #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
  488. #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
  489. #define IOACCEL2_STATUS_SR_IO_ERROR 0x01
  490. #define IOACCEL2_STATUS_SR_IO_ABORTED 0x02
  491. #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03
  492. #define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04
  493. #define IOACCEL2_STATUS_SR_UNDERRUN 0x51
  494. #define IOACCEL2_STATUS_SR_OVERRUN 0x75
  495. u8 data_present; /* low 2 bits */
  496. #define IOACCEL2_NO_DATAPRESENT 0x000
  497. #define IOACCEL2_RESPONSE_DATAPRESENT 0x001
  498. #define IOACCEL2_SENSE_DATA_PRESENT 0x002
  499. #define IOACCEL2_RESERVED 0x003
  500. u8 sense_data_len; /* sense/response data length */
  501. u8 resid_cnt[4]; /* residual count */
  502. u8 sense_data_buff[32]; /* sense/response data buffer */
  503. };
  504. /*
  505. * Structure for I/O accelerator (mode 2 or m2) commands.
  506. * Note that this structure must be 128-byte aligned in size.
  507. */
  508. #define IOACCEL2_COMMANDLIST_ALIGNMENT 128
  509. struct io_accel2_cmd {
  510. u8 IU_type; /* IU Type */
  511. u8 direction; /* direction, memtype, and encryption */
  512. #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */
  513. #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
  514. /* 0b=PCIe, 1b=DDR */
  515. #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
  516. /* 0=off, 1=on */
  517. u8 reply_queue; /* Reply Queue ID */
  518. u8 reserved1; /* Reserved */
  519. __le32 scsi_nexus; /* Device Handle */
  520. __le32 Tag; /* cciss tag, lower 4 bytes only */
  521. __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */
  522. u8 cdb[16]; /* SCSI Command Descriptor Block */
  523. u8 cciss_lun[8]; /* 8 byte SCSI address */
  524. __le32 data_len; /* Total bytes to transfer */
  525. u8 cmd_priority_task_attr; /* priority and task attrs */
  526. #define IOACCEL2_PRIORITY_MASK 0x78
  527. #define IOACCEL2_ATTR_MASK 0x07
  528. u8 sg_count; /* Number of sg elements */
  529. __le16 dekindex; /* Data encryption key index */
  530. __le64 err_ptr; /* Error Pointer */
  531. __le32 err_len; /* Error Length*/
  532. __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */
  533. struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
  534. struct io_accel2_scsi_response error_data;
  535. } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
  536. /*
  537. * defines for Mode 2 command struct
  538. * FIXME: this can't be all I need mfm
  539. */
  540. #define IOACCEL2_IU_TYPE 0x40
  541. #define IOACCEL2_IU_TMF_TYPE 0x41
  542. #define IOACCEL2_DIR_NO_DATA 0x00
  543. #define IOACCEL2_DIR_DATA_IN 0x01
  544. #define IOACCEL2_DIR_DATA_OUT 0x02
  545. #define IOACCEL2_TMF_ABORT 0x01
  546. /*
  547. * SCSI Task Management Request format for Accelerator Mode 2
  548. */
  549. struct hpsa_tmf_struct {
  550. u8 iu_type; /* Information Unit Type */
  551. u8 reply_queue; /* Reply Queue ID */
  552. u8 tmf; /* Task Management Function */
  553. u8 reserved1; /* byte 3 Reserved */
  554. __le32 it_nexus; /* SCSI I-T Nexus */
  555. u8 lun_id[8]; /* LUN ID for TMF request */
  556. __le64 tag; /* cciss tag associated w/ request */
  557. __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */
  558. __le64 error_ptr; /* Error Pointer */
  559. __le32 error_len; /* Error Length */
  560. } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
  561. /* Configuration Table Structure */
  562. struct HostWrite {
  563. __le32 TransportRequest;
  564. __le32 command_pool_addr_hi;
  565. __le32 CoalIntDelay;
  566. __le32 CoalIntCount;
  567. };
  568. #define SIMPLE_MODE 0x02
  569. #define PERFORMANT_MODE 0x04
  570. #define MEMQ_MODE 0x08
  571. #define IOACCEL_MODE_1 0x80
  572. #define DRIVER_SUPPORT_UA_ENABLE 0x00000001
  573. struct CfgTable {
  574. u8 Signature[4];
  575. __le32 SpecValence;
  576. __le32 TransportSupport;
  577. __le32 TransportActive;
  578. struct HostWrite HostWrite;
  579. __le32 CmdsOutMax;
  580. __le32 BusTypes;
  581. __le32 TransMethodOffset;
  582. u8 ServerName[16];
  583. __le32 HeartBeat;
  584. __le32 driver_support;
  585. #define ENABLE_SCSI_PREFETCH 0x100
  586. #define ENABLE_UNIT_ATTN 0x01
  587. __le32 MaxScatterGatherElements;
  588. __le32 MaxLogicalUnits;
  589. __le32 MaxPhysicalDevices;
  590. __le32 MaxPhysicalDrivesPerLogicalUnit;
  591. __le32 MaxPerformantModeCommands;
  592. __le32 MaxBlockFetch;
  593. __le32 PowerConservationSupport;
  594. __le32 PowerConservationEnable;
  595. __le32 TMFSupportFlags;
  596. u8 TMFTagMask[8];
  597. u8 reserved[0x78 - 0x70];
  598. __le32 misc_fw_support; /* offset 0x78 */
  599. #define MISC_FW_DOORBELL_RESET 0x02
  600. #define MISC_FW_DOORBELL_RESET2 0x010
  601. #define MISC_FW_RAID_OFFLOAD_BASIC 0x020
  602. #define MISC_FW_EVENT_NOTIFY 0x080
  603. u8 driver_version[32];
  604. __le32 max_cached_write_size;
  605. u8 driver_scratchpad[16];
  606. __le32 max_error_info_length;
  607. __le32 io_accel_max_embedded_sg_count;
  608. __le32 io_accel_request_size_offset;
  609. __le32 event_notify;
  610. #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
  611. #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
  612. __le32 clear_event_notify;
  613. };
  614. #define NUM_BLOCKFETCH_ENTRIES 8
  615. struct TransTable_struct {
  616. __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
  617. __le32 RepQSize;
  618. __le32 RepQCount;
  619. __le32 RepQCtrAddrLow32;
  620. __le32 RepQCtrAddrHigh32;
  621. #define MAX_REPLY_QUEUES 64
  622. struct vals32 RepQAddr[MAX_REPLY_QUEUES];
  623. };
  624. struct hpsa_pci_info {
  625. unsigned char bus;
  626. unsigned char dev_fn;
  627. unsigned short domain;
  628. u32 board_id;
  629. };
  630. struct bmic_identify_controller {
  631. u8 configured_logical_drive_count; /* offset 0 */
  632. u8 pad1[153];
  633. __le16 extended_logical_unit_count; /* offset 154 */
  634. u8 pad2[136];
  635. u8 controller_mode; /* offset 292 */
  636. u8 pad3[32];
  637. };
  638. struct bmic_identify_physical_device {
  639. u8 scsi_bus; /* SCSI Bus number on controller */
  640. u8 scsi_id; /* SCSI ID on this bus */
  641. __le16 block_size; /* sector size in bytes */
  642. __le32 total_blocks; /* number for sectors on drive */
  643. __le32 reserved_blocks; /* controller reserved (RIS) */
  644. u8 model[40]; /* Physical Drive Model */
  645. u8 serial_number[40]; /* Drive Serial Number */
  646. u8 firmware_revision[8]; /* drive firmware revision */
  647. u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
  648. u8 compaq_drive_stamp; /* 0 means drive not stamped */
  649. u8 last_failure_reason;
  650. #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01
  651. #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02
  652. #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03
  653. #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04
  654. #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05
  655. #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06
  656. #define BMIC_LAST_FAILURE_TIMEOUT 0x07
  657. #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08
  658. #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09
  659. #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a
  660. #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b
  661. #define BMIC_LAST_FAILURE_NOT_READY 0x0c
  662. #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d
  663. #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e
  664. #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f
  665. #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10
  666. #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11
  667. #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12
  668. #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13
  669. #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14
  670. #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15
  671. #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16
  672. #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17
  673. #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18
  674. #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19
  675. #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a
  676. #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b
  677. #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c
  678. #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d
  679. #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e
  680. #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f
  681. #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20
  682. #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21
  683. #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22
  684. #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23
  685. #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24
  686. #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25
  687. #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26
  688. #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27
  689. #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28
  690. #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29
  691. #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a
  692. #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b
  693. #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37
  694. #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38
  695. #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40
  696. #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41
  697. #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42
  698. #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80
  699. #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81
  700. #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82
  701. #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83
  702. u8 flags;
  703. u8 more_flags;
  704. u8 scsi_lun; /* SCSI LUN for phys drive */
  705. u8 yet_more_flags;
  706. u8 even_more_flags;
  707. __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
  708. u8 phys_connector[2]; /* connector number on controller */
  709. u8 phys_box_on_bus; /* phys enclosure this drive resides */
  710. u8 phys_bay_in_box; /* phys drv bay this drive resides */
  711. __le32 rpm; /* Drive rotational speed in rpm */
  712. u8 device_type; /* type of drive */
  713. #define BMIC_DEVICE_TYPE_CONTROLLER 0x07
  714. u8 sata_version; /* only valid when drive_type is SATA */
  715. __le64 big_total_block_count;
  716. __le64 ris_starting_lba;
  717. __le32 ris_size;
  718. u8 wwid[20];
  719. u8 controller_phy_map[32];
  720. __le16 phy_count;
  721. u8 phy_connected_dev_type[256];
  722. u8 phy_to_drive_bay_num[256];
  723. __le16 phy_to_attached_dev_index[256];
  724. u8 box_index;
  725. u8 reserved;
  726. __le16 extra_physical_drive_flags;
  727. #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
  728. (idphydrv->extra_physical_drive_flags & (1 << 10))
  729. u8 negotiated_link_rate[256];
  730. u8 phy_to_phy_map[256];
  731. u8 redundant_path_present_map;
  732. u8 redundant_path_failure_map;
  733. u8 active_path_number;
  734. __le16 alternate_paths_phys_connector[8];
  735. u8 alternate_paths_phys_box_on_port[8];
  736. u8 multi_lun_device_lun_count;
  737. u8 minimum_good_fw_revision[8];
  738. u8 unique_inquiry_bytes[20];
  739. u8 current_temperature_degreesC;
  740. u8 temperature_threshold_degreesC;
  741. u8 max_temperature_degreesC;
  742. u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
  743. __le16 current_queue_depth_limit;
  744. u8 reserved_switch_stuff[60];
  745. __le16 power_on_hours; /* valid only if gas gauge supported */
  746. __le16 percent_endurance_used; /* valid only if gas gauge supported. */
  747. #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
  748. ((idphydrv->percent_endurance_used & 0x80) || \
  749. (idphydrv->percent_endurance_used > 10000))
  750. u8 drive_authentication;
  751. #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
  752. (idphydrv->drive_authentication == 0x80)
  753. u8 smart_carrier_authentication;
  754. #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
  755. (idphydrv->smart_carrier_authentication != 0x0)
  756. #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
  757. (idphydrv->smart_carrier_authentication == 0x01)
  758. u8 smart_carrier_app_fw_version;
  759. u8 smart_carrier_bootloader_fw_version;
  760. u8 sanitize_support_flags;
  761. u8 drive_key_flags;
  762. u8 encryption_key_name[64];
  763. __le32 misc_drive_flags;
  764. __le16 dek_index;
  765. __le16 hba_drive_encryption_flags;
  766. __le16 max_overwrite_time;
  767. __le16 max_block_erase_time;
  768. __le16 max_crypto_erase_time;
  769. u8 device_connector_info[5];
  770. u8 connector_name[8][8];
  771. u8 page_83_id[16];
  772. u8 max_link_rate[256];
  773. u8 neg_phys_link_rate[256];
  774. u8 box_conn_name[8];
  775. } __attribute((aligned(512)));
  776. struct bmic_sense_subsystem_info {
  777. u8 primary_slot_number;
  778. u8 reserved[3];
  779. u8 chasis_serial_number[32];
  780. u8 primary_world_wide_id[8];
  781. u8 primary_array_serial_number[32]; /* NULL terminated */
  782. u8 primary_cache_serial_number[32]; /* NULL terminated */
  783. u8 reserved_2[8];
  784. u8 secondary_array_serial_number[32];
  785. u8 secondary_cache_serial_number[32];
  786. u8 pad[332];
  787. };
  788. struct bmic_sense_storage_box_params {
  789. u8 reserved[36];
  790. u8 inquiry_valid;
  791. u8 reserved_1[68];
  792. u8 phys_box_on_port;
  793. u8 reserved_2[22];
  794. u16 connection_info;
  795. u8 reserver_3[84];
  796. u8 phys_connector[2];
  797. u8 reserved_4[296];
  798. };
  799. #pragma pack()
  800. #endif /* HPSA_CMD_H */