hpsa.h 20 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
  4. * Copyright 2016 Microsemi Corporation
  5. * Copyright 2014-2015 PMC-Sierra, Inc.
  6. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  15. * NON INFRINGEMENT. See the GNU General Public License for more details.
  16. *
  17. * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  18. *
  19. */
  20. #ifndef HPSA_H
  21. #define HPSA_H
  22. #include <scsi/scsicam.h>
  23. #define IO_OK 0
  24. #define IO_ERROR 1
  25. struct ctlr_info;
  26. struct access_method {
  27. void (*submit_command)(struct ctlr_info *h,
  28. struct CommandList *c);
  29. void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
  30. bool (*intr_pending)(struct ctlr_info *h);
  31. unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
  32. };
  33. /* for SAS hosts and SAS expanders */
  34. struct hpsa_sas_node {
  35. struct device *parent_dev;
  36. struct list_head port_list_head;
  37. };
  38. struct hpsa_sas_port {
  39. struct list_head port_list_entry;
  40. u64 sas_address;
  41. struct sas_port *port;
  42. int next_phy_index;
  43. struct list_head phy_list_head;
  44. struct hpsa_sas_node *parent_node;
  45. struct sas_rphy *rphy;
  46. };
  47. struct hpsa_sas_phy {
  48. struct list_head phy_list_entry;
  49. struct sas_phy *phy;
  50. struct hpsa_sas_port *parent_port;
  51. bool added_to_port;
  52. };
  53. #define EXTERNAL_QD 128
  54. struct hpsa_scsi_dev_t {
  55. unsigned int devtype;
  56. int bus, target, lun; /* as presented to the OS */
  57. unsigned char scsi3addr[8]; /* as presented to the HW */
  58. u8 physical_device : 1;
  59. u8 expose_device;
  60. u8 removed : 1; /* device is marked for death */
  61. u8 was_removed : 1; /* device actually removed */
  62. #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
  63. unsigned char device_id[16]; /* from inquiry pg. 0x83 */
  64. u64 sas_address;
  65. u64 eli; /* from report diags. */
  66. unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
  67. unsigned char model[16]; /* bytes 16-31 of inquiry data */
  68. unsigned char rev; /* byte 2 of inquiry data */
  69. unsigned char raid_level; /* from inquiry page 0xC1 */
  70. unsigned char volume_offline; /* discovered via TUR or VPD */
  71. u16 queue_depth; /* max queue_depth for this device */
  72. atomic_t commands_outstanding; /* track commands sent to device */
  73. atomic_t ioaccel_cmds_out; /* Only used for physical devices
  74. * counts commands sent to physical
  75. * device via "ioaccel" path.
  76. */
  77. bool in_reset;
  78. u32 ioaccel_handle;
  79. u8 active_path_index;
  80. u8 path_map;
  81. u8 bay;
  82. u8 box[8];
  83. u16 phys_connector[8];
  84. int offload_config; /* I/O accel RAID offload configured */
  85. int offload_enabled; /* I/O accel RAID offload enabled */
  86. int offload_to_be_enabled;
  87. int hba_ioaccel_enabled;
  88. int offload_to_mirror; /* Send next I/O accelerator RAID
  89. * offload request to mirror drive
  90. */
  91. struct raid_map_data raid_map; /* I/O accelerator RAID map */
  92. /*
  93. * Pointers from logical drive map indices to the phys drives that
  94. * make those logical drives. Note, multiple logical drives may
  95. * share physical drives. You can have for instance 5 physical
  96. * drives with 3 logical drives each using those same 5 physical
  97. * disks. We need these pointers for counting i/o's out to physical
  98. * devices in order to honor physical device queue depth limits.
  99. */
  100. struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
  101. int nphysical_disks;
  102. int supports_aborts;
  103. struct hpsa_sas_port *sas_port;
  104. int external; /* 1-from external array 0-not <0-unknown */
  105. };
  106. struct reply_queue_buffer {
  107. u64 *head;
  108. size_t size;
  109. u8 wraparound;
  110. u32 current_entry;
  111. dma_addr_t busaddr;
  112. };
  113. #pragma pack(1)
  114. struct bmic_controller_parameters {
  115. u8 led_flags;
  116. u8 enable_command_list_verification;
  117. u8 backed_out_write_drives;
  118. u16 stripes_for_parity;
  119. u8 parity_distribution_mode_flags;
  120. u16 max_driver_requests;
  121. u16 elevator_trend_count;
  122. u8 disable_elevator;
  123. u8 force_scan_complete;
  124. u8 scsi_transfer_mode;
  125. u8 force_narrow;
  126. u8 rebuild_priority;
  127. u8 expand_priority;
  128. u8 host_sdb_asic_fix;
  129. u8 pdpi_burst_from_host_disabled;
  130. char software_name[64];
  131. char hardware_name[32];
  132. u8 bridge_revision;
  133. u8 snapshot_priority;
  134. u32 os_specific;
  135. u8 post_prompt_timeout;
  136. u8 automatic_drive_slamming;
  137. u8 reserved1;
  138. u8 nvram_flags;
  139. u8 cache_nvram_flags;
  140. u8 drive_config_flags;
  141. u16 reserved2;
  142. u8 temp_warning_level;
  143. u8 temp_shutdown_level;
  144. u8 temp_condition_reset;
  145. u8 max_coalesce_commands;
  146. u32 max_coalesce_delay;
  147. u8 orca_password[4];
  148. u8 access_id[16];
  149. u8 reserved[356];
  150. };
  151. #pragma pack()
  152. struct ctlr_info {
  153. unsigned int *reply_map;
  154. int ctlr;
  155. char devname[8];
  156. char *product_name;
  157. struct pci_dev *pdev;
  158. u32 board_id;
  159. u64 sas_address;
  160. void __iomem *vaddr;
  161. unsigned long paddr;
  162. int nr_cmds; /* Number of commands allowed on this controller */
  163. #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
  164. #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
  165. struct CfgTable __iomem *cfgtable;
  166. int interrupts_enabled;
  167. int max_commands;
  168. int last_collision_tag; /* tags are global */
  169. atomic_t commands_outstanding;
  170. # define PERF_MODE_INT 0
  171. # define DOORBELL_INT 1
  172. # define SIMPLE_MODE_INT 2
  173. # define MEMQ_MODE_INT 3
  174. unsigned int msix_vectors;
  175. int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
  176. struct access_method access;
  177. /* queue and queue Info */
  178. unsigned int Qdepth;
  179. unsigned int maxSG;
  180. spinlock_t lock;
  181. int maxsgentries;
  182. u8 max_cmd_sg_entries;
  183. int chainsize;
  184. struct SGDescriptor **cmd_sg_list;
  185. struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
  186. /* pointers to command and error info pool */
  187. struct CommandList *cmd_pool;
  188. dma_addr_t cmd_pool_dhandle;
  189. struct io_accel1_cmd *ioaccel_cmd_pool;
  190. dma_addr_t ioaccel_cmd_pool_dhandle;
  191. struct io_accel2_cmd *ioaccel2_cmd_pool;
  192. dma_addr_t ioaccel2_cmd_pool_dhandle;
  193. struct ErrorInfo *errinfo_pool;
  194. dma_addr_t errinfo_pool_dhandle;
  195. unsigned long *cmd_pool_bits;
  196. int scan_finished;
  197. u8 scan_waiting : 1;
  198. spinlock_t scan_lock;
  199. wait_queue_head_t scan_wait_queue;
  200. struct Scsi_Host *scsi_host;
  201. spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
  202. int ndevices; /* number of used elements in .dev[] array. */
  203. struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
  204. /*
  205. * Performant mode tables.
  206. */
  207. u32 trans_support;
  208. u32 trans_offset;
  209. struct TransTable_struct __iomem *transtable;
  210. unsigned long transMethod;
  211. /* cap concurrent passthrus at some reasonable maximum */
  212. #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
  213. atomic_t passthru_cmds_avail;
  214. /*
  215. * Performant mode completion buffers
  216. */
  217. size_t reply_queue_size;
  218. struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
  219. u8 nreply_queues;
  220. u32 *blockFetchTable;
  221. u32 *ioaccel1_blockFetchTable;
  222. u32 *ioaccel2_blockFetchTable;
  223. u32 __iomem *ioaccel2_bft2_regs;
  224. unsigned char *hba_inquiry_data;
  225. u32 driver_support;
  226. u32 fw_support;
  227. int ioaccel_support;
  228. int ioaccel_maxsg;
  229. u64 last_intr_timestamp;
  230. u32 last_heartbeat;
  231. u64 last_heartbeat_timestamp;
  232. u32 heartbeat_sample_interval;
  233. atomic_t firmware_flash_in_progress;
  234. u32 __percpu *lockup_detected;
  235. struct delayed_work monitor_ctlr_work;
  236. struct delayed_work rescan_ctlr_work;
  237. struct delayed_work event_monitor_work;
  238. int remove_in_progress;
  239. /* Address of h->q[x] is passed to intr handler to know which queue */
  240. u8 q[MAX_REPLY_QUEUES];
  241. char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
  242. u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
  243. #define HPSATMF_BITS_SUPPORTED (1 << 0)
  244. #define HPSATMF_PHYS_LUN_RESET (1 << 1)
  245. #define HPSATMF_PHYS_NEX_RESET (1 << 2)
  246. #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
  247. #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
  248. #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
  249. #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
  250. #define HPSATMF_PHYS_QRY_TASK (1 << 7)
  251. #define HPSATMF_PHYS_QRY_TSET (1 << 8)
  252. #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
  253. #define HPSATMF_IOACCEL_ENABLED (1 << 15)
  254. #define HPSATMF_MASK_SUPPORTED (1 << 16)
  255. #define HPSATMF_LOG_LUN_RESET (1 << 17)
  256. #define HPSATMF_LOG_NEX_RESET (1 << 18)
  257. #define HPSATMF_LOG_TASK_ABORT (1 << 19)
  258. #define HPSATMF_LOG_TSET_ABORT (1 << 20)
  259. #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
  260. #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
  261. #define HPSATMF_LOG_QRY_TASK (1 << 23)
  262. #define HPSATMF_LOG_QRY_TSET (1 << 24)
  263. #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
  264. u32 events;
  265. #define CTLR_STATE_CHANGE_EVENT (1 << 0)
  266. #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
  267. #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
  268. #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
  269. #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
  270. #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
  271. #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
  272. #define RESCAN_REQUIRED_EVENT_BITS \
  273. (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
  274. CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
  275. CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
  276. CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
  277. CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
  278. spinlock_t offline_device_lock;
  279. struct list_head offline_device_list;
  280. int acciopath_status;
  281. int drv_req_rescan;
  282. int raid_offload_debug;
  283. int discovery_polling;
  284. int legacy_board;
  285. struct ReportLUNdata *lastlogicals;
  286. int needs_abort_tags_swizzled;
  287. struct workqueue_struct *resubmit_wq;
  288. struct workqueue_struct *rescan_ctlr_wq;
  289. struct workqueue_struct *monitor_ctlr_wq;
  290. atomic_t abort_cmds_available;
  291. wait_queue_head_t event_sync_wait_queue;
  292. struct mutex reset_mutex;
  293. u8 reset_in_progress;
  294. struct hpsa_sas_node *sas_host;
  295. spinlock_t reset_lock;
  296. };
  297. struct offline_device_entry {
  298. unsigned char scsi3addr[8];
  299. struct list_head offline_list;
  300. };
  301. #define HPSA_ABORT_MSG 0
  302. #define HPSA_DEVICE_RESET_MSG 1
  303. #define HPSA_RESET_TYPE_CONTROLLER 0x00
  304. #define HPSA_RESET_TYPE_BUS 0x01
  305. #define HPSA_RESET_TYPE_LUN 0x04
  306. #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
  307. #define HPSA_MSG_SEND_RETRY_LIMIT 10
  308. #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
  309. /* Maximum time in seconds driver will wait for command completions
  310. * when polling before giving up.
  311. */
  312. #define HPSA_MAX_POLL_TIME_SECS (20)
  313. /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
  314. * how many times to retry TEST UNIT READY on a device
  315. * while waiting for it to become ready before giving up.
  316. * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
  317. * between sending TURs while waiting for a device
  318. * to become ready.
  319. */
  320. #define HPSA_TUR_RETRY_LIMIT (20)
  321. #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
  322. /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
  323. * to become ready, in seconds, before giving up on it.
  324. * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
  325. * between polling the board to see if it is ready, in
  326. * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
  327. * HPSA_BOARD_READY_ITERATIONS are derived from those.
  328. */
  329. #define HPSA_BOARD_READY_WAIT_SECS (120)
  330. #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
  331. #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
  332. #define HPSA_BOARD_READY_POLL_INTERVAL \
  333. ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
  334. #define HPSA_BOARD_READY_ITERATIONS \
  335. ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
  336. HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
  337. #define HPSA_BOARD_NOT_READY_ITERATIONS \
  338. ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
  339. HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
  340. #define HPSA_POST_RESET_PAUSE_MSECS (3000)
  341. #define HPSA_POST_RESET_NOOP_RETRIES (12)
  342. /* Defining the diffent access_menthods */
  343. /*
  344. * Memory mapped FIFO interface (SMART 53xx cards)
  345. */
  346. #define SA5_DOORBELL 0x20
  347. #define SA5_REQUEST_PORT_OFFSET 0x40
  348. #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
  349. #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
  350. #define SA5_REPLY_INTR_MASK_OFFSET 0x34
  351. #define SA5_REPLY_PORT_OFFSET 0x44
  352. #define SA5_INTR_STATUS 0x30
  353. #define SA5_SCRATCHPAD_OFFSET 0xB0
  354. #define SA5_CTCFG_OFFSET 0xB4
  355. #define SA5_CTMEM_OFFSET 0xB8
  356. #define SA5_INTR_OFF 0x08
  357. #define SA5B_INTR_OFF 0x04
  358. #define SA5_INTR_PENDING 0x08
  359. #define SA5B_INTR_PENDING 0x04
  360. #define FIFO_EMPTY 0xffffffff
  361. #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
  362. #define HPSA_ERROR_BIT 0x02
  363. /* Performant mode flags */
  364. #define SA5_PERF_INTR_PENDING 0x04
  365. #define SA5_PERF_INTR_OFF 0x05
  366. #define SA5_OUTDB_STATUS_PERF_BIT 0x01
  367. #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
  368. #define SA5_OUTDB_CLEAR 0xA0
  369. #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
  370. #define SA5_OUTDB_STATUS 0x9C
  371. #define HPSA_INTR_ON 1
  372. #define HPSA_INTR_OFF 0
  373. /*
  374. * Inbound Post Queue offsets for IO Accelerator Mode 2
  375. */
  376. #define IOACCEL2_INBOUND_POSTQ_32 0x48
  377. #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
  378. #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
  379. #define HPSA_PHYSICAL_DEVICE_BUS 0
  380. #define HPSA_RAID_VOLUME_BUS 1
  381. #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
  382. #define HPSA_HBA_BUS 0
  383. #define HPSA_LEGACY_HBA_BUS 3
  384. /*
  385. Send the command to the hardware
  386. */
  387. static void SA5_submit_command(struct ctlr_info *h,
  388. struct CommandList *c)
  389. {
  390. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  391. (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  392. }
  393. static void SA5_submit_command_no_read(struct ctlr_info *h,
  394. struct CommandList *c)
  395. {
  396. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  397. }
  398. static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
  399. struct CommandList *c)
  400. {
  401. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  402. }
  403. /*
  404. * This card is the opposite of the other cards.
  405. * 0 turns interrupts on...
  406. * 0x08 turns them off...
  407. */
  408. static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
  409. {
  410. if (val) { /* Turn interrupts on */
  411. h->interrupts_enabled = 1;
  412. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  413. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  414. } else { /* Turn them off */
  415. h->interrupts_enabled = 0;
  416. writel(SA5_INTR_OFF,
  417. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  418. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  419. }
  420. }
  421. /*
  422. * Variant of the above; 0x04 turns interrupts off...
  423. */
  424. static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val)
  425. {
  426. if (val) { /* Turn interrupts on */
  427. h->interrupts_enabled = 1;
  428. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  429. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  430. } else { /* Turn them off */
  431. h->interrupts_enabled = 0;
  432. writel(SA5B_INTR_OFF,
  433. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  434. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  435. }
  436. }
  437. static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
  438. {
  439. if (val) { /* turn on interrupts */
  440. h->interrupts_enabled = 1;
  441. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  442. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  443. } else {
  444. h->interrupts_enabled = 0;
  445. writel(SA5_PERF_INTR_OFF,
  446. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  447. (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  448. }
  449. }
  450. static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
  451. {
  452. struct reply_queue_buffer *rq = &h->reply_queue[q];
  453. unsigned long register_value = FIFO_EMPTY;
  454. /* msi auto clears the interrupt pending bit. */
  455. if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) {
  456. /* flush the controller write of the reply queue by reading
  457. * outbound doorbell status register.
  458. */
  459. (void) readl(h->vaddr + SA5_OUTDB_STATUS);
  460. writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
  461. /* Do a read in order to flush the write to the controller
  462. * (as per spec.)
  463. */
  464. (void) readl(h->vaddr + SA5_OUTDB_STATUS);
  465. }
  466. if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
  467. register_value = rq->head[rq->current_entry];
  468. rq->current_entry++;
  469. atomic_dec(&h->commands_outstanding);
  470. } else {
  471. register_value = FIFO_EMPTY;
  472. }
  473. /* Check for wraparound */
  474. if (rq->current_entry == h->max_commands) {
  475. rq->current_entry = 0;
  476. rq->wraparound ^= 1;
  477. }
  478. return register_value;
  479. }
  480. /*
  481. * returns value read from hardware.
  482. * returns FIFO_EMPTY if there is nothing to read
  483. */
  484. static unsigned long SA5_completed(struct ctlr_info *h,
  485. __attribute__((unused)) u8 q)
  486. {
  487. unsigned long register_value
  488. = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
  489. if (register_value != FIFO_EMPTY)
  490. atomic_dec(&h->commands_outstanding);
  491. #ifdef HPSA_DEBUG
  492. if (register_value != FIFO_EMPTY)
  493. dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
  494. register_value);
  495. else
  496. dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
  497. #endif
  498. return register_value;
  499. }
  500. /*
  501. * Returns true if an interrupt is pending..
  502. */
  503. static bool SA5_intr_pending(struct ctlr_info *h)
  504. {
  505. unsigned long register_value =
  506. readl(h->vaddr + SA5_INTR_STATUS);
  507. return register_value & SA5_INTR_PENDING;
  508. }
  509. static bool SA5_performant_intr_pending(struct ctlr_info *h)
  510. {
  511. unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
  512. if (!register_value)
  513. return false;
  514. /* Read outbound doorbell to flush */
  515. register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
  516. return register_value & SA5_OUTDB_STATUS_PERF_BIT;
  517. }
  518. #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
  519. static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
  520. {
  521. unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
  522. return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
  523. true : false;
  524. }
  525. /*
  526. * Returns true if an interrupt is pending..
  527. */
  528. static bool SA5B_intr_pending(struct ctlr_info *h)
  529. {
  530. return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING;
  531. }
  532. #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
  533. #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
  534. #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
  535. #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
  536. static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
  537. {
  538. u64 register_value;
  539. struct reply_queue_buffer *rq = &h->reply_queue[q];
  540. BUG_ON(q >= h->nreply_queues);
  541. register_value = rq->head[rq->current_entry];
  542. if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
  543. rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
  544. if (++rq->current_entry == rq->size)
  545. rq->current_entry = 0;
  546. /*
  547. * @todo
  548. *
  549. * Don't really need to write the new index after each command,
  550. * but with current driver design this is easiest.
  551. */
  552. wmb();
  553. writel((q << 24) | rq->current_entry, h->vaddr +
  554. IOACCEL_MODE1_CONSUMER_INDEX);
  555. atomic_dec(&h->commands_outstanding);
  556. }
  557. return (unsigned long) register_value;
  558. }
  559. static struct access_method SA5_access = {
  560. .submit_command = SA5_submit_command,
  561. .set_intr_mask = SA5_intr_mask,
  562. .intr_pending = SA5_intr_pending,
  563. .command_completed = SA5_completed,
  564. };
  565. /* Duplicate entry of the above to mark unsupported boards */
  566. static struct access_method SA5A_access = {
  567. .submit_command = SA5_submit_command,
  568. .set_intr_mask = SA5_intr_mask,
  569. .intr_pending = SA5_intr_pending,
  570. .command_completed = SA5_completed,
  571. };
  572. static struct access_method SA5B_access = {
  573. .submit_command = SA5_submit_command,
  574. .set_intr_mask = SA5B_intr_mask,
  575. .intr_pending = SA5B_intr_pending,
  576. .command_completed = SA5_completed,
  577. };
  578. static struct access_method SA5_ioaccel_mode1_access = {
  579. .submit_command = SA5_submit_command,
  580. .set_intr_mask = SA5_performant_intr_mask,
  581. .intr_pending = SA5_ioaccel_mode1_intr_pending,
  582. .command_completed = SA5_ioaccel_mode1_completed,
  583. };
  584. static struct access_method SA5_ioaccel_mode2_access = {
  585. .submit_command = SA5_submit_command_ioaccel2,
  586. .set_intr_mask = SA5_performant_intr_mask,
  587. .intr_pending = SA5_performant_intr_pending,
  588. .command_completed = SA5_performant_completed,
  589. };
  590. static struct access_method SA5_performant_access = {
  591. .submit_command = SA5_submit_command,
  592. .set_intr_mask = SA5_performant_intr_mask,
  593. .intr_pending = SA5_performant_intr_pending,
  594. .command_completed = SA5_performant_completed,
  595. };
  596. static struct access_method SA5_performant_access_no_read = {
  597. .submit_command = SA5_submit_command_no_read,
  598. .set_intr_mask = SA5_performant_intr_mask,
  599. .intr_pending = SA5_performant_intr_pending,
  600. .command_completed = SA5_performant_completed,
  601. };
  602. struct board_type {
  603. u32 board_id;
  604. char *product_name;
  605. struct access_method *access;
  606. };
  607. #endif /* HPSA_H */