hisi_sas_v3_hw.c 105 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2017 Hisilicon Limited.
  4. */
  5. #include "hisi_sas.h"
  6. #define DRV_NAME "hisi_sas_v3_hw"
  7. /* global registers need init */
  8. #define DLVRY_QUEUE_ENABLE 0x0
  9. #define IOST_BASE_ADDR_LO 0x8
  10. #define IOST_BASE_ADDR_HI 0xc
  11. #define ITCT_BASE_ADDR_LO 0x10
  12. #define ITCT_BASE_ADDR_HI 0x14
  13. #define IO_BROKEN_MSG_ADDR_LO 0x18
  14. #define IO_BROKEN_MSG_ADDR_HI 0x1c
  15. #define PHY_CONTEXT 0x20
  16. #define PHY_STATE 0x24
  17. #define PHY_PORT_NUM_MA 0x28
  18. #define PHY_CONN_RATE 0x30
  19. #define ITCT_CLR 0x44
  20. #define ITCT_CLR_EN_OFF 16
  21. #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
  22. #define ITCT_DEV_OFF 0
  23. #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
  24. #define SAS_AXI_USER3 0x50
  25. #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
  26. #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
  27. #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
  28. #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
  29. #define CFG_MAX_TAG 0x68
  30. #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  31. #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
  32. #define HGC_GET_ITV_TIME 0x90
  33. #define DEVICE_MSG_WORK_MODE 0x94
  34. #define OPENA_WT_CONTI_TIME 0x9c
  35. #define I_T_NEXUS_LOSS_TIME 0xa0
  36. #define MAX_CON_TIME_LIMIT_TIME 0xa4
  37. #define BUS_INACTIVE_LIMIT_TIME 0xa8
  38. #define REJECT_TO_OPEN_LIMIT_TIME 0xac
  39. #define CQ_INT_CONVERGE_EN 0xb0
  40. #define CFG_AGING_TIME 0xbc
  41. #define HGC_DFX_CFG2 0xc0
  42. #define CFG_ABT_SET_QUERY_IPTT 0xd4
  43. #define CFG_SET_ABORTED_IPTT_OFF 0
  44. #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
  45. #define CFG_SET_ABORTED_EN_OFF 12
  46. #define CFG_ABT_SET_IPTT_DONE 0xd8
  47. #define CFG_ABT_SET_IPTT_DONE_OFF 0
  48. #define HGC_IOMB_PROC1_STATUS 0x104
  49. #define HGC_LM_DFX_STATUS2 0x128
  50. #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
  51. #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  52. HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  53. #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
  54. #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  55. HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  56. #define HGC_CQE_ECC_ADDR 0x13c
  57. #define HGC_CQE_ECC_1B_ADDR_OFF 0
  58. #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  59. #define HGC_CQE_ECC_MB_ADDR_OFF 8
  60. #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  61. #define HGC_IOST_ECC_ADDR 0x140
  62. #define HGC_IOST_ECC_1B_ADDR_OFF 0
  63. #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  64. #define HGC_IOST_ECC_MB_ADDR_OFF 16
  65. #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  66. #define HGC_DQE_ECC_ADDR 0x144
  67. #define HGC_DQE_ECC_1B_ADDR_OFF 0
  68. #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  69. #define HGC_DQE_ECC_MB_ADDR_OFF 16
  70. #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  71. #define CHNL_INT_STATUS 0x148
  72. #define TAB_DFX 0x14c
  73. #define HGC_ITCT_ECC_ADDR 0x150
  74. #define HGC_ITCT_ECC_1B_ADDR_OFF 0
  75. #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
  76. HGC_ITCT_ECC_1B_ADDR_OFF)
  77. #define HGC_ITCT_ECC_MB_ADDR_OFF 16
  78. #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
  79. HGC_ITCT_ECC_MB_ADDR_OFF)
  80. #define HGC_AXI_FIFO_ERR_INFO 0x154
  81. #define AXI_ERR_INFO_OFF 0
  82. #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
  83. #define FIFO_ERR_INFO_OFF 8
  84. #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
  85. #define TAB_RD_TYPE 0x15c
  86. #define INT_COAL_EN 0x19c
  87. #define OQ_INT_COAL_TIME 0x1a0
  88. #define OQ_INT_COAL_CNT 0x1a4
  89. #define ENT_INT_COAL_TIME 0x1a8
  90. #define ENT_INT_COAL_CNT 0x1ac
  91. #define OQ_INT_SRC 0x1b0
  92. #define OQ_INT_SRC_MSK 0x1b4
  93. #define ENT_INT_SRC1 0x1b8
  94. #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
  95. #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  96. #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
  97. #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  98. #define ENT_INT_SRC2 0x1bc
  99. #define ENT_INT_SRC3 0x1c0
  100. #define ENT_INT_SRC3_WP_DEPTH_OFF 8
  101. #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
  102. #define ENT_INT_SRC3_RP_DEPTH_OFF 10
  103. #define ENT_INT_SRC3_AXI_OFF 11
  104. #define ENT_INT_SRC3_FIFO_OFF 12
  105. #define ENT_INT_SRC3_LM_OFF 14
  106. #define ENT_INT_SRC3_ITC_INT_OFF 15
  107. #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  108. #define ENT_INT_SRC3_ABT_OFF 16
  109. #define ENT_INT_SRC3_DQE_POISON_OFF 18
  110. #define ENT_INT_SRC3_IOST_POISON_OFF 19
  111. #define ENT_INT_SRC3_ITCT_POISON_OFF 20
  112. #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
  113. #define ENT_INT_SRC_MSK1 0x1c4
  114. #define ENT_INT_SRC_MSK2 0x1c8
  115. #define ENT_INT_SRC_MSK3 0x1cc
  116. #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
  117. #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
  118. #define CHNL_ENT_INT_MSK 0x1d4
  119. #define HGC_COM_INT_MSK 0x1d8
  120. #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  121. #define SAS_ECC_INTR 0x1e8
  122. #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
  123. #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
  124. #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
  125. #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
  126. #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
  127. #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
  128. #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
  129. #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
  130. #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
  131. #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
  132. #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
  133. #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
  134. #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
  135. #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
  136. #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
  137. #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
  138. #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
  139. #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
  140. #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
  141. #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
  142. #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
  143. #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
  144. #define SAS_ECC_INTR_MSK 0x1ec
  145. #define HGC_ERR_STAT_EN 0x238
  146. #define CQE_SEND_CNT 0x248
  147. #define DLVRY_Q_0_BASE_ADDR_LO 0x260
  148. #define DLVRY_Q_0_BASE_ADDR_HI 0x264
  149. #define DLVRY_Q_0_DEPTH 0x268
  150. #define DLVRY_Q_0_WR_PTR 0x26c
  151. #define DLVRY_Q_0_RD_PTR 0x270
  152. #define HYPER_STREAM_ID_EN_CFG 0xc80
  153. #define OQ0_INT_SRC_MSK 0xc90
  154. #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
  155. #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
  156. #define COMPL_Q_0_DEPTH 0x4e8
  157. #define COMPL_Q_0_WR_PTR 0x4ec
  158. #define COMPL_Q_0_RD_PTR 0x4f0
  159. #define HGC_RXM_DFX_STATUS14 0xae8
  160. #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
  161. #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
  162. HGC_RXM_DFX_STATUS14_MEM0_OFF)
  163. #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
  164. #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
  165. HGC_RXM_DFX_STATUS14_MEM1_OFF)
  166. #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
  167. #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
  168. HGC_RXM_DFX_STATUS14_MEM2_OFF)
  169. #define HGC_RXM_DFX_STATUS15 0xaec
  170. #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
  171. #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
  172. HGC_RXM_DFX_STATUS15_MEM3_OFF)
  173. #define AWQOS_AWCACHE_CFG 0xc84
  174. #define ARQOS_ARCACHE_CFG 0xc88
  175. #define HILINK_ERR_DFX 0xe04
  176. #define SAS_GPIO_CFG_0 0x1000
  177. #define SAS_GPIO_CFG_1 0x1004
  178. #define SAS_GPIO_TX_0_1 0x1040
  179. #define SAS_CFG_DRIVE_VLD 0x1070
  180. /* phy registers requiring init */
  181. #define PORT_BASE (0x2000)
  182. #define PHY_CFG (PORT_BASE + 0x0)
  183. #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
  184. #define PHY_CFG_ENA_OFF 0
  185. #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
  186. #define PHY_CFG_DC_OPT_OFF 2
  187. #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
  188. #define PHY_CFG_PHY_RST_OFF 3
  189. #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
  190. #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
  191. #define CFG_PROG_PHY_LINK_RATE_OFF 0
  192. #define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
  193. #define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
  194. #define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
  195. #define PHY_CTRL (PORT_BASE + 0x14)
  196. #define PHY_CTRL_RESET_OFF 0
  197. #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
  198. #define CMD_HDR_PIR_OFF 8
  199. #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
  200. #define SERDES_CFG (PORT_BASE + 0x1c)
  201. #define CFG_ALOS_CHK_DISABLE_OFF 9
  202. #define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
  203. #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
  204. #define CFG_BIST_MODE_SEL_OFF 0
  205. #define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
  206. #define CFG_LOOP_TEST_MODE_OFF 14
  207. #define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
  208. #define CFG_RX_BIST_EN_OFF 16
  209. #define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
  210. #define CFG_TX_BIST_EN_OFF 17
  211. #define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
  212. #define CFG_BIST_TEST_OFF 18
  213. #define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
  214. #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
  215. #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
  216. #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
  217. #define SL_CFG (PORT_BASE + 0x84)
  218. #define AIP_LIMIT (PORT_BASE + 0x90)
  219. #define SL_CONTROL (PORT_BASE + 0x94)
  220. #define SL_CONTROL_NOTIFY_EN_OFF 0
  221. #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
  222. #define SL_CTA_OFF 17
  223. #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
  224. #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
  225. #define RX_BCAST_CHG_OFF 1
  226. #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
  227. #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
  228. #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
  229. #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
  230. #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
  231. #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
  232. #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
  233. #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
  234. #define TXID_AUTO (PORT_BASE + 0xb8)
  235. #define CT3_OFF 1
  236. #define CT3_MSK (0x1 << CT3_OFF)
  237. #define TX_HARDRST_OFF 2
  238. #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
  239. #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
  240. #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
  241. #define STP_LINK_TIMER (PORT_BASE + 0x120)
  242. #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
  243. #define CON_CFG_DRIVER (PORT_BASE + 0x130)
  244. #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
  245. #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
  246. #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
  247. #define CHL_INT0 (PORT_BASE + 0x1b4)
  248. #define CHL_INT0_HOTPLUG_TOUT_OFF 0
  249. #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
  250. #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
  251. #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
  252. #define CHL_INT0_SL_PHY_ENABLE_OFF 2
  253. #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
  254. #define CHL_INT0_NOT_RDY_OFF 4
  255. #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
  256. #define CHL_INT0_PHY_RDY_OFF 5
  257. #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
  258. #define CHL_INT1 (PORT_BASE + 0x1b8)
  259. #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
  260. #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
  261. #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
  262. #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
  263. #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
  264. #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
  265. #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
  266. #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
  267. #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
  268. #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
  269. #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
  270. #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
  271. #define CHL_INT2 (PORT_BASE + 0x1bc)
  272. #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
  273. #define CHL_INT2_RX_DISP_ERR_OFF 28
  274. #define CHL_INT2_RX_CODE_ERR_OFF 29
  275. #define CHL_INT2_RX_INVLD_DW_OFF 30
  276. #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
  277. #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
  278. #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
  279. #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
  280. #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
  281. #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
  282. #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
  283. #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
  284. #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
  285. #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
  286. #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
  287. #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
  288. #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
  289. #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
  290. #define DMA_TX_STATUS_BUSY_OFF 0
  291. #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
  292. #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
  293. #define DMA_RX_STATUS_BUSY_OFF 0
  294. #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
  295. #define COARSETUNE_TIME (PORT_BASE + 0x304)
  296. #define TXDEEMPH_G1 (PORT_BASE + 0x350)
  297. #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
  298. #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
  299. #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
  300. #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
  301. #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
  302. #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
  303. #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
  304. #error Max ITCT exceeded
  305. #endif
  306. #define AXI_MASTER_CFG_BASE (0x5000)
  307. #define AM_CTRL_GLOBAL (0x0)
  308. #define AM_CTRL_SHUTDOWN_REQ_OFF 0
  309. #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
  310. #define AM_CURR_TRANS_RETURN (0x150)
  311. #define AM_CFG_MAX_TRANS (0x5010)
  312. #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
  313. #define AXI_CFG (0x5100)
  314. #define AM_ROB_ECC_ERR_ADDR (0x510c)
  315. #define AM_ROB_ECC_ERR_ADDR_OFF 0
  316. #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
  317. /* RAS registers need init */
  318. #define RAS_BASE (0x6000)
  319. #define SAS_RAS_INTR0 (RAS_BASE)
  320. #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
  321. #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
  322. #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
  323. #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
  324. #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
  325. #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
  326. /* HW dma structures */
  327. /* Delivery queue header */
  328. /* dw0 */
  329. #define CMD_HDR_ABORT_FLAG_OFF 0
  330. #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
  331. #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
  332. #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
  333. #define CMD_HDR_RESP_REPORT_OFF 5
  334. #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
  335. #define CMD_HDR_TLR_CTRL_OFF 6
  336. #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
  337. #define CMD_HDR_PORT_OFF 18
  338. #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
  339. #define CMD_HDR_PRIORITY_OFF 27
  340. #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
  341. #define CMD_HDR_CMD_OFF 29
  342. #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
  343. /* dw1 */
  344. #define CMD_HDR_UNCON_CMD_OFF 3
  345. #define CMD_HDR_DIR_OFF 5
  346. #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
  347. #define CMD_HDR_RESET_OFF 7
  348. #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
  349. #define CMD_HDR_VDTL_OFF 10
  350. #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
  351. #define CMD_HDR_FRAME_TYPE_OFF 11
  352. #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
  353. #define CMD_HDR_DEV_ID_OFF 16
  354. #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
  355. /* dw2 */
  356. #define CMD_HDR_CFL_OFF 0
  357. #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
  358. #define CMD_HDR_NCQ_TAG_OFF 10
  359. #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
  360. #define CMD_HDR_MRFL_OFF 15
  361. #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
  362. #define CMD_HDR_SG_MOD_OFF 24
  363. #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
  364. /* dw3 */
  365. #define CMD_HDR_IPTT_OFF 0
  366. #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
  367. /* dw6 */
  368. #define CMD_HDR_DIF_SGL_LEN_OFF 0
  369. #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
  370. #define CMD_HDR_DATA_SGL_LEN_OFF 16
  371. #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
  372. /* dw7 */
  373. #define CMD_HDR_ADDR_MODE_SEL_OFF 15
  374. #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
  375. #define CMD_HDR_ABORT_IPTT_OFF 16
  376. #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
  377. /* Completion header */
  378. /* dw0 */
  379. #define CMPLT_HDR_CMPLT_OFF 0
  380. #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
  381. #define CMPLT_HDR_ERROR_PHASE_OFF 2
  382. #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
  383. #define CMPLT_HDR_RSPNS_XFRD_OFF 10
  384. #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
  385. #define CMPLT_HDR_ERX_OFF 12
  386. #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
  387. #define CMPLT_HDR_ABORT_STAT_OFF 13
  388. #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
  389. /* abort_stat */
  390. #define STAT_IO_NOT_VALID 0x1
  391. #define STAT_IO_NO_DEVICE 0x2
  392. #define STAT_IO_COMPLETE 0x3
  393. #define STAT_IO_ABORTED 0x4
  394. /* dw1 */
  395. #define CMPLT_HDR_IPTT_OFF 0
  396. #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
  397. #define CMPLT_HDR_DEV_ID_OFF 16
  398. #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
  399. /* dw3 */
  400. #define CMPLT_HDR_IO_IN_TARGET_OFF 17
  401. #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
  402. /* ITCT header */
  403. /* qw0 */
  404. #define ITCT_HDR_DEV_TYPE_OFF 0
  405. #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
  406. #define ITCT_HDR_VALID_OFF 2
  407. #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
  408. #define ITCT_HDR_MCR_OFF 5
  409. #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
  410. #define ITCT_HDR_VLN_OFF 9
  411. #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
  412. #define ITCT_HDR_SMP_TIMEOUT_OFF 16
  413. #define ITCT_HDR_AWT_CONTINUE_OFF 25
  414. #define ITCT_HDR_PORT_ID_OFF 28
  415. #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
  416. /* qw2 */
  417. #define ITCT_HDR_INLT_OFF 0
  418. #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
  419. #define ITCT_HDR_RTOLT_OFF 48
  420. #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
  421. struct hisi_sas_protect_iu_v3_hw {
  422. u32 dw0;
  423. u32 lbrtcv;
  424. u32 lbrtgv;
  425. u32 dw3;
  426. u32 dw4;
  427. u32 dw5;
  428. u32 rsv;
  429. };
  430. struct hisi_sas_complete_v3_hdr {
  431. __le32 dw0;
  432. __le32 dw1;
  433. __le32 act;
  434. __le32 dw3;
  435. };
  436. struct hisi_sas_err_record_v3 {
  437. /* dw0 */
  438. __le32 trans_tx_fail_type;
  439. /* dw1 */
  440. __le32 trans_rx_fail_type;
  441. /* dw2 */
  442. __le16 dma_tx_err_type;
  443. __le16 sipc_rx_err_type;
  444. /* dw3 */
  445. __le32 dma_rx_err_type;
  446. };
  447. #define RX_DATA_LEN_UNDERFLOW_OFF 6
  448. #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
  449. #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
  450. #define HISI_SAS_MSI_COUNT_V3_HW 32
  451. #define DIR_NO_DATA 0
  452. #define DIR_TO_INI 1
  453. #define DIR_TO_DEVICE 2
  454. #define DIR_RESERVED 3
  455. #define FIS_CMD_IS_UNCONSTRAINED(fis) \
  456. ((fis.command == ATA_CMD_READ_LOG_EXT) || \
  457. (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
  458. ((fis.command == ATA_CMD_DEV_RESET) && \
  459. ((fis.control & ATA_SRST) != 0)))
  460. #define T10_INSRT_EN_OFF 0
  461. #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
  462. #define T10_RMV_EN_OFF 1
  463. #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
  464. #define T10_RPLC_EN_OFF 2
  465. #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
  466. #define T10_CHK_EN_OFF 3
  467. #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
  468. #define INCR_LBRT_OFF 5
  469. #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
  470. #define USR_DATA_BLOCK_SZ_OFF 20
  471. #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
  472. #define T10_CHK_MSK_OFF 16
  473. #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
  474. #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
  475. #define BASE_VECTORS_V3_HW 16
  476. #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
  477. #define CHNL_INT_STS_MSK 0xeeeeeeee
  478. #define CHNL_INT_STS_PHY_MSK 0xe
  479. #define CHNL_INT_STS_INT0_MSK BIT(1)
  480. #define CHNL_INT_STS_INT1_MSK BIT(2)
  481. #define CHNL_INT_STS_INT2_MSK BIT(3)
  482. #define CHNL_WIDTH 4
  483. enum {
  484. DSM_FUNC_ERR_HANDLE_MSI = 0,
  485. };
  486. static bool hisi_sas_intr_conv;
  487. MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
  488. /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
  489. static int prot_mask;
  490. module_param(prot_mask, int, 0444);
  491. MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
  492. static bool auto_affine_msi_experimental;
  493. module_param(auto_affine_msi_experimental, bool, 0444);
  494. MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n"
  495. "default is off");
  496. static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
  497. {
  498. void __iomem *regs = hisi_hba->regs + off;
  499. return readl(regs);
  500. }
  501. static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
  502. {
  503. void __iomem *regs = hisi_hba->regs + off;
  504. writel(val, regs);
  505. }
  506. static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
  507. u32 off, u32 val)
  508. {
  509. void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
  510. writel(val, regs);
  511. }
  512. static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
  513. int phy_no, u32 off)
  514. {
  515. void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
  516. return readl(regs);
  517. }
  518. #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
  519. timeout_us) \
  520. ({ \
  521. void __iomem *regs = hisi_hba->regs + off; \
  522. readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
  523. })
  524. #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
  525. timeout_us) \
  526. ({ \
  527. void __iomem *regs = hisi_hba->regs + off; \
  528. readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
  529. })
  530. static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
  531. {
  532. int i, j;
  533. /* Global registers init */
  534. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
  535. (u32)((1ULL << hisi_hba->queue_count) - 1));
  536. hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
  537. hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
  538. hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
  539. hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
  540. hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
  541. hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
  542. hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
  543. hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
  544. hisi_sas_intr_conv);
  545. hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
  546. hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
  547. hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
  548. hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
  549. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
  550. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
  551. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
  552. hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
  553. hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
  554. hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
  555. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
  556. hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
  557. hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
  558. for (i = 0; i < hisi_hba->queue_count; i++)
  559. hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
  560. hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
  561. for (i = 0; i < hisi_hba->n_phy; i++) {
  562. enum sas_linkrate max;
  563. struct hisi_sas_phy *phy = &hisi_hba->phy[i];
  564. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  565. u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
  566. PROG_PHY_LINK_RATE);
  567. prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
  568. if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
  569. SAS_LINK_RATE_1_5_GBPS))
  570. max = SAS_LINK_RATE_12_0_GBPS;
  571. else
  572. max = sas_phy->phy->maximum_linkrate;
  573. prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
  574. hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
  575. prog_phy_link_rate);
  576. hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
  577. hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
  578. hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
  579. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
  580. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
  581. hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
  582. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
  583. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
  584. hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
  585. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
  586. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
  587. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
  588. hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
  589. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
  590. hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
  591. hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
  592. hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
  593. hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
  594. 0x30f4240);
  595. /* used for 12G negotiate */
  596. hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
  597. hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
  598. /* get default FFE configuration for BIST */
  599. for (j = 0; j < FFE_CFG_MAX; j++) {
  600. u32 val = hisi_sas_phy_read32(hisi_hba, i,
  601. TXDEEMPH_G1 + (j * 0x4));
  602. hisi_hba->debugfs_bist_ffe[i][j] = val;
  603. }
  604. }
  605. for (i = 0; i < hisi_hba->queue_count; i++) {
  606. /* Delivery queue */
  607. hisi_sas_write32(hisi_hba,
  608. DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
  609. upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
  610. hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
  611. lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
  612. hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
  613. HISI_SAS_QUEUE_SLOTS);
  614. /* Completion queue */
  615. hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
  616. upper_32_bits(hisi_hba->complete_hdr_dma[i]));
  617. hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
  618. lower_32_bits(hisi_hba->complete_hdr_dma[i]));
  619. hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
  620. HISI_SAS_QUEUE_SLOTS);
  621. }
  622. /* itct */
  623. hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
  624. lower_32_bits(hisi_hba->itct_dma));
  625. hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
  626. upper_32_bits(hisi_hba->itct_dma));
  627. /* iost */
  628. hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
  629. lower_32_bits(hisi_hba->iost_dma));
  630. hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
  631. upper_32_bits(hisi_hba->iost_dma));
  632. /* breakpoint */
  633. hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
  634. lower_32_bits(hisi_hba->breakpoint_dma));
  635. hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
  636. upper_32_bits(hisi_hba->breakpoint_dma));
  637. /* SATA broken msg */
  638. hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
  639. lower_32_bits(hisi_hba->sata_breakpoint_dma));
  640. hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
  641. upper_32_bits(hisi_hba->sata_breakpoint_dma));
  642. /* SATA initial fis */
  643. hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
  644. lower_32_bits(hisi_hba->initial_fis_dma));
  645. hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
  646. upper_32_bits(hisi_hba->initial_fis_dma));
  647. /* RAS registers init */
  648. hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
  649. hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
  650. hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
  651. hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
  652. /* LED registers init */
  653. hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
  654. hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
  655. hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
  656. /* Configure blink generator rate A to 1Hz and B to 4Hz */
  657. hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
  658. hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
  659. }
  660. static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  661. {
  662. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  663. cfg &= ~PHY_CFG_DC_OPT_MSK;
  664. cfg |= 1 << PHY_CFG_DC_OPT_OFF;
  665. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  666. }
  667. static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  668. {
  669. struct sas_identify_frame identify_frame;
  670. u32 *identify_buffer;
  671. memset(&identify_frame, 0, sizeof(identify_frame));
  672. identify_frame.dev_type = SAS_END_DEVICE;
  673. identify_frame.frame_type = 0;
  674. identify_frame._un1 = 1;
  675. identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
  676. identify_frame.target_bits = SAS_PROTOCOL_NONE;
  677. memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
  678. memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
  679. identify_frame.phy_id = phy_no;
  680. identify_buffer = (u32 *)(&identify_frame);
  681. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
  682. __swab32(identify_buffer[0]));
  683. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
  684. __swab32(identify_buffer[1]));
  685. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
  686. __swab32(identify_buffer[2]));
  687. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
  688. __swab32(identify_buffer[3]));
  689. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
  690. __swab32(identify_buffer[4]));
  691. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
  692. __swab32(identify_buffer[5]));
  693. }
  694. static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
  695. struct hisi_sas_device *sas_dev)
  696. {
  697. struct domain_device *device = sas_dev->sas_device;
  698. struct device *dev = hisi_hba->dev;
  699. u64 qw0, device_id = sas_dev->device_id;
  700. struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
  701. struct domain_device *parent_dev = device->parent;
  702. struct asd_sas_port *sas_port = device->port;
  703. struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
  704. u64 sas_addr;
  705. memset(itct, 0, sizeof(*itct));
  706. /* qw0 */
  707. qw0 = 0;
  708. switch (sas_dev->dev_type) {
  709. case SAS_END_DEVICE:
  710. case SAS_EDGE_EXPANDER_DEVICE:
  711. case SAS_FANOUT_EXPANDER_DEVICE:
  712. qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
  713. break;
  714. case SAS_SATA_DEV:
  715. case SAS_SATA_PENDING:
  716. if (parent_dev && dev_is_expander(parent_dev->dev_type))
  717. qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
  718. else
  719. qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
  720. break;
  721. default:
  722. dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
  723. sas_dev->dev_type);
  724. }
  725. qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
  726. (device->linkrate << ITCT_HDR_MCR_OFF) |
  727. (1 << ITCT_HDR_VLN_OFF) |
  728. (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
  729. (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
  730. (port->id << ITCT_HDR_PORT_ID_OFF));
  731. itct->qw0 = cpu_to_le64(qw0);
  732. /* qw1 */
  733. memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
  734. itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
  735. /* qw2 */
  736. if (!dev_is_sata(device))
  737. itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
  738. (0x1ULL << ITCT_HDR_RTOLT_OFF));
  739. }
  740. static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
  741. struct hisi_sas_device *sas_dev)
  742. {
  743. DECLARE_COMPLETION_ONSTACK(completion);
  744. u64 dev_id = sas_dev->device_id;
  745. struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
  746. u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
  747. struct device *dev = hisi_hba->dev;
  748. sas_dev->completion = &completion;
  749. /* clear the itct interrupt state */
  750. if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
  751. hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
  752. ENT_INT_SRC3_ITC_INT_MSK);
  753. /* clear the itct table */
  754. reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
  755. hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
  756. if (!wait_for_completion_timeout(sas_dev->completion,
  757. CLEAR_ITCT_TIMEOUT * HZ)) {
  758. dev_warn(dev, "failed to clear ITCT\n");
  759. return -ETIMEDOUT;
  760. }
  761. memset(itct, 0, sizeof(struct hisi_sas_itct));
  762. return 0;
  763. }
  764. static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
  765. struct domain_device *device)
  766. {
  767. struct hisi_sas_slot *slot, *slot2;
  768. struct hisi_sas_device *sas_dev = device->lldd_dev;
  769. u32 cfg_abt_set_query_iptt;
  770. cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
  771. CFG_ABT_SET_QUERY_IPTT);
  772. list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
  773. cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
  774. cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
  775. (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
  776. hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
  777. cfg_abt_set_query_iptt);
  778. }
  779. cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
  780. hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
  781. cfg_abt_set_query_iptt);
  782. hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
  783. 1 << CFG_ABT_SET_IPTT_DONE_OFF);
  784. }
  785. static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
  786. {
  787. struct device *dev = hisi_hba->dev;
  788. int ret;
  789. u32 val;
  790. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
  791. /* Disable all of the PHYs */
  792. hisi_sas_stop_phys(hisi_hba);
  793. udelay(50);
  794. /* Ensure axi bus idle */
  795. ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
  796. 20000, 1000000);
  797. if (ret) {
  798. dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
  799. return -EIO;
  800. }
  801. if (ACPI_HANDLE(dev)) {
  802. acpi_status s;
  803. s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
  804. if (ACPI_FAILURE(s)) {
  805. dev_err(dev, "Reset failed\n");
  806. return -EIO;
  807. }
  808. } else {
  809. dev_err(dev, "no reset method!\n");
  810. return -EINVAL;
  811. }
  812. return 0;
  813. }
  814. static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
  815. {
  816. struct device *dev = hisi_hba->dev;
  817. struct acpi_device *acpi_dev;
  818. union acpi_object *obj;
  819. guid_t guid;
  820. int rc;
  821. rc = reset_hw_v3_hw(hisi_hba);
  822. if (rc) {
  823. dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
  824. return rc;
  825. }
  826. msleep(100);
  827. init_reg_v3_hw(hisi_hba);
  828. if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
  829. dev_err(dev, "Parse GUID failed\n");
  830. return -EINVAL;
  831. }
  832. /*
  833. * This DSM handles some hardware-related configurations:
  834. * 1. Switch over to MSI error handling in kernel
  835. * 2. BIOS *may* reset some register values through this method
  836. */
  837. obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
  838. DSM_FUNC_ERR_HANDLE_MSI, NULL);
  839. if (!obj)
  840. dev_warn(dev, "can not find DSM method, ignore\n");
  841. else
  842. ACPI_FREE(obj);
  843. acpi_dev = ACPI_COMPANION(dev);
  844. if (!acpi_device_power_manageable(acpi_dev))
  845. dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
  846. return 0;
  847. }
  848. static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  849. {
  850. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  851. cfg |= PHY_CFG_ENA_MSK;
  852. cfg &= ~PHY_CFG_PHY_RST_MSK;
  853. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  854. }
  855. static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  856. {
  857. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  858. u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
  859. static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
  860. BIT(CHL_INT2_RX_CODE_ERR_OFF) |
  861. BIT(CHL_INT2_RX_INVLD_DW_OFF);
  862. u32 state;
  863. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
  864. cfg &= ~PHY_CFG_ENA_MSK;
  865. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  866. mdelay(50);
  867. state = hisi_sas_read32(hisi_hba, PHY_STATE);
  868. if (state & BIT(phy_no)) {
  869. cfg |= PHY_CFG_PHY_RST_MSK;
  870. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  871. }
  872. udelay(1);
  873. hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
  874. hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
  875. hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
  876. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
  877. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
  878. }
  879. static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  880. {
  881. config_id_frame_v3_hw(hisi_hba, phy_no);
  882. config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
  883. enable_phy_v3_hw(hisi_hba, phy_no);
  884. }
  885. static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  886. {
  887. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  888. u32 txid_auto;
  889. hisi_sas_phy_enable(hisi_hba, phy_no, 0);
  890. if (phy->identify.device_type == SAS_END_DEVICE) {
  891. txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
  892. hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
  893. txid_auto | TX_HARDRST_MSK);
  894. }
  895. msleep(100);
  896. hisi_sas_phy_enable(hisi_hba, phy_no, 1);
  897. }
  898. static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
  899. {
  900. return SAS_LINK_RATE_12_0_GBPS;
  901. }
  902. static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
  903. {
  904. int i;
  905. for (i = 0; i < hisi_hba->n_phy; i++) {
  906. struct hisi_sas_phy *phy = &hisi_hba->phy[i];
  907. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  908. if (!sas_phy->phy->enabled)
  909. continue;
  910. hisi_sas_phy_enable(hisi_hba, i, 1);
  911. }
  912. }
  913. static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  914. {
  915. u32 sl_control;
  916. sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  917. sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
  918. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
  919. msleep(1);
  920. sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  921. sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
  922. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
  923. }
  924. static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
  925. {
  926. int i, bitmap = 0;
  927. u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
  928. u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
  929. for (i = 0; i < hisi_hba->n_phy; i++)
  930. if (phy_state & BIT(i))
  931. if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
  932. bitmap |= BIT(i);
  933. return bitmap;
  934. }
  935. static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
  936. {
  937. struct hisi_hba *hisi_hba = dq->hisi_hba;
  938. struct hisi_sas_slot *s, *s1, *s2 = NULL;
  939. int dlvry_queue = dq->id;
  940. int wp;
  941. list_for_each_entry_safe(s, s1, &dq->list, delivery) {
  942. if (!s->ready)
  943. break;
  944. s2 = s;
  945. list_del(&s->delivery);
  946. }
  947. if (!s2)
  948. return;
  949. /*
  950. * Ensure that memories for slots built on other CPUs is observed.
  951. */
  952. smp_rmb();
  953. wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
  954. hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
  955. }
  956. static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
  957. struct hisi_sas_slot *slot,
  958. struct hisi_sas_cmd_hdr *hdr,
  959. struct scatterlist *scatter,
  960. int n_elem)
  961. {
  962. struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
  963. struct scatterlist *sg;
  964. int i;
  965. for_each_sg(scatter, sg, n_elem, i) {
  966. struct hisi_sas_sge *entry = &sge_page->sge[i];
  967. entry->addr = cpu_to_le64(sg_dma_address(sg));
  968. entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
  969. entry->data_len = cpu_to_le32(sg_dma_len(sg));
  970. entry->data_off = 0;
  971. }
  972. hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
  973. hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
  974. }
  975. static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
  976. struct hisi_sas_slot *slot,
  977. struct hisi_sas_cmd_hdr *hdr,
  978. struct scatterlist *scatter,
  979. int n_elem)
  980. {
  981. struct hisi_sas_sge_dif_page *sge_dif_page;
  982. struct scatterlist *sg;
  983. int i;
  984. sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
  985. for_each_sg(scatter, sg, n_elem, i) {
  986. struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
  987. entry->addr = cpu_to_le64(sg_dma_address(sg));
  988. entry->page_ctrl_0 = 0;
  989. entry->page_ctrl_1 = 0;
  990. entry->data_len = cpu_to_le32(sg_dma_len(sg));
  991. entry->data_off = 0;
  992. }
  993. hdr->dif_prd_table_addr =
  994. cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
  995. hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
  996. }
  997. static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
  998. {
  999. unsigned char prot_flags = scsi_cmnd->prot_flags;
  1000. if (prot_flags & SCSI_PROT_REF_CHECK)
  1001. return T10_CHK_APP_TAG_MSK;
  1002. return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
  1003. }
  1004. static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
  1005. struct hisi_sas_protect_iu_v3_hw *prot)
  1006. {
  1007. unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
  1008. unsigned int interval = scsi_prot_interval(scsi_cmnd);
  1009. u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
  1010. switch (prot_op) {
  1011. case SCSI_PROT_READ_INSERT:
  1012. prot->dw0 |= T10_INSRT_EN_MSK;
  1013. prot->lbrtgv = lbrt_chk_val;
  1014. break;
  1015. case SCSI_PROT_READ_STRIP:
  1016. prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
  1017. prot->lbrtcv = lbrt_chk_val;
  1018. prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
  1019. break;
  1020. case SCSI_PROT_READ_PASS:
  1021. prot->dw0 |= T10_CHK_EN_MSK;
  1022. prot->lbrtcv = lbrt_chk_val;
  1023. prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
  1024. break;
  1025. case SCSI_PROT_WRITE_INSERT:
  1026. prot->dw0 |= T10_INSRT_EN_MSK;
  1027. prot->lbrtgv = lbrt_chk_val;
  1028. break;
  1029. case SCSI_PROT_WRITE_STRIP:
  1030. prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
  1031. prot->lbrtcv = lbrt_chk_val;
  1032. break;
  1033. case SCSI_PROT_WRITE_PASS:
  1034. prot->dw0 |= T10_CHK_EN_MSK;
  1035. prot->lbrtcv = lbrt_chk_val;
  1036. prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
  1037. break;
  1038. default:
  1039. WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
  1040. break;
  1041. }
  1042. switch (interval) {
  1043. case 512:
  1044. break;
  1045. case 4096:
  1046. prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
  1047. break;
  1048. case 520:
  1049. prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
  1050. break;
  1051. default:
  1052. WARN(1, "protection interval (0x%x) invalid\n",
  1053. interval);
  1054. break;
  1055. }
  1056. prot->dw0 |= INCR_LBRT_MSK;
  1057. }
  1058. static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
  1059. struct hisi_sas_slot *slot)
  1060. {
  1061. struct sas_task *task = slot->task;
  1062. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  1063. struct domain_device *device = task->dev;
  1064. struct hisi_sas_device *sas_dev = device->lldd_dev;
  1065. struct hisi_sas_port *port = slot->port;
  1066. struct sas_ssp_task *ssp_task = &task->ssp_task;
  1067. struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
  1068. struct hisi_sas_tmf_task *tmf = slot->tmf;
  1069. int has_data = 0, priority = !!tmf;
  1070. unsigned char prot_op;
  1071. u8 *buf_cmd;
  1072. u32 dw1 = 0, dw2 = 0, len = 0;
  1073. hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
  1074. (2 << CMD_HDR_TLR_CTRL_OFF) |
  1075. (port->id << CMD_HDR_PORT_OFF) |
  1076. (priority << CMD_HDR_PRIORITY_OFF) |
  1077. (1 << CMD_HDR_CMD_OFF)); /* ssp */
  1078. dw1 = 1 << CMD_HDR_VDTL_OFF;
  1079. if (tmf) {
  1080. dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
  1081. dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
  1082. } else {
  1083. prot_op = scsi_get_prot_op(scsi_cmnd);
  1084. dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
  1085. switch (scsi_cmnd->sc_data_direction) {
  1086. case DMA_TO_DEVICE:
  1087. has_data = 1;
  1088. dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
  1089. break;
  1090. case DMA_FROM_DEVICE:
  1091. has_data = 1;
  1092. dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
  1093. break;
  1094. default:
  1095. dw1 &= ~CMD_HDR_DIR_MSK;
  1096. }
  1097. }
  1098. /* map itct entry */
  1099. dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
  1100. dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
  1101. + 3) / 4) << CMD_HDR_CFL_OFF) |
  1102. ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
  1103. (2 << CMD_HDR_SG_MOD_OFF);
  1104. hdr->dw2 = cpu_to_le32(dw2);
  1105. hdr->transfer_tags = cpu_to_le32(slot->idx);
  1106. if (has_data) {
  1107. prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
  1108. slot->n_elem);
  1109. if (scsi_prot_sg_count(scsi_cmnd))
  1110. prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
  1111. scsi_prot_sglist(scsi_cmnd),
  1112. slot->n_elem_dif);
  1113. }
  1114. hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
  1115. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  1116. buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
  1117. sizeof(struct ssp_frame_hdr);
  1118. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  1119. if (!tmf) {
  1120. buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
  1121. memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
  1122. } else {
  1123. buf_cmd[10] = tmf->tmf;
  1124. switch (tmf->tmf) {
  1125. case TMF_ABORT_TASK:
  1126. case TMF_QUERY_TASK:
  1127. buf_cmd[12] =
  1128. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  1129. buf_cmd[13] =
  1130. tmf->tag_of_task_to_be_managed & 0xff;
  1131. break;
  1132. default:
  1133. break;
  1134. }
  1135. }
  1136. if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
  1137. struct hisi_sas_protect_iu_v3_hw prot;
  1138. u8 *buf_cmd_prot;
  1139. hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
  1140. dw1 |= CMD_HDR_PIR_MSK;
  1141. buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
  1142. sizeof(struct ssp_frame_hdr) +
  1143. sizeof(struct ssp_command_iu);
  1144. memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
  1145. fill_prot_v3_hw(scsi_cmnd, &prot);
  1146. memcpy(buf_cmd_prot, &prot,
  1147. sizeof(struct hisi_sas_protect_iu_v3_hw));
  1148. /*
  1149. * For READ, we need length of info read to memory, while for
  1150. * WRITE we need length of data written to the disk.
  1151. */
  1152. if (prot_op == SCSI_PROT_WRITE_INSERT ||
  1153. prot_op == SCSI_PROT_READ_INSERT ||
  1154. prot_op == SCSI_PROT_WRITE_PASS ||
  1155. prot_op == SCSI_PROT_READ_PASS) {
  1156. unsigned int interval = scsi_prot_interval(scsi_cmnd);
  1157. unsigned int ilog2_interval = ilog2(interval);
  1158. len = (task->total_xfer_len >> ilog2_interval) * 8;
  1159. }
  1160. }
  1161. hdr->dw1 = cpu_to_le32(dw1);
  1162. hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
  1163. }
  1164. static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
  1165. struct hisi_sas_slot *slot)
  1166. {
  1167. struct sas_task *task = slot->task;
  1168. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  1169. struct domain_device *device = task->dev;
  1170. struct hisi_sas_port *port = slot->port;
  1171. struct scatterlist *sg_req;
  1172. struct hisi_sas_device *sas_dev = device->lldd_dev;
  1173. dma_addr_t req_dma_addr;
  1174. unsigned int req_len;
  1175. /* req */
  1176. sg_req = &task->smp_task.smp_req;
  1177. req_len = sg_dma_len(sg_req);
  1178. req_dma_addr = sg_dma_address(sg_req);
  1179. /* create header */
  1180. /* dw0 */
  1181. hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
  1182. (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
  1183. (2 << CMD_HDR_CMD_OFF)); /* smp */
  1184. /* map itct entry */
  1185. hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
  1186. (1 << CMD_HDR_FRAME_TYPE_OFF) |
  1187. (DIR_NO_DATA << CMD_HDR_DIR_OFF));
  1188. /* dw2 */
  1189. hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
  1190. (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
  1191. CMD_HDR_MRFL_OFF));
  1192. hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
  1193. hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
  1194. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  1195. }
  1196. static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
  1197. struct hisi_sas_slot *slot)
  1198. {
  1199. struct sas_task *task = slot->task;
  1200. struct domain_device *device = task->dev;
  1201. struct domain_device *parent_dev = device->parent;
  1202. struct hisi_sas_device *sas_dev = device->lldd_dev;
  1203. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  1204. struct asd_sas_port *sas_port = device->port;
  1205. struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
  1206. u8 *buf_cmd;
  1207. int has_data = 0, hdr_tag = 0;
  1208. u32 dw1 = 0, dw2 = 0;
  1209. hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
  1210. if (parent_dev && dev_is_expander(parent_dev->dev_type))
  1211. hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
  1212. else
  1213. hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
  1214. switch (task->data_dir) {
  1215. case DMA_TO_DEVICE:
  1216. has_data = 1;
  1217. dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
  1218. break;
  1219. case DMA_FROM_DEVICE:
  1220. has_data = 1;
  1221. dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
  1222. break;
  1223. default:
  1224. dw1 &= ~CMD_HDR_DIR_MSK;
  1225. }
  1226. if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
  1227. (task->ata_task.fis.control & ATA_SRST))
  1228. dw1 |= 1 << CMD_HDR_RESET_OFF;
  1229. dw1 |= (hisi_sas_get_ata_protocol(
  1230. &task->ata_task.fis, task->data_dir))
  1231. << CMD_HDR_FRAME_TYPE_OFF;
  1232. dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
  1233. if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
  1234. dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
  1235. hdr->dw1 = cpu_to_le32(dw1);
  1236. /* dw2 */
  1237. if (task->ata_task.use_ncq) {
  1238. struct ata_queued_cmd *qc = task->uldd_task;
  1239. hdr_tag = qc->tag;
  1240. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  1241. dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
  1242. }
  1243. dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
  1244. 2 << CMD_HDR_SG_MOD_OFF;
  1245. hdr->dw2 = cpu_to_le32(dw2);
  1246. /* dw3 */
  1247. hdr->transfer_tags = cpu_to_le32(slot->idx);
  1248. if (has_data)
  1249. prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
  1250. slot->n_elem);
  1251. hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
  1252. hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
  1253. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  1254. buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
  1255. if (likely(!task->ata_task.device_control_reg_update))
  1256. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  1257. /* fill in command FIS */
  1258. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  1259. }
  1260. static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
  1261. struct hisi_sas_slot *slot,
  1262. int device_id, int abort_flag, int tag_to_abort)
  1263. {
  1264. struct sas_task *task = slot->task;
  1265. struct domain_device *dev = task->dev;
  1266. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  1267. struct hisi_sas_port *port = slot->port;
  1268. /* dw0 */
  1269. hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/
  1270. (port->id << CMD_HDR_PORT_OFF) |
  1271. (dev_is_sata(dev)
  1272. << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
  1273. (abort_flag
  1274. << CMD_HDR_ABORT_FLAG_OFF));
  1275. /* dw1 */
  1276. hdr->dw1 = cpu_to_le32(device_id
  1277. << CMD_HDR_DEV_ID_OFF);
  1278. /* dw7 */
  1279. hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
  1280. hdr->transfer_tags = cpu_to_le32(slot->idx);
  1281. }
  1282. static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
  1283. {
  1284. int i;
  1285. irqreturn_t res;
  1286. u32 context, port_id, link_rate;
  1287. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1288. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1289. struct device *dev = hisi_hba->dev;
  1290. unsigned long flags;
  1291. del_timer(&phy->timer);
  1292. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
  1293. port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
  1294. port_id = (port_id >> (4 * phy_no)) & 0xf;
  1295. link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
  1296. link_rate = (link_rate >> (phy_no * 4)) & 0xf;
  1297. if (port_id == 0xf) {
  1298. dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
  1299. res = IRQ_NONE;
  1300. goto end;
  1301. }
  1302. sas_phy->linkrate = link_rate;
  1303. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  1304. /* Check for SATA dev */
  1305. context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
  1306. if (context & (1 << phy_no)) {
  1307. struct hisi_sas_initial_fis *initial_fis;
  1308. struct dev_to_host_fis *fis;
  1309. u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
  1310. struct Scsi_Host *shost = hisi_hba->shost;
  1311. dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
  1312. initial_fis = &hisi_hba->initial_fis[phy_no];
  1313. fis = &initial_fis->fis;
  1314. /* check ERR bit of Status Register */
  1315. if (fis->status & ATA_ERR) {
  1316. dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
  1317. phy_no, fis->status);
  1318. hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
  1319. res = IRQ_NONE;
  1320. goto end;
  1321. }
  1322. sas_phy->oob_mode = SATA_OOB_MODE;
  1323. attached_sas_addr[0] = 0x50;
  1324. attached_sas_addr[6] = shost->host_no;
  1325. attached_sas_addr[7] = phy_no;
  1326. memcpy(sas_phy->attached_sas_addr,
  1327. attached_sas_addr,
  1328. SAS_ADDR_SIZE);
  1329. memcpy(sas_phy->frame_rcvd, fis,
  1330. sizeof(struct dev_to_host_fis));
  1331. phy->phy_type |= PORT_TYPE_SATA;
  1332. phy->identify.device_type = SAS_SATA_DEV;
  1333. phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
  1334. phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
  1335. } else {
  1336. u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
  1337. struct sas_identify_frame *id =
  1338. (struct sas_identify_frame *)frame_rcvd;
  1339. dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
  1340. for (i = 0; i < 6; i++) {
  1341. u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
  1342. RX_IDAF_DWORD0 + (i * 4));
  1343. frame_rcvd[i] = __swab32(idaf);
  1344. }
  1345. sas_phy->oob_mode = SAS_OOB_MODE;
  1346. memcpy(sas_phy->attached_sas_addr,
  1347. &id->sas_addr,
  1348. SAS_ADDR_SIZE);
  1349. phy->phy_type |= PORT_TYPE_SAS;
  1350. phy->identify.device_type = id->dev_type;
  1351. phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
  1352. if (phy->identify.device_type == SAS_END_DEVICE)
  1353. phy->identify.target_port_protocols =
  1354. SAS_PROTOCOL_SSP;
  1355. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  1356. phy->identify.target_port_protocols =
  1357. SAS_PROTOCOL_SMP;
  1358. }
  1359. phy->port_id = port_id;
  1360. phy->phy_attached = 1;
  1361. hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
  1362. res = IRQ_HANDLED;
  1363. spin_lock_irqsave(&phy->lock, flags);
  1364. if (phy->reset_completion) {
  1365. phy->in_reset = 0;
  1366. complete(phy->reset_completion);
  1367. }
  1368. spin_unlock_irqrestore(&phy->lock, flags);
  1369. end:
  1370. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
  1371. CHL_INT0_SL_PHY_ENABLE_MSK);
  1372. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
  1373. return res;
  1374. }
  1375. static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
  1376. {
  1377. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1378. u32 phy_state, sl_ctrl, txid_auto;
  1379. struct device *dev = hisi_hba->dev;
  1380. atomic_inc(&phy->down_cnt);
  1381. del_timer(&phy->timer);
  1382. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
  1383. phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
  1384. dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
  1385. hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
  1386. sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  1387. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
  1388. sl_ctrl&(~SL_CTA_MSK));
  1389. txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
  1390. hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
  1391. txid_auto | CT3_MSK);
  1392. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
  1393. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
  1394. return IRQ_HANDLED;
  1395. }
  1396. static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
  1397. {
  1398. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1399. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1400. u32 bcast_status;
  1401. hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
  1402. bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
  1403. if ((bcast_status & RX_BCAST_CHG_MSK) &&
  1404. !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
  1405. sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1406. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
  1407. CHL_INT0_SL_RX_BCST_ACK_MSK);
  1408. hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
  1409. return IRQ_HANDLED;
  1410. }
  1411. static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
  1412. {
  1413. struct hisi_hba *hisi_hba = p;
  1414. u32 irq_msk;
  1415. int phy_no = 0;
  1416. irqreturn_t res = IRQ_NONE;
  1417. irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
  1418. & 0x11111111;
  1419. while (irq_msk) {
  1420. if (irq_msk & 1) {
  1421. u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
  1422. CHL_INT0);
  1423. u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
  1424. int rdy = phy_state & (1 << phy_no);
  1425. if (rdy) {
  1426. if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
  1427. /* phy up */
  1428. if (phy_up_v3_hw(phy_no, hisi_hba)
  1429. == IRQ_HANDLED)
  1430. res = IRQ_HANDLED;
  1431. if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
  1432. /* phy bcast */
  1433. if (phy_bcast_v3_hw(phy_no, hisi_hba)
  1434. == IRQ_HANDLED)
  1435. res = IRQ_HANDLED;
  1436. } else {
  1437. if (irq_value & CHL_INT0_NOT_RDY_MSK)
  1438. /* phy down */
  1439. if (phy_down_v3_hw(phy_no, hisi_hba)
  1440. == IRQ_HANDLED)
  1441. res = IRQ_HANDLED;
  1442. }
  1443. }
  1444. irq_msk >>= 4;
  1445. phy_no++;
  1446. }
  1447. return res;
  1448. }
  1449. static const struct hisi_sas_hw_error port_axi_error[] = {
  1450. {
  1451. .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
  1452. .msg = "dmac_tx_ecc_bad_err",
  1453. },
  1454. {
  1455. .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
  1456. .msg = "dmac_rx_ecc_bad_err",
  1457. },
  1458. {
  1459. .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
  1460. .msg = "dma_tx_axi_wr_err",
  1461. },
  1462. {
  1463. .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
  1464. .msg = "dma_tx_axi_rd_err",
  1465. },
  1466. {
  1467. .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
  1468. .msg = "dma_rx_axi_wr_err",
  1469. },
  1470. {
  1471. .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
  1472. .msg = "dma_rx_axi_rd_err",
  1473. },
  1474. {
  1475. .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
  1476. .msg = "dma_tx_fifo_err",
  1477. },
  1478. {
  1479. .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
  1480. .msg = "dma_rx_fifo_err",
  1481. },
  1482. {
  1483. .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
  1484. .msg = "dma_tx_axi_ruser_err",
  1485. },
  1486. {
  1487. .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
  1488. .msg = "dma_rx_axi_ruser_err",
  1489. },
  1490. };
  1491. static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  1492. {
  1493. u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
  1494. u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
  1495. struct device *dev = hisi_hba->dev;
  1496. int i;
  1497. irq_value &= ~irq_msk;
  1498. if (!irq_value)
  1499. return;
  1500. for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
  1501. const struct hisi_sas_hw_error *error = &port_axi_error[i];
  1502. if (!(irq_value & error->irq_msk))
  1503. continue;
  1504. dev_err(dev, "%s error (phy%d 0x%x) found!\n",
  1505. error->msg, phy_no, irq_value);
  1506. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  1507. }
  1508. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
  1509. }
  1510. static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  1511. {
  1512. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1513. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1514. struct sas_phy *sphy = sas_phy->phy;
  1515. unsigned long flags;
  1516. u32 reg_value;
  1517. spin_lock_irqsave(&phy->lock, flags);
  1518. /* loss dword sync */
  1519. reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
  1520. sphy->loss_of_dword_sync_count += reg_value;
  1521. /* phy reset problem */
  1522. reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
  1523. sphy->phy_reset_problem_count += reg_value;
  1524. /* invalid dword */
  1525. reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
  1526. sphy->invalid_dword_count += reg_value;
  1527. /* disparity err */
  1528. reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
  1529. sphy->running_disparity_error_count += reg_value;
  1530. /* code violation error */
  1531. reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
  1532. phy->code_violation_err_count += reg_value;
  1533. spin_unlock_irqrestore(&phy->lock, flags);
  1534. }
  1535. static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  1536. {
  1537. u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
  1538. u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
  1539. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1540. struct pci_dev *pci_dev = hisi_hba->pci_dev;
  1541. struct device *dev = hisi_hba->dev;
  1542. static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
  1543. BIT(CHL_INT2_RX_CODE_ERR_OFF) |
  1544. BIT(CHL_INT2_RX_INVLD_DW_OFF);
  1545. irq_value &= ~irq_msk;
  1546. if (!irq_value)
  1547. return;
  1548. if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
  1549. dev_warn(dev, "phy%d identify timeout\n", phy_no);
  1550. hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
  1551. }
  1552. if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
  1553. u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
  1554. STP_LINK_TIMEOUT_STATE);
  1555. dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
  1556. phy_no, reg_value);
  1557. if (reg_value & BIT(4))
  1558. hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
  1559. }
  1560. if (pci_dev->revision > 0x20 && (irq_value & msk)) {
  1561. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1562. struct sas_phy *sphy = sas_phy->phy;
  1563. phy_get_events_v3_hw(hisi_hba, phy_no);
  1564. if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
  1565. dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
  1566. sphy->invalid_dword_count);
  1567. if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
  1568. dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
  1569. phy->code_violation_err_count);
  1570. if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
  1571. dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
  1572. sphy->running_disparity_error_count);
  1573. }
  1574. if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
  1575. (pci_dev->revision == 0x20)) {
  1576. u32 reg_value;
  1577. int rc;
  1578. rc = hisi_sas_read32_poll_timeout_atomic(
  1579. HILINK_ERR_DFX, reg_value,
  1580. !((reg_value >> 8) & BIT(phy_no)),
  1581. 1000, 10000);
  1582. if (rc)
  1583. hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
  1584. }
  1585. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
  1586. }
  1587. static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
  1588. {
  1589. u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
  1590. if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
  1591. hisi_sas_phy_oob_ready(hisi_hba, phy_no);
  1592. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
  1593. irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
  1594. & (~CHL_INT0_SL_PHY_ENABLE_MSK)
  1595. & (~CHL_INT0_NOT_RDY_MSK));
  1596. }
  1597. static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
  1598. {
  1599. struct hisi_hba *hisi_hba = p;
  1600. u32 irq_msk;
  1601. int phy_no = 0;
  1602. irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
  1603. & CHNL_INT_STS_MSK;
  1604. while (irq_msk) {
  1605. if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
  1606. handle_chl_int0_v3_hw(hisi_hba, phy_no);
  1607. if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
  1608. handle_chl_int1_v3_hw(hisi_hba, phy_no);
  1609. if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
  1610. handle_chl_int2_v3_hw(hisi_hba, phy_no);
  1611. irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
  1612. phy_no++;
  1613. }
  1614. return IRQ_HANDLED;
  1615. }
  1616. static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
  1617. {
  1618. .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
  1619. .msk = HGC_DQE_ECC_MB_ADDR_MSK,
  1620. .shift = HGC_DQE_ECC_MB_ADDR_OFF,
  1621. .msg = "hgc_dqe_eccbad_intr",
  1622. .reg = HGC_DQE_ECC_ADDR,
  1623. },
  1624. {
  1625. .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
  1626. .msk = HGC_IOST_ECC_MB_ADDR_MSK,
  1627. .shift = HGC_IOST_ECC_MB_ADDR_OFF,
  1628. .msg = "hgc_iost_eccbad_intr",
  1629. .reg = HGC_IOST_ECC_ADDR,
  1630. },
  1631. {
  1632. .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
  1633. .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
  1634. .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
  1635. .msg = "hgc_itct_eccbad_intr",
  1636. .reg = HGC_ITCT_ECC_ADDR,
  1637. },
  1638. {
  1639. .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
  1640. .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
  1641. .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
  1642. .msg = "hgc_iostl_eccbad_intr",
  1643. .reg = HGC_LM_DFX_STATUS2,
  1644. },
  1645. {
  1646. .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
  1647. .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
  1648. .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
  1649. .msg = "hgc_itctl_eccbad_intr",
  1650. .reg = HGC_LM_DFX_STATUS2,
  1651. },
  1652. {
  1653. .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
  1654. .msk = HGC_CQE_ECC_MB_ADDR_MSK,
  1655. .shift = HGC_CQE_ECC_MB_ADDR_OFF,
  1656. .msg = "hgc_cqe_eccbad_intr",
  1657. .reg = HGC_CQE_ECC_ADDR,
  1658. },
  1659. {
  1660. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
  1661. .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
  1662. .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
  1663. .msg = "rxm_mem0_eccbad_intr",
  1664. .reg = HGC_RXM_DFX_STATUS14,
  1665. },
  1666. {
  1667. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
  1668. .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
  1669. .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
  1670. .msg = "rxm_mem1_eccbad_intr",
  1671. .reg = HGC_RXM_DFX_STATUS14,
  1672. },
  1673. {
  1674. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
  1675. .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
  1676. .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
  1677. .msg = "rxm_mem2_eccbad_intr",
  1678. .reg = HGC_RXM_DFX_STATUS14,
  1679. },
  1680. {
  1681. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
  1682. .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
  1683. .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
  1684. .msg = "rxm_mem3_eccbad_intr",
  1685. .reg = HGC_RXM_DFX_STATUS15,
  1686. },
  1687. {
  1688. .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
  1689. .msk = AM_ROB_ECC_ERR_ADDR_MSK,
  1690. .shift = AM_ROB_ECC_ERR_ADDR_OFF,
  1691. .msg = "ooo_ram_eccbad_intr",
  1692. .reg = AM_ROB_ECC_ERR_ADDR,
  1693. },
  1694. };
  1695. static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
  1696. u32 irq_value)
  1697. {
  1698. struct device *dev = hisi_hba->dev;
  1699. const struct hisi_sas_hw_error *ecc_error;
  1700. u32 val;
  1701. int i;
  1702. for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
  1703. ecc_error = &multi_bit_ecc_errors[i];
  1704. if (irq_value & ecc_error->irq_msk) {
  1705. val = hisi_sas_read32(hisi_hba, ecc_error->reg);
  1706. val &= ecc_error->msk;
  1707. val >>= ecc_error->shift;
  1708. dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
  1709. ecc_error->msg, irq_value, val);
  1710. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  1711. }
  1712. }
  1713. }
  1714. static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
  1715. {
  1716. u32 irq_value, irq_msk;
  1717. irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
  1718. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
  1719. irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
  1720. if (irq_value)
  1721. multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
  1722. hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
  1723. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
  1724. }
  1725. static const struct hisi_sas_hw_error axi_error[] = {
  1726. { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
  1727. { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
  1728. { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
  1729. { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
  1730. { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
  1731. { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
  1732. { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
  1733. { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
  1734. {}
  1735. };
  1736. static const struct hisi_sas_hw_error fifo_error[] = {
  1737. { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
  1738. { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
  1739. { .msk = BIT(10), .msg = "GETDQE_FIFO" },
  1740. { .msk = BIT(11), .msg = "CMDP_FIFO" },
  1741. { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
  1742. {}
  1743. };
  1744. static const struct hisi_sas_hw_error fatal_axi_error[] = {
  1745. {
  1746. .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
  1747. .msg = "write pointer and depth",
  1748. },
  1749. {
  1750. .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
  1751. .msg = "iptt no match slot",
  1752. },
  1753. {
  1754. .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
  1755. .msg = "read pointer and depth",
  1756. },
  1757. {
  1758. .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
  1759. .reg = HGC_AXI_FIFO_ERR_INFO,
  1760. .sub = axi_error,
  1761. },
  1762. {
  1763. .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
  1764. .reg = HGC_AXI_FIFO_ERR_INFO,
  1765. .sub = fifo_error,
  1766. },
  1767. {
  1768. .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
  1769. .msg = "LM add/fetch list",
  1770. },
  1771. {
  1772. .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
  1773. .msg = "SAS_HGC_ABT fetch LM list",
  1774. },
  1775. {
  1776. .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
  1777. .msg = "read dqe poison",
  1778. },
  1779. {
  1780. .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
  1781. .msg = "read iost poison",
  1782. },
  1783. {
  1784. .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
  1785. .msg = "read itct poison",
  1786. },
  1787. {
  1788. .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
  1789. .msg = "read itct ncq poison",
  1790. },
  1791. };
  1792. static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
  1793. {
  1794. u32 irq_value, irq_msk;
  1795. struct hisi_hba *hisi_hba = p;
  1796. struct device *dev = hisi_hba->dev;
  1797. struct pci_dev *pdev = hisi_hba->pci_dev;
  1798. int i;
  1799. irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
  1800. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
  1801. irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
  1802. irq_value &= ~irq_msk;
  1803. for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
  1804. const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
  1805. if (!(irq_value & error->irq_msk))
  1806. continue;
  1807. if (error->sub) {
  1808. const struct hisi_sas_hw_error *sub = error->sub;
  1809. u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
  1810. for (; sub->msk || sub->msg; sub++) {
  1811. if (!(err_value & sub->msk))
  1812. continue;
  1813. dev_err(dev, "%s error (0x%x) found!\n",
  1814. sub->msg, irq_value);
  1815. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  1816. }
  1817. } else {
  1818. dev_err(dev, "%s error (0x%x) found!\n",
  1819. error->msg, irq_value);
  1820. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  1821. }
  1822. if (pdev->revision < 0x21) {
  1823. u32 reg_val;
  1824. reg_val = hisi_sas_read32(hisi_hba,
  1825. AXI_MASTER_CFG_BASE +
  1826. AM_CTRL_GLOBAL);
  1827. reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
  1828. hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
  1829. AM_CTRL_GLOBAL, reg_val);
  1830. }
  1831. }
  1832. fatal_ecc_int_v3_hw(hisi_hba);
  1833. if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
  1834. u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
  1835. u32 dev_id = reg_val & ITCT_DEV_MSK;
  1836. struct hisi_sas_device *sas_dev =
  1837. &hisi_hba->devices[dev_id];
  1838. hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
  1839. dev_dbg(dev, "clear ITCT ok\n");
  1840. complete(sas_dev->completion);
  1841. }
  1842. hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
  1843. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
  1844. return IRQ_HANDLED;
  1845. }
  1846. static void
  1847. slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
  1848. struct hisi_sas_slot *slot)
  1849. {
  1850. struct task_status_struct *ts = &task->task_status;
  1851. struct hisi_sas_complete_v3_hdr *complete_queue =
  1852. hisi_hba->complete_hdr[slot->cmplt_queue];
  1853. struct hisi_sas_complete_v3_hdr *complete_hdr =
  1854. &complete_queue[slot->cmplt_queue_slot];
  1855. struct hisi_sas_err_record_v3 *record =
  1856. hisi_sas_status_buf_addr_mem(slot);
  1857. u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
  1858. u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
  1859. u32 dw3 = le32_to_cpu(complete_hdr->dw3);
  1860. switch (task->task_proto) {
  1861. case SAS_PROTOCOL_SSP:
  1862. if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
  1863. ts->residual = trans_tx_fail_type;
  1864. ts->stat = SAS_DATA_UNDERRUN;
  1865. } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
  1866. ts->stat = SAS_QUEUE_FULL;
  1867. slot->abort = 1;
  1868. } else {
  1869. ts->stat = SAS_OPEN_REJECT;
  1870. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1871. }
  1872. break;
  1873. case SAS_PROTOCOL_SATA:
  1874. case SAS_PROTOCOL_STP:
  1875. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1876. if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
  1877. ts->residual = trans_tx_fail_type;
  1878. ts->stat = SAS_DATA_UNDERRUN;
  1879. } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
  1880. ts->stat = SAS_PHY_DOWN;
  1881. slot->abort = 1;
  1882. } else {
  1883. ts->stat = SAS_OPEN_REJECT;
  1884. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1885. }
  1886. hisi_sas_sata_done(task, slot);
  1887. break;
  1888. case SAS_PROTOCOL_SMP:
  1889. ts->stat = SAM_STAT_CHECK_CONDITION;
  1890. break;
  1891. default:
  1892. break;
  1893. }
  1894. }
  1895. static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
  1896. struct hisi_sas_slot *slot)
  1897. {
  1898. struct sas_task *task = slot->task;
  1899. struct hisi_sas_device *sas_dev;
  1900. struct device *dev = hisi_hba->dev;
  1901. struct task_status_struct *ts;
  1902. struct domain_device *device;
  1903. struct sas_ha_struct *ha;
  1904. struct hisi_sas_complete_v3_hdr *complete_queue =
  1905. hisi_hba->complete_hdr[slot->cmplt_queue];
  1906. struct hisi_sas_complete_v3_hdr *complete_hdr =
  1907. &complete_queue[slot->cmplt_queue_slot];
  1908. unsigned long flags;
  1909. bool is_internal = slot->is_internal;
  1910. u32 dw0, dw1, dw3;
  1911. if (unlikely(!task || !task->lldd_task || !task->dev))
  1912. return;
  1913. ts = &task->task_status;
  1914. device = task->dev;
  1915. ha = device->port->ha;
  1916. sas_dev = device->lldd_dev;
  1917. spin_lock_irqsave(&task->task_state_lock, flags);
  1918. task->task_state_flags &=
  1919. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1920. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1921. memset(ts, 0, sizeof(*ts));
  1922. ts->resp = SAS_TASK_COMPLETE;
  1923. if (unlikely(!sas_dev)) {
  1924. dev_dbg(dev, "slot complete: port has not device\n");
  1925. ts->stat = SAS_PHY_DOWN;
  1926. goto out;
  1927. }
  1928. dw0 = le32_to_cpu(complete_hdr->dw0);
  1929. dw1 = le32_to_cpu(complete_hdr->dw1);
  1930. dw3 = le32_to_cpu(complete_hdr->dw3);
  1931. /*
  1932. * Use SAS+TMF status codes
  1933. */
  1934. switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
  1935. case STAT_IO_ABORTED:
  1936. /* this IO has been aborted by abort command */
  1937. ts->stat = SAS_ABORTED_TASK;
  1938. goto out;
  1939. case STAT_IO_COMPLETE:
  1940. /* internal abort command complete */
  1941. ts->stat = TMF_RESP_FUNC_SUCC;
  1942. goto out;
  1943. case STAT_IO_NO_DEVICE:
  1944. ts->stat = TMF_RESP_FUNC_COMPLETE;
  1945. goto out;
  1946. case STAT_IO_NOT_VALID:
  1947. /*
  1948. * abort single IO, the controller can't find the IO
  1949. */
  1950. ts->stat = TMF_RESP_FUNC_FAILED;
  1951. goto out;
  1952. default:
  1953. break;
  1954. }
  1955. /* check for erroneous completion */
  1956. if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
  1957. u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
  1958. slot_err_v3_hw(hisi_hba, task, slot);
  1959. if (ts->stat != SAS_DATA_UNDERRUN)
  1960. dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
  1961. slot->idx, task, sas_dev->device_id,
  1962. dw0, dw1, complete_hdr->act, dw3,
  1963. error_info[0], error_info[1],
  1964. error_info[2], error_info[3]);
  1965. if (unlikely(slot->abort)) {
  1966. sas_task_abort(task);
  1967. return;
  1968. }
  1969. goto out;
  1970. }
  1971. switch (task->task_proto) {
  1972. case SAS_PROTOCOL_SSP: {
  1973. struct ssp_response_iu *iu =
  1974. hisi_sas_status_buf_addr_mem(slot) +
  1975. sizeof(struct hisi_sas_err_record);
  1976. sas_ssp_task_response(dev, task, iu);
  1977. break;
  1978. }
  1979. case SAS_PROTOCOL_SMP: {
  1980. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1981. void *to = page_address(sg_page(sg_resp));
  1982. ts->stat = SAM_STAT_GOOD;
  1983. dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
  1984. DMA_TO_DEVICE);
  1985. memcpy(to + sg_resp->offset,
  1986. hisi_sas_status_buf_addr_mem(slot) +
  1987. sizeof(struct hisi_sas_err_record),
  1988. sg_resp->length);
  1989. break;
  1990. }
  1991. case SAS_PROTOCOL_SATA:
  1992. case SAS_PROTOCOL_STP:
  1993. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1994. ts->stat = SAM_STAT_GOOD;
  1995. hisi_sas_sata_done(task, slot);
  1996. break;
  1997. default:
  1998. ts->stat = SAM_STAT_CHECK_CONDITION;
  1999. break;
  2000. }
  2001. if (!slot->port->port_attached) {
  2002. dev_warn(dev, "slot complete: port %d has removed\n",
  2003. slot->port->sas_port.id);
  2004. ts->stat = SAS_PHY_DOWN;
  2005. }
  2006. out:
  2007. spin_lock_irqsave(&task->task_state_lock, flags);
  2008. if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
  2009. spin_unlock_irqrestore(&task->task_state_lock, flags);
  2010. dev_info(dev, "slot complete: task(%pK) aborted\n", task);
  2011. return;
  2012. }
  2013. task->task_state_flags |= SAS_TASK_STATE_DONE;
  2014. spin_unlock_irqrestore(&task->task_state_lock, flags);
  2015. hisi_sas_slot_task_free(hisi_hba, task, slot);
  2016. if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
  2017. spin_lock_irqsave(&device->done_lock, flags);
  2018. if (test_bit(SAS_HA_FROZEN, &ha->state)) {
  2019. spin_unlock_irqrestore(&device->done_lock, flags);
  2020. dev_info(dev, "slot complete: task(%pK) ignored\n ",
  2021. task);
  2022. return;
  2023. }
  2024. spin_unlock_irqrestore(&device->done_lock, flags);
  2025. }
  2026. if (task->task_done)
  2027. task->task_done(task);
  2028. }
  2029. static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
  2030. {
  2031. struct hisi_sas_cq *cq = p;
  2032. struct hisi_hba *hisi_hba = cq->hisi_hba;
  2033. struct hisi_sas_slot *slot;
  2034. struct hisi_sas_complete_v3_hdr *complete_queue;
  2035. u32 rd_point = cq->rd_point, wr_point;
  2036. int queue = cq->id;
  2037. complete_queue = hisi_hba->complete_hdr[queue];
  2038. wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
  2039. (0x14 * queue));
  2040. while (rd_point != wr_point) {
  2041. struct hisi_sas_complete_v3_hdr *complete_hdr;
  2042. struct device *dev = hisi_hba->dev;
  2043. u32 dw1;
  2044. int iptt;
  2045. complete_hdr = &complete_queue[rd_point];
  2046. dw1 = le32_to_cpu(complete_hdr->dw1);
  2047. iptt = dw1 & CMPLT_HDR_IPTT_MSK;
  2048. if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
  2049. slot = &hisi_hba->slot_info[iptt];
  2050. slot->cmplt_queue_slot = rd_point;
  2051. slot->cmplt_queue = queue;
  2052. slot_complete_v3_hw(hisi_hba, slot);
  2053. } else
  2054. dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
  2055. if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
  2056. rd_point = 0;
  2057. }
  2058. /* update rd_point */
  2059. cq->rd_point = rd_point;
  2060. hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
  2061. return IRQ_HANDLED;
  2062. }
  2063. static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
  2064. {
  2065. struct hisi_sas_cq *cq = p;
  2066. struct hisi_hba *hisi_hba = cq->hisi_hba;
  2067. int queue = cq->id;
  2068. hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
  2069. return IRQ_WAKE_THREAD;
  2070. }
  2071. static void hisi_sas_v3_free_vectors(void *data)
  2072. {
  2073. struct pci_dev *pdev = data;
  2074. pci_free_irq_vectors(pdev);
  2075. }
  2076. static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
  2077. {
  2078. int vectors;
  2079. int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
  2080. struct Scsi_Host *shost = hisi_hba->shost;
  2081. struct pci_dev *pdev = hisi_hba->pci_dev;
  2082. struct irq_affinity desc = {
  2083. .pre_vectors = BASE_VECTORS_V3_HW,
  2084. };
  2085. min_msi = MIN_AFFINE_VECTORS_V3_HW;
  2086. vectors = pci_alloc_irq_vectors_affinity(pdev,
  2087. min_msi, max_msi,
  2088. PCI_IRQ_MSI |
  2089. PCI_IRQ_AFFINITY,
  2090. &desc);
  2091. if (vectors < 0)
  2092. return -ENOENT;
  2093. hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
  2094. shost->nr_hw_queues = hisi_hba->cq_nvecs;
  2095. devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
  2096. return 0;
  2097. }
  2098. static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
  2099. {
  2100. struct device *dev = hisi_hba->dev;
  2101. struct pci_dev *pdev = hisi_hba->pci_dev;
  2102. int rc, i;
  2103. rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
  2104. int_phy_up_down_bcast_v3_hw, 0,
  2105. DRV_NAME " phy", hisi_hba);
  2106. if (rc) {
  2107. dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
  2108. return -ENOENT;
  2109. }
  2110. rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
  2111. int_chnl_int_v3_hw, 0,
  2112. DRV_NAME " channel", hisi_hba);
  2113. if (rc) {
  2114. dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
  2115. return -ENOENT;
  2116. }
  2117. rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
  2118. fatal_axi_int_v3_hw, 0,
  2119. DRV_NAME " fatal", hisi_hba);
  2120. if (rc) {
  2121. dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
  2122. return -ENOENT;
  2123. }
  2124. if (hisi_sas_intr_conv)
  2125. dev_info(dev, "Enable interrupt converge\n");
  2126. for (i = 0; i < hisi_hba->cq_nvecs; i++) {
  2127. struct hisi_sas_cq *cq = &hisi_hba->cq[i];
  2128. int nr = hisi_sas_intr_conv ? 16 : 16 + i;
  2129. unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
  2130. IRQF_ONESHOT;
  2131. cq->irq_no = pci_irq_vector(pdev, nr);
  2132. rc = devm_request_threaded_irq(dev, cq->irq_no,
  2133. cq_interrupt_v3_hw,
  2134. cq_thread_v3_hw,
  2135. irqflags,
  2136. DRV_NAME " cq", cq);
  2137. if (rc) {
  2138. dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
  2139. i, rc);
  2140. return -ENOENT;
  2141. }
  2142. cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
  2143. if (!cq->irq_mask) {
  2144. dev_err(dev, "could not get cq%d irq affinity!\n", i);
  2145. return -ENOENT;
  2146. }
  2147. }
  2148. return 0;
  2149. }
  2150. static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
  2151. {
  2152. int rc;
  2153. rc = hw_init_v3_hw(hisi_hba);
  2154. if (rc)
  2155. return rc;
  2156. rc = interrupt_init_v3_hw(hisi_hba);
  2157. if (rc)
  2158. return rc;
  2159. return 0;
  2160. }
  2161. static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
  2162. struct sas_phy_linkrates *r)
  2163. {
  2164. enum sas_linkrate max = r->maximum_linkrate;
  2165. u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
  2166. PROG_PHY_LINK_RATE);
  2167. prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
  2168. prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
  2169. hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
  2170. prog_phy_link_rate);
  2171. }
  2172. static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
  2173. {
  2174. struct pci_dev *pdev = hisi_hba->pci_dev;
  2175. int i;
  2176. synchronize_irq(pci_irq_vector(pdev, 1));
  2177. synchronize_irq(pci_irq_vector(pdev, 2));
  2178. synchronize_irq(pci_irq_vector(pdev, 11));
  2179. for (i = 0; i < hisi_hba->queue_count; i++)
  2180. hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
  2181. for (i = 0; i < hisi_hba->cq_nvecs; i++)
  2182. synchronize_irq(pci_irq_vector(pdev, i + 16));
  2183. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
  2184. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
  2185. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
  2186. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
  2187. for (i = 0; i < hisi_hba->n_phy; i++) {
  2188. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
  2189. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
  2190. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
  2191. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
  2192. hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
  2193. }
  2194. }
  2195. static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
  2196. {
  2197. return hisi_sas_read32(hisi_hba, PHY_STATE);
  2198. }
  2199. static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
  2200. {
  2201. struct device *dev = hisi_hba->dev;
  2202. u32 status, reg_val;
  2203. int rc;
  2204. interrupt_disable_v3_hw(hisi_hba);
  2205. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
  2206. hisi_sas_stop_phys(hisi_hba);
  2207. mdelay(10);
  2208. reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
  2209. AM_CTRL_GLOBAL);
  2210. reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
  2211. hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
  2212. AM_CTRL_GLOBAL, reg_val);
  2213. /* wait until bus idle */
  2214. rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
  2215. AM_CURR_TRANS_RETURN, status,
  2216. status == 0x3, 10, 100);
  2217. if (rc) {
  2218. dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
  2219. return rc;
  2220. }
  2221. return 0;
  2222. }
  2223. static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
  2224. {
  2225. struct device *dev = hisi_hba->dev;
  2226. int rc;
  2227. rc = disable_host_v3_hw(hisi_hba);
  2228. if (rc) {
  2229. dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
  2230. return rc;
  2231. }
  2232. hisi_sas_init_mem(hisi_hba);
  2233. return hw_init_v3_hw(hisi_hba);
  2234. }
  2235. static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
  2236. u8 reg_index, u8 reg_count, u8 *write_data)
  2237. {
  2238. struct device *dev = hisi_hba->dev;
  2239. u32 *data = (u32 *)write_data;
  2240. int i;
  2241. switch (reg_type) {
  2242. case SAS_GPIO_REG_TX:
  2243. if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
  2244. dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
  2245. reg_index, reg_index + reg_count - 1);
  2246. return -EINVAL;
  2247. }
  2248. for (i = 0; i < reg_count; i++)
  2249. hisi_sas_write32(hisi_hba,
  2250. SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
  2251. data[i]);
  2252. break;
  2253. default:
  2254. dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
  2255. reg_type);
  2256. return -EINVAL;
  2257. }
  2258. return 0;
  2259. }
  2260. static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
  2261. int delay_ms, int timeout_ms)
  2262. {
  2263. struct device *dev = hisi_hba->dev;
  2264. int entries, entries_old = 0, time;
  2265. for (time = 0; time < timeout_ms; time += delay_ms) {
  2266. entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
  2267. if (entries == entries_old)
  2268. break;
  2269. entries_old = entries;
  2270. msleep(delay_ms);
  2271. }
  2272. if (time >= timeout_ms) {
  2273. dev_dbg(dev, "Wait commands complete timeout!\n");
  2274. return;
  2275. }
  2276. dev_dbg(dev, "wait commands complete %dms\n", time);
  2277. }
  2278. static ssize_t intr_conv_v3_hw_show(struct device *dev,
  2279. struct device_attribute *attr, char *buf)
  2280. {
  2281. return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
  2282. }
  2283. static DEVICE_ATTR_RO(intr_conv_v3_hw);
  2284. static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
  2285. {
  2286. /* config those registers between enable and disable PHYs */
  2287. hisi_sas_stop_phys(hisi_hba);
  2288. if (hisi_hba->intr_coal_ticks == 0 ||
  2289. hisi_hba->intr_coal_count == 0) {
  2290. hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
  2291. hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
  2292. hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
  2293. } else {
  2294. hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
  2295. hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
  2296. hisi_hba->intr_coal_ticks);
  2297. hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
  2298. hisi_hba->intr_coal_count);
  2299. }
  2300. phys_init_v3_hw(hisi_hba);
  2301. }
  2302. static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
  2303. struct device_attribute *attr,
  2304. char *buf)
  2305. {
  2306. struct Scsi_Host *shost = class_to_shost(dev);
  2307. struct hisi_hba *hisi_hba = shost_priv(shost);
  2308. return scnprintf(buf, PAGE_SIZE, "%u\n",
  2309. hisi_hba->intr_coal_ticks);
  2310. }
  2311. static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
  2312. struct device_attribute *attr,
  2313. const char *buf, size_t count)
  2314. {
  2315. struct Scsi_Host *shost = class_to_shost(dev);
  2316. struct hisi_hba *hisi_hba = shost_priv(shost);
  2317. u32 intr_coal_ticks;
  2318. int ret;
  2319. ret = kstrtou32(buf, 10, &intr_coal_ticks);
  2320. if (ret) {
  2321. dev_err(dev, "Input data of interrupt coalesce unmatch\n");
  2322. return -EINVAL;
  2323. }
  2324. if (intr_coal_ticks >= BIT(24)) {
  2325. dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
  2326. return -EINVAL;
  2327. }
  2328. hisi_hba->intr_coal_ticks = intr_coal_ticks;
  2329. config_intr_coal_v3_hw(hisi_hba);
  2330. return count;
  2331. }
  2332. static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
  2333. static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
  2334. struct device_attribute
  2335. *attr, char *buf)
  2336. {
  2337. struct Scsi_Host *shost = class_to_shost(dev);
  2338. struct hisi_hba *hisi_hba = shost_priv(shost);
  2339. return scnprintf(buf, PAGE_SIZE, "%u\n",
  2340. hisi_hba->intr_coal_count);
  2341. }
  2342. static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
  2343. struct device_attribute
  2344. *attr, const char *buf, size_t count)
  2345. {
  2346. struct Scsi_Host *shost = class_to_shost(dev);
  2347. struct hisi_hba *hisi_hba = shost_priv(shost);
  2348. u32 intr_coal_count;
  2349. int ret;
  2350. ret = kstrtou32(buf, 10, &intr_coal_count);
  2351. if (ret) {
  2352. dev_err(dev, "Input data of interrupt coalesce unmatch\n");
  2353. return -EINVAL;
  2354. }
  2355. if (intr_coal_count >= BIT(8)) {
  2356. dev_err(dev, "intr_coal_count must be less than 2^8!\n");
  2357. return -EINVAL;
  2358. }
  2359. hisi_hba->intr_coal_count = intr_coal_count;
  2360. config_intr_coal_v3_hw(hisi_hba);
  2361. return count;
  2362. }
  2363. static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
  2364. static int slave_configure_v3_hw(struct scsi_device *sdev)
  2365. {
  2366. struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
  2367. struct domain_device *ddev = sdev_to_domain_dev(sdev);
  2368. struct hisi_hba *hisi_hba = shost_priv(shost);
  2369. struct device *dev = hisi_hba->dev;
  2370. int ret = sas_slave_configure(sdev);
  2371. if (ret)
  2372. return ret;
  2373. if (!dev_is_sata(ddev))
  2374. sas_change_queue_depth(sdev, 64);
  2375. if (sdev->type == TYPE_ENCLOSURE)
  2376. return 0;
  2377. if (!device_link_add(&sdev->sdev_gendev, dev,
  2378. DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
  2379. if (pm_runtime_enabled(dev)) {
  2380. dev_info(dev, "add device link failed, disable runtime PM for the host\n");
  2381. pm_runtime_disable(dev);
  2382. }
  2383. }
  2384. return 0;
  2385. }
  2386. static struct device_attribute *host_attrs_v3_hw[] = {
  2387. &dev_attr_phy_event_threshold,
  2388. &dev_attr_intr_conv_v3_hw,
  2389. &dev_attr_intr_coal_ticks_v3_hw,
  2390. &dev_attr_intr_coal_count_v3_hw,
  2391. NULL
  2392. };
  2393. static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
  2394. HISI_SAS_DEBUGFS_REG(PHY_CFG),
  2395. HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
  2396. HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
  2397. HISI_SAS_DEBUGFS_REG(PHY_CTRL),
  2398. HISI_SAS_DEBUGFS_REG(SL_CFG),
  2399. HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
  2400. HISI_SAS_DEBUGFS_REG(SL_CONTROL),
  2401. HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
  2402. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
  2403. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
  2404. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
  2405. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
  2406. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
  2407. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
  2408. HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
  2409. HISI_SAS_DEBUGFS_REG(TXID_AUTO),
  2410. HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
  2411. HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
  2412. HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
  2413. HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
  2414. HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
  2415. HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
  2416. HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
  2417. HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
  2418. HISI_SAS_DEBUGFS_REG(CHL_INT0),
  2419. HISI_SAS_DEBUGFS_REG(CHL_INT1),
  2420. HISI_SAS_DEBUGFS_REG(CHL_INT2),
  2421. HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
  2422. HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
  2423. HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
  2424. HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
  2425. HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
  2426. HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
  2427. HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
  2428. HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
  2429. HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
  2430. HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
  2431. HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
  2432. HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
  2433. HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
  2434. HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
  2435. HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
  2436. HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
  2437. HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
  2438. HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
  2439. HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
  2440. HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
  2441. {}
  2442. };
  2443. static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
  2444. .lu = debugfs_port_reg_lu,
  2445. .count = 0x100,
  2446. .base_off = PORT_BASE,
  2447. .read_port_reg = hisi_sas_phy_read32,
  2448. };
  2449. static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
  2450. HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
  2451. HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
  2452. HISI_SAS_DEBUGFS_REG(PHY_STATE),
  2453. HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
  2454. HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
  2455. HISI_SAS_DEBUGFS_REG(ITCT_CLR),
  2456. HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
  2457. HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
  2458. HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
  2459. HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
  2460. HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
  2461. HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
  2462. HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
  2463. HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
  2464. HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
  2465. HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
  2466. HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
  2467. HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
  2468. HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
  2469. HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
  2470. HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
  2471. HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
  2472. HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
  2473. HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
  2474. HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
  2475. HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
  2476. HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
  2477. HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
  2478. HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
  2479. HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
  2480. HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
  2481. HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
  2482. HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
  2483. HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
  2484. HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
  2485. HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
  2486. HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
  2487. HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
  2488. HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
  2489. HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
  2490. HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
  2491. HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
  2492. HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
  2493. HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
  2494. HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
  2495. HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
  2496. HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
  2497. HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
  2498. HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
  2499. HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
  2500. HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
  2501. HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
  2502. HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
  2503. HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
  2504. HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
  2505. HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
  2506. HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
  2507. HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
  2508. HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
  2509. HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
  2510. HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
  2511. HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
  2512. HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
  2513. {}
  2514. };
  2515. static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
  2516. .lu = debugfs_global_reg_lu,
  2517. .count = 0x800,
  2518. .read_global_reg = hisi_sas_read32,
  2519. };
  2520. static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
  2521. HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
  2522. HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
  2523. HISI_SAS_DEBUGFS_REG(AXI_CFG),
  2524. HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
  2525. {}
  2526. };
  2527. static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
  2528. .lu = debugfs_axi_reg_lu,
  2529. .count = 0x61,
  2530. .base_off = AXI_MASTER_CFG_BASE,
  2531. .read_global_reg = hisi_sas_read32,
  2532. };
  2533. static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
  2534. HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
  2535. HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
  2536. HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
  2537. HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
  2538. HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
  2539. HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
  2540. HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
  2541. {}
  2542. };
  2543. static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
  2544. .lu = debugfs_ras_reg_lu,
  2545. .count = 0x10,
  2546. .base_off = RAS_BASE,
  2547. .read_global_reg = hisi_sas_read32,
  2548. };
  2549. static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
  2550. {
  2551. set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
  2552. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
  2553. wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
  2554. hisi_sas_sync_irqs(hisi_hba);
  2555. }
  2556. static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
  2557. {
  2558. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
  2559. (u32)((1ULL << hisi_hba->queue_count) - 1));
  2560. clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
  2561. }
  2562. static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
  2563. enum hisi_sas_debugfs_cache_type type,
  2564. u32 *cache)
  2565. {
  2566. u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
  2567. HISI_SAS_IOST_ITCT_CACHE_NUM;
  2568. struct device *dev = hisi_hba->dev;
  2569. u32 *buf = cache;
  2570. u32 i, val;
  2571. hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
  2572. for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
  2573. val = hisi_sas_read32(hisi_hba, TAB_DFX);
  2574. if (val == 0xffffffff)
  2575. break;
  2576. }
  2577. if (val != 0xffffffff) {
  2578. dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
  2579. return;
  2580. }
  2581. memset(buf, 0, cache_dw_size * 4);
  2582. buf[0] = val;
  2583. for (i = 1; i < cache_dw_size; i++)
  2584. buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
  2585. }
  2586. static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
  2587. {
  2588. u32 reg_val;
  2589. int phy_no = hisi_hba->debugfs_bist_phy_no;
  2590. int i;
  2591. /* disable PHY */
  2592. hisi_sas_phy_enable(hisi_hba, phy_no, 0);
  2593. /* update FFE */
  2594. for (i = 0; i < FFE_CFG_MAX; i++)
  2595. hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
  2596. hisi_hba->debugfs_bist_ffe[phy_no][i]);
  2597. /* disable ALOS */
  2598. reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
  2599. reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
  2600. hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
  2601. }
  2602. static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
  2603. {
  2604. u32 reg_val;
  2605. int phy_no = hisi_hba->debugfs_bist_phy_no;
  2606. /* disable loopback */
  2607. reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
  2608. reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
  2609. CFG_BIST_TEST_MSK);
  2610. hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
  2611. /* enable ALOS */
  2612. reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
  2613. reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
  2614. hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
  2615. /* restore the linkrate */
  2616. reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
  2617. /* init OOB link rate as 1.5 Gbits */
  2618. reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
  2619. reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
  2620. hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
  2621. /* enable PHY */
  2622. hisi_sas_phy_enable(hisi_hba, phy_no, 1);
  2623. }
  2624. #define SAS_PHY_BIST_CODE_INIT 0x1
  2625. #define SAS_PHY_BIST_CODE1_INIT 0X80
  2626. static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
  2627. {
  2628. u32 reg_val, mode_tmp;
  2629. u32 linkrate = hisi_hba->debugfs_bist_linkrate;
  2630. u32 phy_no = hisi_hba->debugfs_bist_phy_no;
  2631. u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
  2632. u32 code_mode = hisi_hba->debugfs_bist_code_mode;
  2633. u32 path_mode = hisi_hba->debugfs_bist_mode;
  2634. u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
  2635. struct device *dev = hisi_hba->dev;
  2636. dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
  2637. phy_no, linkrate, code_mode, path_mode,
  2638. ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
  2639. ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
  2640. ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
  2641. ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
  2642. fix_code[FIXED_CODE_1]);
  2643. mode_tmp = path_mode ? 2 : 1;
  2644. if (enable) {
  2645. /* some preparations before bist test */
  2646. hisi_sas_bist_test_prep_v3_hw(hisi_hba);
  2647. /* set linkrate of bit test*/
  2648. reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
  2649. PROG_PHY_LINK_RATE);
  2650. reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
  2651. reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
  2652. hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
  2653. reg_val);
  2654. /* set code mode of bit test */
  2655. reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
  2656. SAS_PHY_BIST_CTRL);
  2657. reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
  2658. CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
  2659. CFG_BIST_TEST_MSK);
  2660. reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
  2661. (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
  2662. CFG_BIST_TEST_MSK);
  2663. hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
  2664. reg_val);
  2665. /* set the bist init value */
  2666. if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
  2667. reg_val = hisi_hba->debugfs_bist_fixed_code[0];
  2668. hisi_sas_phy_write32(hisi_hba, phy_no,
  2669. SAS_PHY_BIST_CODE, reg_val);
  2670. reg_val = hisi_hba->debugfs_bist_fixed_code[1];
  2671. hisi_sas_phy_write32(hisi_hba, phy_no,
  2672. SAS_PHY_BIST_CODE1, reg_val);
  2673. } else {
  2674. hisi_sas_phy_write32(hisi_hba, phy_no,
  2675. SAS_PHY_BIST_CODE,
  2676. SAS_PHY_BIST_CODE_INIT);
  2677. hisi_sas_phy_write32(hisi_hba, phy_no,
  2678. SAS_PHY_BIST_CODE1,
  2679. SAS_PHY_BIST_CODE1_INIT);
  2680. }
  2681. mdelay(100);
  2682. reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
  2683. hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
  2684. reg_val);
  2685. /* clear error bit */
  2686. mdelay(100);
  2687. hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
  2688. } else {
  2689. /* disable bist test and recover it */
  2690. hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
  2691. phy_no, SAS_BIST_ERR_CNT);
  2692. hisi_sas_bist_test_restore_v3_hw(hisi_hba);
  2693. }
  2694. return 0;
  2695. }
  2696. static int hisi_sas_map_queues(struct Scsi_Host *shost)
  2697. {
  2698. struct hisi_hba *hisi_hba = shost_priv(shost);
  2699. struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
  2700. return blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
  2701. BASE_VECTORS_V3_HW);
  2702. }
  2703. static struct scsi_host_template sht_v3_hw = {
  2704. .name = DRV_NAME,
  2705. .proc_name = DRV_NAME,
  2706. .module = THIS_MODULE,
  2707. .queuecommand = sas_queuecommand,
  2708. .dma_need_drain = ata_scsi_dma_need_drain,
  2709. .target_alloc = sas_target_alloc,
  2710. .slave_configure = slave_configure_v3_hw,
  2711. .scan_finished = hisi_sas_scan_finished,
  2712. .scan_start = hisi_sas_scan_start,
  2713. .map_queues = hisi_sas_map_queues,
  2714. .change_queue_depth = sas_change_queue_depth,
  2715. .bios_param = sas_bios_param,
  2716. .this_id = -1,
  2717. .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
  2718. .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
  2719. .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
  2720. .eh_device_reset_handler = sas_eh_device_reset_handler,
  2721. .eh_target_reset_handler = sas_eh_target_reset_handler,
  2722. .slave_alloc = sas_slave_alloc,
  2723. .target_destroy = sas_target_destroy,
  2724. .ioctl = sas_ioctl,
  2725. #ifdef CONFIG_COMPAT
  2726. .compat_ioctl = sas_ioctl,
  2727. #endif
  2728. .shost_attrs = host_attrs_v3_hw,
  2729. .tag_alloc_policy = BLK_TAG_ALLOC_RR,
  2730. .host_reset = hisi_sas_host_reset,
  2731. .host_tagset = 1,
  2732. };
  2733. static const struct hisi_sas_hw hisi_sas_v3_hw = {
  2734. .hw_init = hisi_sas_v3_init,
  2735. .setup_itct = setup_itct_v3_hw,
  2736. .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
  2737. .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
  2738. .clear_itct = clear_itct_v3_hw,
  2739. .sl_notify_ssp = sl_notify_ssp_v3_hw,
  2740. .prep_ssp = prep_ssp_v3_hw,
  2741. .prep_smp = prep_smp_v3_hw,
  2742. .prep_stp = prep_ata_v3_hw,
  2743. .prep_abort = prep_abort_v3_hw,
  2744. .start_delivery = start_delivery_v3_hw,
  2745. .phys_init = phys_init_v3_hw,
  2746. .phy_start = start_phy_v3_hw,
  2747. .phy_disable = disable_phy_v3_hw,
  2748. .phy_hard_reset = phy_hard_reset_v3_hw,
  2749. .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
  2750. .phy_set_linkrate = phy_set_linkrate_v3_hw,
  2751. .dereg_device = dereg_device_v3_hw,
  2752. .soft_reset = soft_reset_v3_hw,
  2753. .get_phys_state = get_phys_state_v3_hw,
  2754. .get_events = phy_get_events_v3_hw,
  2755. .write_gpio = write_gpio_v3_hw,
  2756. .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
  2757. .debugfs_reg_array[DEBUGFS_GLOBAL] = &debugfs_global_reg,
  2758. .debugfs_reg_array[DEBUGFS_AXI] = &debugfs_axi_reg,
  2759. .debugfs_reg_array[DEBUGFS_RAS] = &debugfs_ras_reg,
  2760. .debugfs_reg_port = &debugfs_port_reg,
  2761. .snapshot_prepare = debugfs_snapshot_prepare_v3_hw,
  2762. .snapshot_restore = debugfs_snapshot_restore_v3_hw,
  2763. .read_iost_itct_cache = read_iost_itct_cache_v3_hw,
  2764. .set_bist = debugfs_set_bist_v3_hw,
  2765. };
  2766. static struct Scsi_Host *
  2767. hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
  2768. {
  2769. struct Scsi_Host *shost;
  2770. struct hisi_hba *hisi_hba;
  2771. struct device *dev = &pdev->dev;
  2772. shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
  2773. if (!shost) {
  2774. dev_err(dev, "shost alloc failed\n");
  2775. return NULL;
  2776. }
  2777. hisi_hba = shost_priv(shost);
  2778. INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
  2779. INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler);
  2780. hisi_hba->hw = &hisi_sas_v3_hw;
  2781. hisi_hba->pci_dev = pdev;
  2782. hisi_hba->dev = dev;
  2783. hisi_hba->shost = shost;
  2784. SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
  2785. if (prot_mask & ~HISI_SAS_PROT_MASK)
  2786. dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
  2787. prot_mask);
  2788. else
  2789. hisi_hba->prot_mask = prot_mask;
  2790. if (hisi_sas_get_fw_info(hisi_hba) < 0)
  2791. goto err_out;
  2792. if (hisi_sas_alloc(hisi_hba)) {
  2793. hisi_sas_free(hisi_hba);
  2794. goto err_out;
  2795. }
  2796. return shost;
  2797. err_out:
  2798. scsi_host_put(shost);
  2799. dev_err(dev, "shost alloc failed\n");
  2800. return NULL;
  2801. }
  2802. static int
  2803. hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  2804. {
  2805. struct Scsi_Host *shost;
  2806. struct hisi_hba *hisi_hba;
  2807. struct device *dev = &pdev->dev;
  2808. struct asd_sas_phy **arr_phy;
  2809. struct asd_sas_port **arr_port;
  2810. struct sas_ha_struct *sha;
  2811. int rc, phy_nr, port_nr, i;
  2812. rc = pci_enable_device(pdev);
  2813. if (rc)
  2814. goto err_out;
  2815. pci_set_master(pdev);
  2816. rc = pci_request_regions(pdev, DRV_NAME);
  2817. if (rc)
  2818. goto err_out_disable_device;
  2819. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
  2820. if (rc)
  2821. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  2822. if (rc) {
  2823. dev_err(dev, "No usable DMA addressing method\n");
  2824. rc = -ENODEV;
  2825. goto err_out_regions;
  2826. }
  2827. shost = hisi_sas_shost_alloc_pci(pdev);
  2828. if (!shost) {
  2829. rc = -ENOMEM;
  2830. goto err_out_regions;
  2831. }
  2832. sha = SHOST_TO_SAS_HA(shost);
  2833. hisi_hba = shost_priv(shost);
  2834. dev_set_drvdata(dev, sha);
  2835. hisi_hba->regs = pcim_iomap(pdev, 5, 0);
  2836. if (!hisi_hba->regs) {
  2837. dev_err(dev, "cannot map register\n");
  2838. rc = -ENOMEM;
  2839. goto err_out_ha;
  2840. }
  2841. phy_nr = port_nr = hisi_hba->n_phy;
  2842. arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
  2843. arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
  2844. if (!arr_phy || !arr_port) {
  2845. rc = -ENOMEM;
  2846. goto err_out_ha;
  2847. }
  2848. sha->sas_phy = arr_phy;
  2849. sha->sas_port = arr_port;
  2850. sha->core.shost = shost;
  2851. sha->lldd_ha = hisi_hba;
  2852. shost->transportt = hisi_sas_stt;
  2853. shost->max_id = HISI_SAS_MAX_DEVICES;
  2854. shost->max_lun = ~0;
  2855. shost->max_channel = 1;
  2856. shost->max_cmd_len = 16;
  2857. shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
  2858. shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
  2859. sha->sas_ha_name = DRV_NAME;
  2860. sha->dev = dev;
  2861. sha->lldd_module = THIS_MODULE;
  2862. sha->sas_addr = &hisi_hba->sas_addr[0];
  2863. sha->num_phys = hisi_hba->n_phy;
  2864. for (i = 0; i < hisi_hba->n_phy; i++) {
  2865. sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
  2866. sha->sas_port[i] = &hisi_hba->port[i].sas_port;
  2867. }
  2868. if (hisi_hba->prot_mask) {
  2869. dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
  2870. prot_mask);
  2871. scsi_host_set_prot(hisi_hba->shost, prot_mask);
  2872. if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
  2873. scsi_host_set_guard(hisi_hba->shost,
  2874. SHOST_DIX_GUARD_CRC);
  2875. }
  2876. if (hisi_sas_debugfs_enable)
  2877. hisi_sas_debugfs_init(hisi_hba);
  2878. rc = interrupt_preinit_v3_hw(hisi_hba);
  2879. if (rc)
  2880. goto err_out_debugfs;
  2881. dev_err(dev, "%d hw queues\n", shost->nr_hw_queues);
  2882. rc = scsi_add_host(shost, dev);
  2883. if (rc)
  2884. goto err_out_debugfs;
  2885. rc = sas_register_ha(sha);
  2886. if (rc)
  2887. goto err_out_register_ha;
  2888. rc = hisi_hba->hw->hw_init(hisi_hba);
  2889. if (rc)
  2890. goto err_out_register_ha;
  2891. scsi_scan_host(shost);
  2892. /*
  2893. * For the situation that there are ATA disks connected with SAS
  2894. * controller, it additionally creates ata_port which will affect the
  2895. * child_count of hisi_hba->dev. Even if suspended all the disks,
  2896. * ata_port is still and the child_count of hisi_hba->dev is not 0.
  2897. * So use pm_suspend_ignore_children() to ignore the effect to
  2898. * hisi_hba->dev.
  2899. */
  2900. pm_suspend_ignore_children(dev, true);
  2901. pm_runtime_put_noidle(&pdev->dev);
  2902. return 0;
  2903. err_out_register_ha:
  2904. scsi_remove_host(shost);
  2905. err_out_debugfs:
  2906. hisi_sas_debugfs_exit(hisi_hba);
  2907. err_out_ha:
  2908. hisi_sas_free(hisi_hba);
  2909. scsi_host_put(shost);
  2910. err_out_regions:
  2911. pci_release_regions(pdev);
  2912. err_out_disable_device:
  2913. pci_disable_device(pdev);
  2914. err_out:
  2915. return rc;
  2916. }
  2917. static void
  2918. hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
  2919. {
  2920. int i;
  2921. devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
  2922. devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
  2923. devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
  2924. for (i = 0; i < hisi_hba->cq_nvecs; i++) {
  2925. struct hisi_sas_cq *cq = &hisi_hba->cq[i];
  2926. int nr = hisi_sas_intr_conv ? 16 : 16 + i;
  2927. devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
  2928. }
  2929. }
  2930. static void hisi_sas_v3_remove(struct pci_dev *pdev)
  2931. {
  2932. struct device *dev = &pdev->dev;
  2933. struct sas_ha_struct *sha = dev_get_drvdata(dev);
  2934. struct hisi_hba *hisi_hba = sha->lldd_ha;
  2935. struct Scsi_Host *shost = sha->core.shost;
  2936. pm_runtime_get_noresume(dev);
  2937. if (timer_pending(&hisi_hba->timer))
  2938. del_timer(&hisi_hba->timer);
  2939. sas_unregister_ha(sha);
  2940. sas_remove_host(sha->core.shost);
  2941. hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
  2942. pci_release_regions(pdev);
  2943. pci_disable_device(pdev);
  2944. hisi_sas_free(hisi_hba);
  2945. hisi_sas_debugfs_exit(hisi_hba);
  2946. scsi_host_put(shost);
  2947. }
  2948. static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
  2949. {
  2950. struct sas_ha_struct *sha = pci_get_drvdata(pdev);
  2951. struct hisi_hba *hisi_hba = sha->lldd_ha;
  2952. struct device *dev = hisi_hba->dev;
  2953. int rc;
  2954. dev_info(dev, "FLR prepare\n");
  2955. set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
  2956. hisi_sas_controller_reset_prepare(hisi_hba);
  2957. rc = disable_host_v3_hw(hisi_hba);
  2958. if (rc)
  2959. dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
  2960. }
  2961. static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
  2962. {
  2963. struct sas_ha_struct *sha = pci_get_drvdata(pdev);
  2964. struct hisi_hba *hisi_hba = sha->lldd_ha;
  2965. struct device *dev = hisi_hba->dev;
  2966. int rc;
  2967. hisi_sas_init_mem(hisi_hba);
  2968. rc = hw_init_v3_hw(hisi_hba);
  2969. if (rc) {
  2970. dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
  2971. return;
  2972. }
  2973. hisi_sas_controller_reset_done(hisi_hba);
  2974. dev_info(dev, "FLR done\n");
  2975. }
  2976. enum {
  2977. /* instances of the controller */
  2978. hip08,
  2979. };
  2980. static int _suspend_v3_hw(struct device *device)
  2981. {
  2982. struct pci_dev *pdev = to_pci_dev(device);
  2983. struct sas_ha_struct *sha = pci_get_drvdata(pdev);
  2984. struct hisi_hba *hisi_hba = sha->lldd_ha;
  2985. struct device *dev = hisi_hba->dev;
  2986. struct Scsi_Host *shost = hisi_hba->shost;
  2987. pci_power_t device_state;
  2988. int rc;
  2989. if (!pdev->pm_cap) {
  2990. dev_err(dev, "PCI PM not supported\n");
  2991. return -ENODEV;
  2992. }
  2993. if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
  2994. return -1;
  2995. scsi_block_requests(shost);
  2996. set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
  2997. flush_workqueue(hisi_hba->wq);
  2998. rc = disable_host_v3_hw(hisi_hba);
  2999. if (rc) {
  3000. dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
  3001. clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
  3002. clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
  3003. scsi_unblock_requests(shost);
  3004. return rc;
  3005. }
  3006. hisi_sas_init_mem(hisi_hba);
  3007. device_state = pci_choose_state(pdev, PMSG_SUSPEND);
  3008. dev_warn(dev, "entering operating state [D%d]\n",
  3009. device_state);
  3010. pci_save_state(pdev);
  3011. pci_disable_device(pdev);
  3012. pci_set_power_state(pdev, device_state);
  3013. hisi_sas_release_tasks(hisi_hba);
  3014. sas_suspend_ha(sha);
  3015. return 0;
  3016. }
  3017. static int _resume_v3_hw(struct device *device)
  3018. {
  3019. struct pci_dev *pdev = to_pci_dev(device);
  3020. struct sas_ha_struct *sha = pci_get_drvdata(pdev);
  3021. struct hisi_hba *hisi_hba = sha->lldd_ha;
  3022. struct Scsi_Host *shost = hisi_hba->shost;
  3023. struct device *dev = hisi_hba->dev;
  3024. unsigned int rc;
  3025. pci_power_t device_state = pdev->current_state;
  3026. dev_warn(dev, "resuming from operating state [D%d]\n",
  3027. device_state);
  3028. pci_set_power_state(pdev, PCI_D0);
  3029. pci_enable_wake(pdev, PCI_D0, 0);
  3030. pci_restore_state(pdev);
  3031. rc = pci_enable_device(pdev);
  3032. if (rc) {
  3033. dev_err(dev, "enable device failed during resume (%d)\n", rc);
  3034. return rc;
  3035. }
  3036. pci_set_master(pdev);
  3037. scsi_unblock_requests(shost);
  3038. clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
  3039. sas_prep_resume_ha(sha);
  3040. rc = hw_init_v3_hw(hisi_hba);
  3041. if (rc) {
  3042. scsi_remove_host(shost);
  3043. pci_disable_device(pdev);
  3044. return rc;
  3045. }
  3046. hisi_hba->hw->phys_init(hisi_hba);
  3047. sas_resume_ha(sha);
  3048. clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
  3049. return 0;
  3050. }
  3051. static int suspend_v3_hw(struct device *device)
  3052. {
  3053. struct pci_dev *pdev = to_pci_dev(device);
  3054. struct sas_ha_struct *sha = pci_get_drvdata(pdev);
  3055. struct hisi_hba *hisi_hba = sha->lldd_ha;
  3056. int rc;
  3057. set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
  3058. rc = _suspend_v3_hw(device);
  3059. if (rc)
  3060. clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
  3061. return rc;
  3062. }
  3063. static int resume_v3_hw(struct device *device)
  3064. {
  3065. struct pci_dev *pdev = to_pci_dev(device);
  3066. struct sas_ha_struct *sha = pci_get_drvdata(pdev);
  3067. struct hisi_hba *hisi_hba = sha->lldd_ha;
  3068. int rc = _resume_v3_hw(device);
  3069. clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
  3070. return rc;
  3071. }
  3072. static const struct pci_device_id sas_v3_pci_table[] = {
  3073. { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
  3074. {}
  3075. };
  3076. MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
  3077. static const struct pci_error_handlers hisi_sas_err_handler = {
  3078. .reset_prepare = hisi_sas_reset_prepare_v3_hw,
  3079. .reset_done = hisi_sas_reset_done_v3_hw,
  3080. };
  3081. static int runtime_suspend_v3_hw(struct device *dev)
  3082. {
  3083. return suspend_v3_hw(dev);
  3084. }
  3085. static int runtime_resume_v3_hw(struct device *dev)
  3086. {
  3087. return resume_v3_hw(dev);
  3088. }
  3089. static const struct dev_pm_ops hisi_sas_v3_pm_ops = {
  3090. SET_SYSTEM_SLEEP_PM_OPS(suspend_v3_hw, resume_v3_hw)
  3091. SET_RUNTIME_PM_OPS(runtime_suspend_v3_hw,
  3092. runtime_resume_v3_hw, NULL)
  3093. };
  3094. static struct pci_driver sas_v3_pci_driver = {
  3095. .name = DRV_NAME,
  3096. .id_table = sas_v3_pci_table,
  3097. .probe = hisi_sas_v3_probe,
  3098. .remove = hisi_sas_v3_remove,
  3099. .err_handler = &hisi_sas_err_handler,
  3100. .driver.pm = &hisi_sas_v3_pm_ops,
  3101. };
  3102. module_pci_driver(sas_v3_pci_driver);
  3103. module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
  3104. MODULE_LICENSE("GPL");
  3105. MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
  3106. MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
  3107. MODULE_ALIAS("pci:" DRV_NAME);