hisi_sas_v2_hw.c 106 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2016 Linaro Ltd.
  4. * Copyright (c) 2016 Hisilicon Limited.
  5. */
  6. #include "hisi_sas.h"
  7. #define DRV_NAME "hisi_sas_v2_hw"
  8. /* global registers need init*/
  9. #define DLVRY_QUEUE_ENABLE 0x0
  10. #define IOST_BASE_ADDR_LO 0x8
  11. #define IOST_BASE_ADDR_HI 0xc
  12. #define ITCT_BASE_ADDR_LO 0x10
  13. #define ITCT_BASE_ADDR_HI 0x14
  14. #define IO_BROKEN_MSG_ADDR_LO 0x18
  15. #define IO_BROKEN_MSG_ADDR_HI 0x1c
  16. #define PHY_CONTEXT 0x20
  17. #define PHY_STATE 0x24
  18. #define PHY_PORT_NUM_MA 0x28
  19. #define PORT_STATE 0x2c
  20. #define PORT_STATE_PHY8_PORT_NUM_OFF 16
  21. #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  22. #define PORT_STATE_PHY8_CONN_RATE_OFF 20
  23. #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  24. #define PHY_CONN_RATE 0x30
  25. #define HGC_TRANS_TASK_CNT_LIMIT 0x38
  26. #define AXI_AHB_CLK_CFG 0x3c
  27. #define ITCT_CLR 0x44
  28. #define ITCT_CLR_EN_OFF 16
  29. #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
  30. #define ITCT_DEV_OFF 0
  31. #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
  32. #define AXI_USER1 0x48
  33. #define AXI_USER2 0x4c
  34. #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
  35. #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
  36. #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
  37. #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
  38. #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  39. #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
  40. #define HGC_GET_ITV_TIME 0x90
  41. #define DEVICE_MSG_WORK_MODE 0x94
  42. #define OPENA_WT_CONTI_TIME 0x9c
  43. #define I_T_NEXUS_LOSS_TIME 0xa0
  44. #define MAX_CON_TIME_LIMIT_TIME 0xa4
  45. #define BUS_INACTIVE_LIMIT_TIME 0xa8
  46. #define REJECT_TO_OPEN_LIMIT_TIME 0xac
  47. #define CFG_AGING_TIME 0xbc
  48. #define HGC_DFX_CFG2 0xc0
  49. #define HGC_IOMB_PROC1_STATUS 0x104
  50. #define CFG_1US_TIMER_TRSH 0xcc
  51. #define HGC_LM_DFX_STATUS2 0x128
  52. #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
  53. #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  54. HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  55. #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
  56. #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  57. HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  58. #define HGC_CQE_ECC_ADDR 0x13c
  59. #define HGC_CQE_ECC_1B_ADDR_OFF 0
  60. #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  61. #define HGC_CQE_ECC_MB_ADDR_OFF 8
  62. #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  63. #define HGC_IOST_ECC_ADDR 0x140
  64. #define HGC_IOST_ECC_1B_ADDR_OFF 0
  65. #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  66. #define HGC_IOST_ECC_MB_ADDR_OFF 16
  67. #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  68. #define HGC_DQE_ECC_ADDR 0x144
  69. #define HGC_DQE_ECC_1B_ADDR_OFF 0
  70. #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  71. #define HGC_DQE_ECC_MB_ADDR_OFF 16
  72. #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  73. #define HGC_INVLD_DQE_INFO 0x148
  74. #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
  75. #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  76. #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
  77. #define HGC_ITCT_ECC_ADDR 0x150
  78. #define HGC_ITCT_ECC_1B_ADDR_OFF 0
  79. #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
  80. HGC_ITCT_ECC_1B_ADDR_OFF)
  81. #define HGC_ITCT_ECC_MB_ADDR_OFF 16
  82. #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
  83. HGC_ITCT_ECC_MB_ADDR_OFF)
  84. #define HGC_AXI_FIFO_ERR_INFO 0x154
  85. #define AXI_ERR_INFO_OFF 0
  86. #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
  87. #define FIFO_ERR_INFO_OFF 8
  88. #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
  89. #define INT_COAL_EN 0x19c
  90. #define OQ_INT_COAL_TIME 0x1a0
  91. #define OQ_INT_COAL_CNT 0x1a4
  92. #define ENT_INT_COAL_TIME 0x1a8
  93. #define ENT_INT_COAL_CNT 0x1ac
  94. #define OQ_INT_SRC 0x1b0
  95. #define OQ_INT_SRC_MSK 0x1b4
  96. #define ENT_INT_SRC1 0x1b8
  97. #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
  98. #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  99. #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
  100. #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  101. #define ENT_INT_SRC2 0x1bc
  102. #define ENT_INT_SRC3 0x1c0
  103. #define ENT_INT_SRC3_WP_DEPTH_OFF 8
  104. #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
  105. #define ENT_INT_SRC3_RP_DEPTH_OFF 10
  106. #define ENT_INT_SRC3_AXI_OFF 11
  107. #define ENT_INT_SRC3_FIFO_OFF 12
  108. #define ENT_INT_SRC3_LM_OFF 14
  109. #define ENT_INT_SRC3_ITC_INT_OFF 15
  110. #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  111. #define ENT_INT_SRC3_ABT_OFF 16
  112. #define ENT_INT_SRC_MSK1 0x1c4
  113. #define ENT_INT_SRC_MSK2 0x1c8
  114. #define ENT_INT_SRC_MSK3 0x1cc
  115. #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
  116. #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  117. #define SAS_ECC_INTR 0x1e8
  118. #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
  119. #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
  120. #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
  121. #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
  122. #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
  123. #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
  124. #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
  125. #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
  126. #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
  127. #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
  128. #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
  129. #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
  130. #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
  131. #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
  132. #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
  133. #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
  134. #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
  135. #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
  136. #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
  137. #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
  138. #define SAS_ECC_INTR_MSK 0x1ec
  139. #define HGC_ERR_STAT_EN 0x238
  140. #define CQE_SEND_CNT 0x248
  141. #define DLVRY_Q_0_BASE_ADDR_LO 0x260
  142. #define DLVRY_Q_0_BASE_ADDR_HI 0x264
  143. #define DLVRY_Q_0_DEPTH 0x268
  144. #define DLVRY_Q_0_WR_PTR 0x26c
  145. #define DLVRY_Q_0_RD_PTR 0x270
  146. #define HYPER_STREAM_ID_EN_CFG 0xc80
  147. #define OQ0_INT_SRC_MSK 0xc90
  148. #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
  149. #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
  150. #define COMPL_Q_0_DEPTH 0x4e8
  151. #define COMPL_Q_0_WR_PTR 0x4ec
  152. #define COMPL_Q_0_RD_PTR 0x4f0
  153. #define HGC_RXM_DFX_STATUS14 0xae8
  154. #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
  155. #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
  156. HGC_RXM_DFX_STATUS14_MEM0_OFF)
  157. #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
  158. #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
  159. HGC_RXM_DFX_STATUS14_MEM1_OFF)
  160. #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
  161. #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
  162. HGC_RXM_DFX_STATUS14_MEM2_OFF)
  163. #define HGC_RXM_DFX_STATUS15 0xaec
  164. #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
  165. #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
  166. HGC_RXM_DFX_STATUS15_MEM3_OFF)
  167. /* phy registers need init */
  168. #define PORT_BASE (0x2000)
  169. #define PHY_CFG (PORT_BASE + 0x0)
  170. #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
  171. #define PHY_CFG_ENA_OFF 0
  172. #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
  173. #define PHY_CFG_DC_OPT_OFF 2
  174. #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
  175. #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
  176. #define PROG_PHY_LINK_RATE_MAX_OFF 0
  177. #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
  178. #define PHY_CTRL (PORT_BASE + 0x14)
  179. #define PHY_CTRL_RESET_OFF 0
  180. #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
  181. #define SAS_PHY_CTRL (PORT_BASE + 0x20)
  182. #define SL_CFG (PORT_BASE + 0x84)
  183. #define PHY_PCN (PORT_BASE + 0x44)
  184. #define SL_TOUT_CFG (PORT_BASE + 0x8c)
  185. #define SL_CONTROL (PORT_BASE + 0x94)
  186. #define SL_CONTROL_NOTIFY_EN_OFF 0
  187. #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
  188. #define SL_CONTROL_CTA_OFF 17
  189. #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
  190. #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
  191. #define RX_BCAST_CHG_OFF 1
  192. #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
  193. #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
  194. #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
  195. #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
  196. #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
  197. #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
  198. #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
  199. #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
  200. #define TXID_AUTO (PORT_BASE + 0xb8)
  201. #define TXID_AUTO_CT3_OFF 1
  202. #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
  203. #define TXID_AUTO_CTB_OFF 11
  204. #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
  205. #define TX_HARDRST_OFF 2
  206. #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
  207. #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
  208. #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
  209. #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
  210. #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
  211. #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
  212. #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
  213. #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
  214. #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
  215. #define CON_CONTROL (PORT_BASE + 0x118)
  216. #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
  217. #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
  218. (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
  219. #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
  220. #define CHL_INT0 (PORT_BASE + 0x1b4)
  221. #define CHL_INT0_HOTPLUG_TOUT_OFF 0
  222. #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
  223. #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
  224. #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
  225. #define CHL_INT0_SL_PHY_ENABLE_OFF 2
  226. #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
  227. #define CHL_INT0_NOT_RDY_OFF 4
  228. #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
  229. #define CHL_INT0_PHY_RDY_OFF 5
  230. #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
  231. #define CHL_INT1 (PORT_BASE + 0x1b8)
  232. #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
  233. #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
  234. #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
  235. #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
  236. #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
  237. #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
  238. #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
  239. #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
  240. #define CHL_INT2 (PORT_BASE + 0x1bc)
  241. #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
  242. #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
  243. #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
  244. #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
  245. #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
  246. #define DMA_TX_DFX0 (PORT_BASE + 0x200)
  247. #define DMA_TX_DFX1 (PORT_BASE + 0x204)
  248. #define DMA_TX_DFX1_IPTT_OFF 0
  249. #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
  250. #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
  251. #define PORT_DFX0 (PORT_BASE + 0x258)
  252. #define LINK_DFX2 (PORT_BASE + 0X264)
  253. #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
  254. #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
  255. #define LINK_DFX2_SEND_HOLD_STS_OFF 10
  256. #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
  257. #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
  258. #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
  259. #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
  260. #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
  261. #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
  262. #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
  263. #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
  264. #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
  265. #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
  266. #define DMA_TX_STATUS_BUSY_OFF 0
  267. #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
  268. #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
  269. #define DMA_RX_STATUS_BUSY_OFF 0
  270. #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
  271. #define AXI_CFG (0x5100)
  272. #define AM_CFG_MAX_TRANS (0x5010)
  273. #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
  274. #define AXI_MASTER_CFG_BASE (0x5000)
  275. #define AM_CTRL_GLOBAL (0x0)
  276. #define AM_CURR_TRANS_RETURN (0x150)
  277. /* HW dma structures */
  278. /* Delivery queue header */
  279. /* dw0 */
  280. #define CMD_HDR_ABORT_FLAG_OFF 0
  281. #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
  282. #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
  283. #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
  284. #define CMD_HDR_RESP_REPORT_OFF 5
  285. #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
  286. #define CMD_HDR_TLR_CTRL_OFF 6
  287. #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
  288. #define CMD_HDR_PHY_ID_OFF 8
  289. #define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF)
  290. #define CMD_HDR_FORCE_PHY_OFF 17
  291. #define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF)
  292. #define CMD_HDR_PORT_OFF 18
  293. #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
  294. #define CMD_HDR_PRIORITY_OFF 27
  295. #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
  296. #define CMD_HDR_CMD_OFF 29
  297. #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
  298. /* dw1 */
  299. #define CMD_HDR_DIR_OFF 5
  300. #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
  301. #define CMD_HDR_RESET_OFF 7
  302. #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
  303. #define CMD_HDR_VDTL_OFF 10
  304. #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
  305. #define CMD_HDR_FRAME_TYPE_OFF 11
  306. #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
  307. #define CMD_HDR_DEV_ID_OFF 16
  308. #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
  309. /* dw2 */
  310. #define CMD_HDR_CFL_OFF 0
  311. #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
  312. #define CMD_HDR_NCQ_TAG_OFF 10
  313. #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
  314. #define CMD_HDR_MRFL_OFF 15
  315. #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
  316. #define CMD_HDR_SG_MOD_OFF 24
  317. #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
  318. #define CMD_HDR_FIRST_BURST_OFF 26
  319. #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
  320. /* dw3 */
  321. #define CMD_HDR_IPTT_OFF 0
  322. #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
  323. /* dw6 */
  324. #define CMD_HDR_DIF_SGL_LEN_OFF 0
  325. #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
  326. #define CMD_HDR_DATA_SGL_LEN_OFF 16
  327. #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
  328. #define CMD_HDR_ABORT_IPTT_OFF 16
  329. #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
  330. /* Completion header */
  331. /* dw0 */
  332. #define CMPLT_HDR_ERR_PHASE_OFF 2
  333. #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
  334. #define CMPLT_HDR_RSPNS_XFRD_OFF 10
  335. #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
  336. #define CMPLT_HDR_ERX_OFF 12
  337. #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
  338. #define CMPLT_HDR_ABORT_STAT_OFF 13
  339. #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
  340. /* abort_stat */
  341. #define STAT_IO_NOT_VALID 0x1
  342. #define STAT_IO_NO_DEVICE 0x2
  343. #define STAT_IO_COMPLETE 0x3
  344. #define STAT_IO_ABORTED 0x4
  345. /* dw1 */
  346. #define CMPLT_HDR_IPTT_OFF 0
  347. #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
  348. #define CMPLT_HDR_DEV_ID_OFF 16
  349. #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
  350. /* ITCT header */
  351. /* qw0 */
  352. #define ITCT_HDR_DEV_TYPE_OFF 0
  353. #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
  354. #define ITCT_HDR_VALID_OFF 2
  355. #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
  356. #define ITCT_HDR_MCR_OFF 5
  357. #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
  358. #define ITCT_HDR_VLN_OFF 9
  359. #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
  360. #define ITCT_HDR_SMP_TIMEOUT_OFF 16
  361. #define ITCT_HDR_SMP_TIMEOUT_8US 1
  362. #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
  363. 250) /* 2ms */
  364. #define ITCT_HDR_AWT_CONTINUE_OFF 25
  365. #define ITCT_HDR_PORT_ID_OFF 28
  366. #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
  367. /* qw2 */
  368. #define ITCT_HDR_INLT_OFF 0
  369. #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
  370. #define ITCT_HDR_BITLT_OFF 16
  371. #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
  372. #define ITCT_HDR_MCTLT_OFF 32
  373. #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
  374. #define ITCT_HDR_RTOLT_OFF 48
  375. #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
  376. #define HISI_SAS_FATAL_INT_NR 2
  377. struct hisi_sas_complete_v2_hdr {
  378. __le32 dw0;
  379. __le32 dw1;
  380. __le32 act;
  381. __le32 dw3;
  382. };
  383. struct hisi_sas_err_record_v2 {
  384. /* dw0 */
  385. __le32 trans_tx_fail_type;
  386. /* dw1 */
  387. __le32 trans_rx_fail_type;
  388. /* dw2 */
  389. __le16 dma_tx_err_type;
  390. __le16 sipc_rx_err_type;
  391. /* dw3 */
  392. __le32 dma_rx_err_type;
  393. };
  394. struct signal_attenuation_s {
  395. u32 de_emphasis;
  396. u32 preshoot;
  397. u32 boost;
  398. };
  399. struct sig_atten_lu_s {
  400. const struct signal_attenuation_s *att;
  401. u32 sas_phy_ctrl;
  402. };
  403. static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
  404. {
  405. .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
  406. .msk = HGC_DQE_ECC_1B_ADDR_MSK,
  407. .shift = HGC_DQE_ECC_1B_ADDR_OFF,
  408. .msg = "hgc_dqe_ecc1b_intr",
  409. .reg = HGC_DQE_ECC_ADDR,
  410. },
  411. {
  412. .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
  413. .msk = HGC_IOST_ECC_1B_ADDR_MSK,
  414. .shift = HGC_IOST_ECC_1B_ADDR_OFF,
  415. .msg = "hgc_iost_ecc1b_intr",
  416. .reg = HGC_IOST_ECC_ADDR,
  417. },
  418. {
  419. .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
  420. .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
  421. .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
  422. .msg = "hgc_itct_ecc1b_intr",
  423. .reg = HGC_ITCT_ECC_ADDR,
  424. },
  425. {
  426. .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
  427. .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
  428. .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
  429. .msg = "hgc_iostl_ecc1b_intr",
  430. .reg = HGC_LM_DFX_STATUS2,
  431. },
  432. {
  433. .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
  434. .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
  435. .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
  436. .msg = "hgc_itctl_ecc1b_intr",
  437. .reg = HGC_LM_DFX_STATUS2,
  438. },
  439. {
  440. .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
  441. .msk = HGC_CQE_ECC_1B_ADDR_MSK,
  442. .shift = HGC_CQE_ECC_1B_ADDR_OFF,
  443. .msg = "hgc_cqe_ecc1b_intr",
  444. .reg = HGC_CQE_ECC_ADDR,
  445. },
  446. {
  447. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
  448. .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
  449. .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
  450. .msg = "rxm_mem0_ecc1b_intr",
  451. .reg = HGC_RXM_DFX_STATUS14,
  452. },
  453. {
  454. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
  455. .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
  456. .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
  457. .msg = "rxm_mem1_ecc1b_intr",
  458. .reg = HGC_RXM_DFX_STATUS14,
  459. },
  460. {
  461. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
  462. .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
  463. .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
  464. .msg = "rxm_mem2_ecc1b_intr",
  465. .reg = HGC_RXM_DFX_STATUS14,
  466. },
  467. {
  468. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
  469. .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
  470. .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
  471. .msg = "rxm_mem3_ecc1b_intr",
  472. .reg = HGC_RXM_DFX_STATUS15,
  473. },
  474. };
  475. static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
  476. {
  477. .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
  478. .msk = HGC_DQE_ECC_MB_ADDR_MSK,
  479. .shift = HGC_DQE_ECC_MB_ADDR_OFF,
  480. .msg = "hgc_dqe_eccbad_intr",
  481. .reg = HGC_DQE_ECC_ADDR,
  482. },
  483. {
  484. .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
  485. .msk = HGC_IOST_ECC_MB_ADDR_MSK,
  486. .shift = HGC_IOST_ECC_MB_ADDR_OFF,
  487. .msg = "hgc_iost_eccbad_intr",
  488. .reg = HGC_IOST_ECC_ADDR,
  489. },
  490. {
  491. .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
  492. .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
  493. .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
  494. .msg = "hgc_itct_eccbad_intr",
  495. .reg = HGC_ITCT_ECC_ADDR,
  496. },
  497. {
  498. .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
  499. .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
  500. .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
  501. .msg = "hgc_iostl_eccbad_intr",
  502. .reg = HGC_LM_DFX_STATUS2,
  503. },
  504. {
  505. .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
  506. .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
  507. .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
  508. .msg = "hgc_itctl_eccbad_intr",
  509. .reg = HGC_LM_DFX_STATUS2,
  510. },
  511. {
  512. .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
  513. .msk = HGC_CQE_ECC_MB_ADDR_MSK,
  514. .shift = HGC_CQE_ECC_MB_ADDR_OFF,
  515. .msg = "hgc_cqe_eccbad_intr",
  516. .reg = HGC_CQE_ECC_ADDR,
  517. },
  518. {
  519. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
  520. .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
  521. .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
  522. .msg = "rxm_mem0_eccbad_intr",
  523. .reg = HGC_RXM_DFX_STATUS14,
  524. },
  525. {
  526. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
  527. .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
  528. .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
  529. .msg = "rxm_mem1_eccbad_intr",
  530. .reg = HGC_RXM_DFX_STATUS14,
  531. },
  532. {
  533. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
  534. .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
  535. .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
  536. .msg = "rxm_mem2_eccbad_intr",
  537. .reg = HGC_RXM_DFX_STATUS14,
  538. },
  539. {
  540. .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
  541. .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
  542. .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
  543. .msg = "rxm_mem3_eccbad_intr",
  544. .reg = HGC_RXM_DFX_STATUS15,
  545. },
  546. };
  547. enum {
  548. HISI_SAS_PHY_PHY_UPDOWN,
  549. HISI_SAS_PHY_CHNL_INT,
  550. HISI_SAS_PHY_INT_NR
  551. };
  552. enum {
  553. TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
  554. TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
  555. DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
  556. SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
  557. DMA_RX_ERR_BASE = 0x60, /* dw3 */
  558. /* trans tx*/
  559. TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
  560. TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
  561. TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
  562. TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
  563. TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
  564. RESERVED0, /* 0x5 */
  565. TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
  566. TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
  567. TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
  568. TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
  569. TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
  570. TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
  571. TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
  572. TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
  573. TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
  574. TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
  575. TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
  576. TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
  577. TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
  578. TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
  579. TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
  580. TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
  581. TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
  582. TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
  583. TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
  584. TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
  585. TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
  586. TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
  587. /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
  588. TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
  589. /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
  590. TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
  591. TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
  592. /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
  593. TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
  594. /* trans rx */
  595. TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
  596. TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
  597. TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
  598. /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
  599. TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
  600. TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
  601. TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
  602. /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
  603. TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
  604. TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
  605. TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
  606. TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
  607. TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
  608. RESERVED1, /* 0x2b */
  609. TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
  610. TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
  611. TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
  612. TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
  613. TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
  614. TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
  615. /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
  616. TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
  617. /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
  618. TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
  619. /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
  620. RESERVED2, /* 0x34 */
  621. RESERVED3, /* 0x35 */
  622. RESERVED4, /* 0x36 */
  623. RESERVED5, /* 0x37 */
  624. TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
  625. TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
  626. TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
  627. RESERVED6, /* 0x3b */
  628. RESERVED7, /* 0x3c */
  629. RESERVED8, /* 0x3d */
  630. RESERVED9, /* 0x3e */
  631. TRANS_RX_R_ERR, /* 0x3f */
  632. /* dma tx */
  633. DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
  634. DMA_TX_DIF_APP_ERR, /* 0x41 */
  635. DMA_TX_DIF_RPP_ERR, /* 0x42 */
  636. DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
  637. DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
  638. DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
  639. DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
  640. DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
  641. DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
  642. DMA_TX_RAM_ECC_ERR, /* 0x49 */
  643. DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
  644. DMA_TX_MAX_ERR_CODE,
  645. /* sipc rx */
  646. SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
  647. SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
  648. SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
  649. SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
  650. SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
  651. SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
  652. SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
  653. SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
  654. SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
  655. SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
  656. SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
  657. SIPC_RX_MAX_ERR_CODE,
  658. /* dma rx */
  659. DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
  660. DMA_RX_DIF_APP_ERR, /* 0x61 */
  661. DMA_RX_DIF_RPP_ERR, /* 0x62 */
  662. DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
  663. DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
  664. DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
  665. DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
  666. DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
  667. RESERVED10, /* 0x68 */
  668. DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
  669. DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
  670. DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
  671. DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
  672. DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
  673. DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
  674. DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
  675. DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
  676. DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
  677. DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
  678. DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
  679. DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
  680. DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
  681. DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
  682. DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
  683. DMA_RX_RAM_ECC_ERR, /* 0x78 */
  684. DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
  685. DMA_RX_MAX_ERR_CODE,
  686. };
  687. #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
  688. #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
  689. #define DIR_NO_DATA 0
  690. #define DIR_TO_INI 1
  691. #define DIR_TO_DEVICE 2
  692. #define DIR_RESERVED 3
  693. #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
  694. err_phase == 0x4 || err_phase == 0x8 ||\
  695. err_phase == 0x6 || err_phase == 0xa)
  696. #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
  697. err_phase == 0x20 || err_phase == 0x40)
  698. static void link_timeout_disable_link(struct timer_list *t);
  699. static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
  700. {
  701. void __iomem *regs = hisi_hba->regs + off;
  702. return readl(regs);
  703. }
  704. static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
  705. {
  706. void __iomem *regs = hisi_hba->regs + off;
  707. return readl_relaxed(regs);
  708. }
  709. static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
  710. {
  711. void __iomem *regs = hisi_hba->regs + off;
  712. writel(val, regs);
  713. }
  714. static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
  715. u32 off, u32 val)
  716. {
  717. void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
  718. writel(val, regs);
  719. }
  720. static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
  721. int phy_no, u32 off)
  722. {
  723. void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
  724. return readl(regs);
  725. }
  726. /* This function needs to be protected from pre-emption. */
  727. static int
  728. slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
  729. struct domain_device *device)
  730. {
  731. int sata_dev = dev_is_sata(device);
  732. void *bitmap = hisi_hba->slot_index_tags;
  733. struct hisi_sas_device *sas_dev = device->lldd_dev;
  734. int sata_idx = sas_dev->sata_idx;
  735. int start, end;
  736. if (!sata_dev) {
  737. /*
  738. * STP link SoC bug workaround: index starts from 1.
  739. * additionally, we can only allocate odd IPTT(1~4095)
  740. * for SAS/SMP device.
  741. */
  742. start = 1;
  743. end = hisi_hba->slot_index_count;
  744. } else {
  745. if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
  746. return -EINVAL;
  747. /*
  748. * For SATA device: allocate even IPTT in this interval
  749. * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
  750. * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
  751. * SoC bug workaround. So we ignore the first 32 even IPTTs.
  752. */
  753. start = 64 * (sata_idx + 1);
  754. end = 64 * (sata_idx + 2);
  755. }
  756. spin_lock(&hisi_hba->lock);
  757. while (1) {
  758. start = find_next_zero_bit(bitmap,
  759. hisi_hba->slot_index_count, start);
  760. if (start >= end) {
  761. spin_unlock(&hisi_hba->lock);
  762. return -SAS_QUEUE_FULL;
  763. }
  764. /*
  765. * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
  766. */
  767. if (sata_dev ^ (start & 1))
  768. break;
  769. start++;
  770. }
  771. set_bit(start, bitmap);
  772. spin_unlock(&hisi_hba->lock);
  773. return start;
  774. }
  775. static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
  776. {
  777. unsigned int index;
  778. struct device *dev = hisi_hba->dev;
  779. void *bitmap = hisi_hba->sata_dev_bitmap;
  780. index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
  781. if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
  782. dev_warn(dev, "alloc sata index failed, index=%d\n", index);
  783. return false;
  784. }
  785. set_bit(index, bitmap);
  786. *idx = index;
  787. return true;
  788. }
  789. static struct
  790. hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
  791. {
  792. struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
  793. struct hisi_sas_device *sas_dev = NULL;
  794. int i, sata_dev = dev_is_sata(device);
  795. int sata_idx = -1;
  796. spin_lock(&hisi_hba->lock);
  797. if (sata_dev)
  798. if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
  799. goto out;
  800. for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
  801. /*
  802. * SATA device id bit0 should be 0
  803. */
  804. if (sata_dev && (i & 1))
  805. continue;
  806. if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
  807. int queue = i % hisi_hba->queue_count;
  808. struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
  809. hisi_hba->devices[i].device_id = i;
  810. sas_dev = &hisi_hba->devices[i];
  811. sas_dev->dev_status = HISI_SAS_DEV_INIT;
  812. sas_dev->dev_type = device->dev_type;
  813. sas_dev->hisi_hba = hisi_hba;
  814. sas_dev->sas_device = device;
  815. sas_dev->sata_idx = sata_idx;
  816. sas_dev->dq = dq;
  817. spin_lock_init(&sas_dev->lock);
  818. INIT_LIST_HEAD(&hisi_hba->devices[i].list);
  819. break;
  820. }
  821. }
  822. out:
  823. spin_unlock(&hisi_hba->lock);
  824. return sas_dev;
  825. }
  826. static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  827. {
  828. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  829. cfg &= ~PHY_CFG_DC_OPT_MSK;
  830. cfg |= 1 << PHY_CFG_DC_OPT_OFF;
  831. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  832. }
  833. static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  834. {
  835. struct sas_identify_frame identify_frame;
  836. u32 *identify_buffer;
  837. memset(&identify_frame, 0, sizeof(identify_frame));
  838. identify_frame.dev_type = SAS_END_DEVICE;
  839. identify_frame.frame_type = 0;
  840. identify_frame._un1 = 1;
  841. identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
  842. identify_frame.target_bits = SAS_PROTOCOL_NONE;
  843. memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
  844. memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
  845. identify_frame.phy_id = phy_no;
  846. identify_buffer = (u32 *)(&identify_frame);
  847. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
  848. __swab32(identify_buffer[0]));
  849. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
  850. __swab32(identify_buffer[1]));
  851. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
  852. __swab32(identify_buffer[2]));
  853. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
  854. __swab32(identify_buffer[3]));
  855. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
  856. __swab32(identify_buffer[4]));
  857. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
  858. __swab32(identify_buffer[5]));
  859. }
  860. static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
  861. struct hisi_sas_device *sas_dev)
  862. {
  863. struct domain_device *device = sas_dev->sas_device;
  864. struct device *dev = hisi_hba->dev;
  865. u64 qw0, device_id = sas_dev->device_id;
  866. struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
  867. struct domain_device *parent_dev = device->parent;
  868. struct asd_sas_port *sas_port = device->port;
  869. struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
  870. u64 sas_addr;
  871. memset(itct, 0, sizeof(*itct));
  872. /* qw0 */
  873. qw0 = 0;
  874. switch (sas_dev->dev_type) {
  875. case SAS_END_DEVICE:
  876. case SAS_EDGE_EXPANDER_DEVICE:
  877. case SAS_FANOUT_EXPANDER_DEVICE:
  878. qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
  879. break;
  880. case SAS_SATA_DEV:
  881. case SAS_SATA_PENDING:
  882. if (parent_dev && dev_is_expander(parent_dev->dev_type))
  883. qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
  884. else
  885. qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
  886. break;
  887. default:
  888. dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
  889. sas_dev->dev_type);
  890. }
  891. qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
  892. (device->linkrate << ITCT_HDR_MCR_OFF) |
  893. (1 << ITCT_HDR_VLN_OFF) |
  894. (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
  895. (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
  896. (port->id << ITCT_HDR_PORT_ID_OFF));
  897. itct->qw0 = cpu_to_le64(qw0);
  898. /* qw1 */
  899. memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
  900. itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
  901. /* qw2 */
  902. if (!dev_is_sata(device))
  903. itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
  904. (0x1ULL << ITCT_HDR_BITLT_OFF) |
  905. (0x32ULL << ITCT_HDR_MCTLT_OFF) |
  906. (0x1ULL << ITCT_HDR_RTOLT_OFF));
  907. }
  908. static int clear_itct_v2_hw(struct hisi_hba *hisi_hba,
  909. struct hisi_sas_device *sas_dev)
  910. {
  911. DECLARE_COMPLETION_ONSTACK(completion);
  912. u64 dev_id = sas_dev->device_id;
  913. struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
  914. u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
  915. struct device *dev = hisi_hba->dev;
  916. int i;
  917. sas_dev->completion = &completion;
  918. /* clear the itct interrupt state */
  919. if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
  920. hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
  921. ENT_INT_SRC3_ITC_INT_MSK);
  922. /* need to set register twice to clear ITCT for v2 hw */
  923. for (i = 0; i < 2; i++) {
  924. reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
  925. hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
  926. if (!wait_for_completion_timeout(sas_dev->completion,
  927. CLEAR_ITCT_TIMEOUT * HZ)) {
  928. dev_warn(dev, "failed to clear ITCT\n");
  929. return -ETIMEDOUT;
  930. }
  931. memset(itct, 0, sizeof(struct hisi_sas_itct));
  932. }
  933. return 0;
  934. }
  935. static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
  936. {
  937. struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
  938. /* SoC bug workaround */
  939. if (dev_is_sata(sas_dev->sas_device))
  940. clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
  941. }
  942. static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
  943. {
  944. int i, reset_val;
  945. u32 val;
  946. unsigned long end_time;
  947. struct device *dev = hisi_hba->dev;
  948. /* The mask needs to be set depending on the number of phys */
  949. if (hisi_hba->n_phy == 9)
  950. reset_val = 0x1fffff;
  951. else
  952. reset_val = 0x7ffff;
  953. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
  954. /* Disable all of the PHYs */
  955. for (i = 0; i < hisi_hba->n_phy; i++) {
  956. u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
  957. phy_cfg &= ~PHY_CTRL_RESET_MSK;
  958. hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
  959. }
  960. udelay(50);
  961. /* Ensure DMA tx & rx idle */
  962. for (i = 0; i < hisi_hba->n_phy; i++) {
  963. u32 dma_tx_status, dma_rx_status;
  964. end_time = jiffies + msecs_to_jiffies(1000);
  965. while (1) {
  966. dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
  967. DMA_TX_STATUS);
  968. dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
  969. DMA_RX_STATUS);
  970. if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
  971. !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
  972. break;
  973. msleep(20);
  974. if (time_after(jiffies, end_time))
  975. return -EIO;
  976. }
  977. }
  978. /* Ensure axi bus idle */
  979. end_time = jiffies + msecs_to_jiffies(1000);
  980. while (1) {
  981. u32 axi_status =
  982. hisi_sas_read32(hisi_hba, AXI_CFG);
  983. if (axi_status == 0)
  984. break;
  985. msleep(20);
  986. if (time_after(jiffies, end_time))
  987. return -EIO;
  988. }
  989. if (ACPI_HANDLE(dev)) {
  990. acpi_status s;
  991. s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
  992. if (ACPI_FAILURE(s)) {
  993. dev_err(dev, "Reset failed\n");
  994. return -EIO;
  995. }
  996. } else if (hisi_hba->ctrl) {
  997. /* reset and disable clock*/
  998. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
  999. reset_val);
  1000. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
  1001. reset_val);
  1002. msleep(1);
  1003. regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
  1004. if (reset_val != (val & reset_val)) {
  1005. dev_err(dev, "SAS reset fail.\n");
  1006. return -EIO;
  1007. }
  1008. /* De-reset and enable clock*/
  1009. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
  1010. reset_val);
  1011. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
  1012. reset_val);
  1013. msleep(1);
  1014. regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
  1015. &val);
  1016. if (val & reset_val) {
  1017. dev_err(dev, "SAS de-reset fail.\n");
  1018. return -EIO;
  1019. }
  1020. } else {
  1021. dev_err(dev, "no reset method\n");
  1022. return -EINVAL;
  1023. }
  1024. return 0;
  1025. }
  1026. /* This function needs to be called after resetting SAS controller. */
  1027. static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
  1028. {
  1029. u32 cfg;
  1030. int phy_no;
  1031. hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
  1032. for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
  1033. cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
  1034. if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
  1035. continue;
  1036. cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
  1037. hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
  1038. }
  1039. }
  1040. static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
  1041. {
  1042. int phy_no;
  1043. u32 dma_tx_dfx1;
  1044. for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
  1045. if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
  1046. continue;
  1047. dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
  1048. DMA_TX_DFX1);
  1049. if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
  1050. u32 cfg = hisi_sas_phy_read32(hisi_hba,
  1051. phy_no, CON_CONTROL);
  1052. cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
  1053. hisi_sas_phy_write32(hisi_hba, phy_no,
  1054. CON_CONTROL, cfg);
  1055. clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
  1056. }
  1057. }
  1058. }
  1059. static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
  1060. static const struct sig_atten_lu_s sig_atten_lu[] = {
  1061. { &x6000, 0x3016a68 },
  1062. };
  1063. static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
  1064. {
  1065. struct device *dev = hisi_hba->dev;
  1066. u32 sas_phy_ctrl = 0x30b9908;
  1067. u32 signal[3];
  1068. int i;
  1069. /* Global registers init */
  1070. /* Deal with am-max-transmissions quirk */
  1071. if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
  1072. hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
  1073. hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
  1074. 0x2020);
  1075. } /* Else, use defaults -> do nothing */
  1076. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
  1077. (u32)((1ULL << hisi_hba->queue_count) - 1));
  1078. hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
  1079. hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
  1080. hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
  1081. hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
  1082. hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
  1083. hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
  1084. hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
  1085. hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
  1086. hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
  1087. hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
  1088. hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
  1089. hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
  1090. hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
  1091. hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
  1092. hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
  1093. hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
  1094. hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
  1095. hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
  1096. hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
  1097. hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
  1098. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
  1099. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
  1100. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
  1101. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
  1102. for (i = 0; i < hisi_hba->queue_count; i++)
  1103. hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
  1104. hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
  1105. hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
  1106. /* Get sas_phy_ctrl value to deal with TX FFE issue. */
  1107. if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
  1108. signal, ARRAY_SIZE(signal))) {
  1109. for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
  1110. const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
  1111. const struct signal_attenuation_s *att = lookup->att;
  1112. if ((signal[0] == att->de_emphasis) &&
  1113. (signal[1] == att->preshoot) &&
  1114. (signal[2] == att->boost)) {
  1115. sas_phy_ctrl = lookup->sas_phy_ctrl;
  1116. break;
  1117. }
  1118. }
  1119. if (i == ARRAY_SIZE(sig_atten_lu))
  1120. dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
  1121. }
  1122. for (i = 0; i < hisi_hba->n_phy; i++) {
  1123. struct hisi_sas_phy *phy = &hisi_hba->phy[i];
  1124. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1125. u32 prog_phy_link_rate = 0x800;
  1126. if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
  1127. SAS_LINK_RATE_1_5_GBPS)) {
  1128. prog_phy_link_rate = 0x855;
  1129. } else {
  1130. enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
  1131. prog_phy_link_rate =
  1132. hisi_sas_get_prog_phy_linkrate_mask(max) |
  1133. 0x800;
  1134. }
  1135. hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
  1136. prog_phy_link_rate);
  1137. hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
  1138. hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
  1139. hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
  1140. hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
  1141. hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
  1142. hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
  1143. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
  1144. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
  1145. hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
  1146. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
  1147. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
  1148. hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
  1149. hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
  1150. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
  1151. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
  1152. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
  1153. hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
  1154. hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
  1155. hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
  1156. if (hisi_hba->refclk_frequency_mhz == 66)
  1157. hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
  1158. /* else, do nothing -> leave it how you found it */
  1159. }
  1160. for (i = 0; i < hisi_hba->queue_count; i++) {
  1161. /* Delivery queue */
  1162. hisi_sas_write32(hisi_hba,
  1163. DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
  1164. upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
  1165. hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
  1166. lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
  1167. hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
  1168. HISI_SAS_QUEUE_SLOTS);
  1169. /* Completion queue */
  1170. hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
  1171. upper_32_bits(hisi_hba->complete_hdr_dma[i]));
  1172. hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
  1173. lower_32_bits(hisi_hba->complete_hdr_dma[i]));
  1174. hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
  1175. HISI_SAS_QUEUE_SLOTS);
  1176. }
  1177. /* itct */
  1178. hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
  1179. lower_32_bits(hisi_hba->itct_dma));
  1180. hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
  1181. upper_32_bits(hisi_hba->itct_dma));
  1182. /* iost */
  1183. hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
  1184. lower_32_bits(hisi_hba->iost_dma));
  1185. hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
  1186. upper_32_bits(hisi_hba->iost_dma));
  1187. /* breakpoint */
  1188. hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
  1189. lower_32_bits(hisi_hba->breakpoint_dma));
  1190. hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
  1191. upper_32_bits(hisi_hba->breakpoint_dma));
  1192. /* SATA broken msg */
  1193. hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
  1194. lower_32_bits(hisi_hba->sata_breakpoint_dma));
  1195. hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
  1196. upper_32_bits(hisi_hba->sata_breakpoint_dma));
  1197. /* SATA initial fis */
  1198. hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
  1199. lower_32_bits(hisi_hba->initial_fis_dma));
  1200. hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
  1201. upper_32_bits(hisi_hba->initial_fis_dma));
  1202. }
  1203. static void link_timeout_enable_link(struct timer_list *t)
  1204. {
  1205. struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
  1206. int i, reg_val;
  1207. for (i = 0; i < hisi_hba->n_phy; i++) {
  1208. if (hisi_hba->reject_stp_links_msk & BIT(i))
  1209. continue;
  1210. reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
  1211. if (!(reg_val & BIT(0))) {
  1212. hisi_sas_phy_write32(hisi_hba, i,
  1213. CON_CONTROL, 0x7);
  1214. break;
  1215. }
  1216. }
  1217. hisi_hba->timer.function = link_timeout_disable_link;
  1218. mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
  1219. }
  1220. static void link_timeout_disable_link(struct timer_list *t)
  1221. {
  1222. struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
  1223. int i, reg_val;
  1224. reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
  1225. for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
  1226. if (hisi_hba->reject_stp_links_msk & BIT(i))
  1227. continue;
  1228. if (reg_val & BIT(i)) {
  1229. hisi_sas_phy_write32(hisi_hba, i,
  1230. CON_CONTROL, 0x6);
  1231. break;
  1232. }
  1233. }
  1234. hisi_hba->timer.function = link_timeout_enable_link;
  1235. mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
  1236. }
  1237. static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
  1238. {
  1239. hisi_hba->timer.function = link_timeout_disable_link;
  1240. hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
  1241. add_timer(&hisi_hba->timer);
  1242. }
  1243. static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
  1244. {
  1245. struct device *dev = hisi_hba->dev;
  1246. int rc;
  1247. rc = reset_hw_v2_hw(hisi_hba);
  1248. if (rc) {
  1249. dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
  1250. return rc;
  1251. }
  1252. msleep(100);
  1253. init_reg_v2_hw(hisi_hba);
  1254. return 0;
  1255. }
  1256. static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1257. {
  1258. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  1259. cfg |= PHY_CFG_ENA_MSK;
  1260. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  1261. }
  1262. static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1263. {
  1264. u32 context;
  1265. context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
  1266. if (context & (1 << phy_no))
  1267. return true;
  1268. return false;
  1269. }
  1270. static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1271. {
  1272. u32 dfx_val;
  1273. dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
  1274. if (dfx_val & BIT(16))
  1275. return false;
  1276. return true;
  1277. }
  1278. static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1279. {
  1280. int i, max_loop = 1000;
  1281. struct device *dev = hisi_hba->dev;
  1282. u32 status, axi_status, dfx_val, dfx_tx_val;
  1283. for (i = 0; i < max_loop; i++) {
  1284. status = hisi_sas_read32_relaxed(hisi_hba,
  1285. AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
  1286. axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
  1287. dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
  1288. dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
  1289. phy_no, DMA_TX_FIFO_DFX0);
  1290. if ((status == 0x3) && (axi_status == 0x0) &&
  1291. (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
  1292. return true;
  1293. udelay(10);
  1294. }
  1295. dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
  1296. phy_no, status, axi_status,
  1297. dfx_val, dfx_tx_val);
  1298. return false;
  1299. }
  1300. static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1301. {
  1302. int i, max_loop = 1000;
  1303. struct device *dev = hisi_hba->dev;
  1304. u32 status, tx_dfx0;
  1305. for (i = 0; i < max_loop; i++) {
  1306. status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
  1307. status = (status & 0x3fc0) >> 6;
  1308. if (status != 0x1)
  1309. return true;
  1310. tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
  1311. if ((tx_dfx0 & 0x1ff) == 0x2)
  1312. return true;
  1313. udelay(10);
  1314. }
  1315. dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
  1316. phy_no, status, tx_dfx0);
  1317. return false;
  1318. }
  1319. static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1320. {
  1321. if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
  1322. return true;
  1323. if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
  1324. return false;
  1325. if (!wait_io_done_v2_hw(hisi_hba, phy_no))
  1326. return false;
  1327. return true;
  1328. }
  1329. static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1330. {
  1331. u32 cfg, axi_val, dfx0_val, txid_auto;
  1332. struct device *dev = hisi_hba->dev;
  1333. /* Close axi bus. */
  1334. axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
  1335. AM_CTRL_GLOBAL);
  1336. axi_val |= 0x1;
  1337. hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
  1338. AM_CTRL_GLOBAL, axi_val);
  1339. if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
  1340. if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
  1341. goto do_disable;
  1342. /* Reset host controller. */
  1343. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  1344. return;
  1345. }
  1346. dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
  1347. dfx0_val = (dfx0_val & 0x1fc0) >> 6;
  1348. if (dfx0_val != 0x4)
  1349. goto do_disable;
  1350. if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
  1351. dev_warn(dev, "phy%d, wait tx fifo need send break\n",
  1352. phy_no);
  1353. txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
  1354. TXID_AUTO);
  1355. txid_auto |= TXID_AUTO_CTB_MSK;
  1356. hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
  1357. txid_auto);
  1358. }
  1359. do_disable:
  1360. cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  1361. cfg &= ~PHY_CFG_ENA_MSK;
  1362. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  1363. /* Open axi bus. */
  1364. axi_val &= ~0x1;
  1365. hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
  1366. AM_CTRL_GLOBAL, axi_val);
  1367. }
  1368. static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1369. {
  1370. config_id_frame_v2_hw(hisi_hba, phy_no);
  1371. config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
  1372. enable_phy_v2_hw(hisi_hba, phy_no);
  1373. }
  1374. static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1375. {
  1376. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1377. u32 txid_auto;
  1378. hisi_sas_phy_enable(hisi_hba, phy_no, 0);
  1379. if (phy->identify.device_type == SAS_END_DEVICE) {
  1380. txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
  1381. hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
  1382. txid_auto | TX_HARDRST_MSK);
  1383. }
  1384. msleep(100);
  1385. hisi_sas_phy_enable(hisi_hba, phy_no, 1);
  1386. }
  1387. static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1388. {
  1389. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  1390. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1391. struct sas_phy *sphy = sas_phy->phy;
  1392. u32 err4_reg_val, err6_reg_val;
  1393. /* loss dword syn, phy reset problem */
  1394. err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
  1395. /* disparity err, invalid dword */
  1396. err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
  1397. sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
  1398. sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
  1399. sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
  1400. sphy->running_disparity_error_count += err6_reg_val & 0xFF;
  1401. }
  1402. static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
  1403. {
  1404. int i;
  1405. for (i = 0; i < hisi_hba->n_phy; i++) {
  1406. struct hisi_sas_phy *phy = &hisi_hba->phy[i];
  1407. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1408. if (!sas_phy->phy->enabled)
  1409. continue;
  1410. hisi_sas_phy_enable(hisi_hba, i, 1);
  1411. }
  1412. }
  1413. static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
  1414. {
  1415. u32 sl_control;
  1416. sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  1417. sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
  1418. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
  1419. msleep(1);
  1420. sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  1421. sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
  1422. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
  1423. }
  1424. static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
  1425. {
  1426. return SAS_LINK_RATE_12_0_GBPS;
  1427. }
  1428. static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
  1429. struct sas_phy_linkrates *r)
  1430. {
  1431. enum sas_linkrate max = r->maximum_linkrate;
  1432. u32 prog_phy_link_rate = 0x800;
  1433. prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
  1434. hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
  1435. prog_phy_link_rate);
  1436. }
  1437. static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
  1438. {
  1439. int i, bitmap = 0;
  1440. u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
  1441. u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
  1442. for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
  1443. if (phy_state & 1 << i)
  1444. if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
  1445. bitmap |= 1 << i;
  1446. if (hisi_hba->n_phy == 9) {
  1447. u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
  1448. if (phy_state & 1 << 8)
  1449. if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
  1450. PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
  1451. bitmap |= 1 << 9;
  1452. }
  1453. return bitmap;
  1454. }
  1455. /* DQ lock must be taken here */
  1456. static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
  1457. {
  1458. struct hisi_hba *hisi_hba = dq->hisi_hba;
  1459. struct hisi_sas_slot *s, *s1, *s2 = NULL;
  1460. int dlvry_queue = dq->id;
  1461. int wp;
  1462. list_for_each_entry_safe(s, s1, &dq->list, delivery) {
  1463. if (!s->ready)
  1464. break;
  1465. s2 = s;
  1466. list_del(&s->delivery);
  1467. }
  1468. if (!s2)
  1469. return;
  1470. /*
  1471. * Ensure that memories for slots built on other CPUs is observed.
  1472. */
  1473. smp_rmb();
  1474. wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
  1475. hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
  1476. }
  1477. static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
  1478. struct hisi_sas_slot *slot,
  1479. struct hisi_sas_cmd_hdr *hdr,
  1480. struct scatterlist *scatter,
  1481. int n_elem)
  1482. {
  1483. struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
  1484. struct scatterlist *sg;
  1485. int i;
  1486. for_each_sg(scatter, sg, n_elem, i) {
  1487. struct hisi_sas_sge *entry = &sge_page->sge[i];
  1488. entry->addr = cpu_to_le64(sg_dma_address(sg));
  1489. entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
  1490. entry->data_len = cpu_to_le32(sg_dma_len(sg));
  1491. entry->data_off = 0;
  1492. }
  1493. hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
  1494. hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
  1495. }
  1496. static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
  1497. struct hisi_sas_slot *slot)
  1498. {
  1499. struct sas_task *task = slot->task;
  1500. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  1501. struct domain_device *device = task->dev;
  1502. struct hisi_sas_port *port = slot->port;
  1503. struct scatterlist *sg_req;
  1504. struct hisi_sas_device *sas_dev = device->lldd_dev;
  1505. dma_addr_t req_dma_addr;
  1506. unsigned int req_len;
  1507. /* req */
  1508. sg_req = &task->smp_task.smp_req;
  1509. req_dma_addr = sg_dma_address(sg_req);
  1510. req_len = sg_dma_len(&task->smp_task.smp_req);
  1511. /* create header */
  1512. /* dw0 */
  1513. hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
  1514. (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
  1515. (2 << CMD_HDR_CMD_OFF)); /* smp */
  1516. /* map itct entry */
  1517. hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
  1518. (1 << CMD_HDR_FRAME_TYPE_OFF) |
  1519. (DIR_NO_DATA << CMD_HDR_DIR_OFF));
  1520. /* dw2 */
  1521. hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
  1522. (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
  1523. CMD_HDR_MRFL_OFF));
  1524. hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
  1525. hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
  1526. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  1527. }
  1528. static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
  1529. struct hisi_sas_slot *slot)
  1530. {
  1531. struct sas_task *task = slot->task;
  1532. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  1533. struct domain_device *device = task->dev;
  1534. struct hisi_sas_device *sas_dev = device->lldd_dev;
  1535. struct hisi_sas_port *port = slot->port;
  1536. struct sas_ssp_task *ssp_task = &task->ssp_task;
  1537. struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
  1538. struct hisi_sas_tmf_task *tmf = slot->tmf;
  1539. int has_data = 0, priority = !!tmf;
  1540. u8 *buf_cmd;
  1541. u32 dw1 = 0, dw2 = 0;
  1542. hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
  1543. (2 << CMD_HDR_TLR_CTRL_OFF) |
  1544. (port->id << CMD_HDR_PORT_OFF) |
  1545. (priority << CMD_HDR_PRIORITY_OFF) |
  1546. (1 << CMD_HDR_CMD_OFF)); /* ssp */
  1547. dw1 = 1 << CMD_HDR_VDTL_OFF;
  1548. if (tmf) {
  1549. dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
  1550. dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
  1551. } else {
  1552. dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
  1553. switch (scsi_cmnd->sc_data_direction) {
  1554. case DMA_TO_DEVICE:
  1555. has_data = 1;
  1556. dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
  1557. break;
  1558. case DMA_FROM_DEVICE:
  1559. has_data = 1;
  1560. dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
  1561. break;
  1562. default:
  1563. dw1 &= ~CMD_HDR_DIR_MSK;
  1564. }
  1565. }
  1566. /* map itct entry */
  1567. dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
  1568. hdr->dw1 = cpu_to_le32(dw1);
  1569. dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
  1570. + 3) / 4) << CMD_HDR_CFL_OFF) |
  1571. ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
  1572. (2 << CMD_HDR_SG_MOD_OFF);
  1573. hdr->dw2 = cpu_to_le32(dw2);
  1574. hdr->transfer_tags = cpu_to_le32(slot->idx);
  1575. if (has_data)
  1576. prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
  1577. slot->n_elem);
  1578. hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
  1579. hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
  1580. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  1581. buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
  1582. sizeof(struct ssp_frame_hdr);
  1583. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  1584. if (!tmf) {
  1585. buf_cmd[9] = task->ssp_task.task_attr |
  1586. (task->ssp_task.task_prio << 3);
  1587. memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
  1588. task->ssp_task.cmd->cmd_len);
  1589. } else {
  1590. buf_cmd[10] = tmf->tmf;
  1591. switch (tmf->tmf) {
  1592. case TMF_ABORT_TASK:
  1593. case TMF_QUERY_TASK:
  1594. buf_cmd[12] =
  1595. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  1596. buf_cmd[13] =
  1597. tmf->tag_of_task_to_be_managed & 0xff;
  1598. break;
  1599. default:
  1600. break;
  1601. }
  1602. }
  1603. }
  1604. #define TRANS_TX_ERR 0
  1605. #define TRANS_RX_ERR 1
  1606. #define DMA_TX_ERR 2
  1607. #define SIPC_RX_ERR 3
  1608. #define DMA_RX_ERR 4
  1609. #define DMA_TX_ERR_OFF 0
  1610. #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
  1611. #define SIPC_RX_ERR_OFF 16
  1612. #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
  1613. static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
  1614. {
  1615. static const u8 trans_tx_err_code_prio[] = {
  1616. TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
  1617. TRANS_TX_ERR_PHY_NOT_ENABLE,
  1618. TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
  1619. TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
  1620. TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
  1621. RESERVED0,
  1622. TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
  1623. TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
  1624. TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
  1625. TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
  1626. TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
  1627. TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
  1628. TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
  1629. TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
  1630. TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
  1631. TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
  1632. TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
  1633. TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
  1634. TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
  1635. TRANS_TX_ERR_WITH_CLOSE_COMINIT,
  1636. TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
  1637. TRANS_TX_ERR_WITH_BREAK_REQUEST,
  1638. TRANS_TX_ERR_WITH_BREAK_RECEVIED,
  1639. TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
  1640. TRANS_TX_ERR_WITH_CLOSE_NORMAL,
  1641. TRANS_TX_ERR_WITH_NAK_RECEVIED,
  1642. TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
  1643. TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
  1644. TRANS_TX_ERR_WITH_IPTT_CONFLICT,
  1645. TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
  1646. TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
  1647. };
  1648. int index, i;
  1649. for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
  1650. index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
  1651. if (err_msk & (1 << index))
  1652. return trans_tx_err_code_prio[i];
  1653. }
  1654. return -1;
  1655. }
  1656. static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
  1657. {
  1658. static const u8 trans_rx_err_code_prio[] = {
  1659. TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
  1660. TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
  1661. TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
  1662. TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
  1663. TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
  1664. TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
  1665. TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
  1666. TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
  1667. TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
  1668. TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
  1669. TRANS_RX_ERR_WITH_CLOSE_COMINIT,
  1670. TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
  1671. TRANS_RX_ERR_WITH_BREAK_REQUEST,
  1672. TRANS_RX_ERR_WITH_BREAK_RECEVIED,
  1673. RESERVED1,
  1674. TRANS_RX_ERR_WITH_CLOSE_NORMAL,
  1675. TRANS_RX_ERR_WITH_DATA_LEN0,
  1676. TRANS_RX_ERR_WITH_BAD_HASH,
  1677. TRANS_RX_XRDY_WLEN_ZERO_ERR,
  1678. TRANS_RX_SSP_FRM_LEN_ERR,
  1679. RESERVED2,
  1680. RESERVED3,
  1681. RESERVED4,
  1682. RESERVED5,
  1683. TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
  1684. TRANS_RX_SMP_FRM_LEN_ERR,
  1685. TRANS_RX_SMP_RESP_TIMEOUT_ERR,
  1686. RESERVED6,
  1687. RESERVED7,
  1688. RESERVED8,
  1689. RESERVED9,
  1690. TRANS_RX_R_ERR,
  1691. };
  1692. int index, i;
  1693. for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
  1694. index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
  1695. if (err_msk & (1 << index))
  1696. return trans_rx_err_code_prio[i];
  1697. }
  1698. return -1;
  1699. }
  1700. static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
  1701. {
  1702. static const u8 dma_tx_err_code_prio[] = {
  1703. DMA_TX_UNEXP_XFER_ERR,
  1704. DMA_TX_UNEXP_RETRANS_ERR,
  1705. DMA_TX_XFER_LEN_OVERFLOW,
  1706. DMA_TX_XFER_OFFSET_ERR,
  1707. DMA_TX_RAM_ECC_ERR,
  1708. DMA_TX_DIF_LEN_ALIGN_ERR,
  1709. DMA_TX_DIF_CRC_ERR,
  1710. DMA_TX_DIF_APP_ERR,
  1711. DMA_TX_DIF_RPP_ERR,
  1712. DMA_TX_DATA_SGL_OVERFLOW,
  1713. DMA_TX_DIF_SGL_OVERFLOW,
  1714. };
  1715. int index, i;
  1716. for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
  1717. index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
  1718. err_msk = err_msk & DMA_TX_ERR_MSK;
  1719. if (err_msk & (1 << index))
  1720. return dma_tx_err_code_prio[i];
  1721. }
  1722. return -1;
  1723. }
  1724. static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
  1725. {
  1726. static const u8 sipc_rx_err_code_prio[] = {
  1727. SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
  1728. SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
  1729. SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
  1730. SIPC_RX_WRSETUP_LEN_ODD_ERR,
  1731. SIPC_RX_WRSETUP_LEN_ZERO_ERR,
  1732. SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
  1733. SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
  1734. SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
  1735. SIPC_RX_SATA_UNEXP_FIS_ERR,
  1736. SIPC_RX_WRSETUP_ESTATUS_ERR,
  1737. SIPC_RX_DATA_UNDERFLOW_ERR,
  1738. };
  1739. int index, i;
  1740. for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
  1741. index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
  1742. err_msk = err_msk & SIPC_RX_ERR_MSK;
  1743. if (err_msk & (1 << (index + 0x10)))
  1744. return sipc_rx_err_code_prio[i];
  1745. }
  1746. return -1;
  1747. }
  1748. static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
  1749. {
  1750. static const u8 dma_rx_err_code_prio[] = {
  1751. DMA_RX_UNKNOWN_FRM_ERR,
  1752. DMA_RX_DATA_LEN_OVERFLOW,
  1753. DMA_RX_DATA_LEN_UNDERFLOW,
  1754. DMA_RX_DATA_OFFSET_ERR,
  1755. RESERVED10,
  1756. DMA_RX_SATA_FRAME_TYPE_ERR,
  1757. DMA_RX_RESP_BUF_OVERFLOW,
  1758. DMA_RX_UNEXP_RETRANS_RESP_ERR,
  1759. DMA_RX_UNEXP_NORM_RESP_ERR,
  1760. DMA_RX_UNEXP_RDFRAME_ERR,
  1761. DMA_RX_PIO_DATA_LEN_ERR,
  1762. DMA_RX_RDSETUP_STATUS_ERR,
  1763. DMA_RX_RDSETUP_STATUS_DRQ_ERR,
  1764. DMA_RX_RDSETUP_STATUS_BSY_ERR,
  1765. DMA_RX_RDSETUP_LEN_ODD_ERR,
  1766. DMA_RX_RDSETUP_LEN_ZERO_ERR,
  1767. DMA_RX_RDSETUP_LEN_OVER_ERR,
  1768. DMA_RX_RDSETUP_OFFSET_ERR,
  1769. DMA_RX_RDSETUP_ACTIVE_ERR,
  1770. DMA_RX_RDSETUP_ESTATUS_ERR,
  1771. DMA_RX_RAM_ECC_ERR,
  1772. DMA_RX_DIF_CRC_ERR,
  1773. DMA_RX_DIF_APP_ERR,
  1774. DMA_RX_DIF_RPP_ERR,
  1775. DMA_RX_DATA_SGL_OVERFLOW,
  1776. DMA_RX_DIF_SGL_OVERFLOW,
  1777. };
  1778. int index, i;
  1779. for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
  1780. index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
  1781. if (err_msk & (1 << index))
  1782. return dma_rx_err_code_prio[i];
  1783. }
  1784. return -1;
  1785. }
  1786. /* by default, task resp is complete */
  1787. static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
  1788. struct sas_task *task,
  1789. struct hisi_sas_slot *slot,
  1790. int err_phase)
  1791. {
  1792. struct task_status_struct *ts = &task->task_status;
  1793. struct hisi_sas_err_record_v2 *err_record =
  1794. hisi_sas_status_buf_addr_mem(slot);
  1795. u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
  1796. u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
  1797. u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
  1798. u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
  1799. u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
  1800. int error = -1;
  1801. if (err_phase == 1) {
  1802. /* error in TX phase, the priority of error is: DW2 > DW0 */
  1803. error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
  1804. if (error == -1)
  1805. error = parse_trans_tx_err_code_v2_hw(
  1806. trans_tx_fail_type);
  1807. } else if (err_phase == 2) {
  1808. /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
  1809. error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
  1810. if (error == -1) {
  1811. error = parse_dma_rx_err_code_v2_hw(
  1812. dma_rx_err_type);
  1813. if (error == -1)
  1814. error = parse_sipc_rx_err_code_v2_hw(
  1815. sipc_rx_err_type);
  1816. }
  1817. }
  1818. switch (task->task_proto) {
  1819. case SAS_PROTOCOL_SSP:
  1820. {
  1821. switch (error) {
  1822. case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
  1823. {
  1824. ts->stat = SAS_OPEN_REJECT;
  1825. ts->open_rej_reason = SAS_OREJ_NO_DEST;
  1826. break;
  1827. }
  1828. case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
  1829. {
  1830. ts->stat = SAS_OPEN_REJECT;
  1831. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1832. break;
  1833. }
  1834. case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
  1835. {
  1836. ts->stat = SAS_OPEN_REJECT;
  1837. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1838. break;
  1839. }
  1840. case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
  1841. {
  1842. ts->stat = SAS_OPEN_REJECT;
  1843. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  1844. break;
  1845. }
  1846. case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
  1847. {
  1848. ts->stat = SAS_OPEN_REJECT;
  1849. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1850. break;
  1851. }
  1852. case DMA_RX_UNEXP_NORM_RESP_ERR:
  1853. case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
  1854. case DMA_RX_RESP_BUF_OVERFLOW:
  1855. {
  1856. ts->stat = SAS_OPEN_REJECT;
  1857. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1858. break;
  1859. }
  1860. case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
  1861. {
  1862. /* not sure */
  1863. ts->stat = SAS_DEV_NO_RESPONSE;
  1864. break;
  1865. }
  1866. case DMA_RX_DATA_LEN_OVERFLOW:
  1867. {
  1868. ts->stat = SAS_DATA_OVERRUN;
  1869. ts->residual = 0;
  1870. break;
  1871. }
  1872. case DMA_RX_DATA_LEN_UNDERFLOW:
  1873. {
  1874. ts->residual = trans_tx_fail_type;
  1875. ts->stat = SAS_DATA_UNDERRUN;
  1876. break;
  1877. }
  1878. case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
  1879. case TRANS_TX_ERR_PHY_NOT_ENABLE:
  1880. case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
  1881. case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
  1882. case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
  1883. case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
  1884. case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
  1885. case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
  1886. case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
  1887. case TRANS_TX_ERR_WITH_BREAK_REQUEST:
  1888. case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
  1889. case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
  1890. case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
  1891. case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
  1892. case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
  1893. case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
  1894. case TRANS_TX_ERR_WITH_NAK_RECEVIED:
  1895. case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
  1896. case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
  1897. case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
  1898. case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
  1899. case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
  1900. case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
  1901. case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
  1902. case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
  1903. case TRANS_RX_ERR_WITH_BREAK_REQUEST:
  1904. case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
  1905. case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
  1906. case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
  1907. case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
  1908. case TRANS_TX_ERR_FRAME_TXED:
  1909. case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
  1910. case TRANS_RX_ERR_WITH_DATA_LEN0:
  1911. case TRANS_RX_ERR_WITH_BAD_HASH:
  1912. case TRANS_RX_XRDY_WLEN_ZERO_ERR:
  1913. case TRANS_RX_SSP_FRM_LEN_ERR:
  1914. case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
  1915. case DMA_TX_DATA_SGL_OVERFLOW:
  1916. case DMA_TX_UNEXP_XFER_ERR:
  1917. case DMA_TX_UNEXP_RETRANS_ERR:
  1918. case DMA_TX_XFER_LEN_OVERFLOW:
  1919. case DMA_TX_XFER_OFFSET_ERR:
  1920. case SIPC_RX_DATA_UNDERFLOW_ERR:
  1921. case DMA_RX_DATA_SGL_OVERFLOW:
  1922. case DMA_RX_DATA_OFFSET_ERR:
  1923. case DMA_RX_RDSETUP_LEN_ODD_ERR:
  1924. case DMA_RX_RDSETUP_LEN_ZERO_ERR:
  1925. case DMA_RX_RDSETUP_LEN_OVER_ERR:
  1926. case DMA_RX_SATA_FRAME_TYPE_ERR:
  1927. case DMA_RX_UNKNOWN_FRM_ERR:
  1928. {
  1929. /* This will request a retry */
  1930. ts->stat = SAS_QUEUE_FULL;
  1931. slot->abort = 1;
  1932. break;
  1933. }
  1934. default:
  1935. break;
  1936. }
  1937. }
  1938. break;
  1939. case SAS_PROTOCOL_SMP:
  1940. ts->stat = SAM_STAT_CHECK_CONDITION;
  1941. break;
  1942. case SAS_PROTOCOL_SATA:
  1943. case SAS_PROTOCOL_STP:
  1944. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1945. {
  1946. switch (error) {
  1947. case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
  1948. {
  1949. ts->stat = SAS_OPEN_REJECT;
  1950. ts->open_rej_reason = SAS_OREJ_NO_DEST;
  1951. break;
  1952. }
  1953. case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
  1954. {
  1955. ts->resp = SAS_TASK_UNDELIVERED;
  1956. ts->stat = SAS_DEV_NO_RESPONSE;
  1957. break;
  1958. }
  1959. case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
  1960. {
  1961. ts->stat = SAS_OPEN_REJECT;
  1962. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1963. break;
  1964. }
  1965. case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
  1966. {
  1967. ts->stat = SAS_OPEN_REJECT;
  1968. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1969. break;
  1970. }
  1971. case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
  1972. {
  1973. ts->stat = SAS_OPEN_REJECT;
  1974. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1975. break;
  1976. }
  1977. case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
  1978. {
  1979. ts->stat = SAS_OPEN_REJECT;
  1980. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1981. break;
  1982. }
  1983. case DMA_RX_RESP_BUF_OVERFLOW:
  1984. case DMA_RX_UNEXP_NORM_RESP_ERR:
  1985. case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
  1986. {
  1987. ts->stat = SAS_OPEN_REJECT;
  1988. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1989. break;
  1990. }
  1991. case DMA_RX_DATA_LEN_OVERFLOW:
  1992. {
  1993. ts->stat = SAS_DATA_OVERRUN;
  1994. ts->residual = 0;
  1995. break;
  1996. }
  1997. case DMA_RX_DATA_LEN_UNDERFLOW:
  1998. {
  1999. ts->residual = trans_tx_fail_type;
  2000. ts->stat = SAS_DATA_UNDERRUN;
  2001. break;
  2002. }
  2003. case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
  2004. case TRANS_TX_ERR_PHY_NOT_ENABLE:
  2005. case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
  2006. case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
  2007. case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
  2008. case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
  2009. case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
  2010. case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
  2011. case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
  2012. case TRANS_TX_ERR_WITH_BREAK_REQUEST:
  2013. case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
  2014. case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
  2015. case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
  2016. case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
  2017. case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
  2018. case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
  2019. case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
  2020. case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
  2021. case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
  2022. case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
  2023. case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
  2024. case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
  2025. case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
  2026. case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
  2027. case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
  2028. case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
  2029. case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
  2030. case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
  2031. case TRANS_RX_ERR_WITH_BREAK_REQUEST:
  2032. case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
  2033. case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
  2034. case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
  2035. case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
  2036. case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
  2037. case TRANS_RX_ERR_WITH_DATA_LEN0:
  2038. case TRANS_RX_ERR_WITH_BAD_HASH:
  2039. case TRANS_RX_XRDY_WLEN_ZERO_ERR:
  2040. case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
  2041. case DMA_TX_DATA_SGL_OVERFLOW:
  2042. case DMA_TX_UNEXP_XFER_ERR:
  2043. case DMA_TX_UNEXP_RETRANS_ERR:
  2044. case DMA_TX_XFER_LEN_OVERFLOW:
  2045. case DMA_TX_XFER_OFFSET_ERR:
  2046. case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
  2047. case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
  2048. case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
  2049. case SIPC_RX_WRSETUP_LEN_ODD_ERR:
  2050. case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
  2051. case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
  2052. case SIPC_RX_SATA_UNEXP_FIS_ERR:
  2053. case DMA_RX_DATA_SGL_OVERFLOW:
  2054. case DMA_RX_DATA_OFFSET_ERR:
  2055. case DMA_RX_SATA_FRAME_TYPE_ERR:
  2056. case DMA_RX_UNEXP_RDFRAME_ERR:
  2057. case DMA_RX_PIO_DATA_LEN_ERR:
  2058. case DMA_RX_RDSETUP_STATUS_ERR:
  2059. case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
  2060. case DMA_RX_RDSETUP_STATUS_BSY_ERR:
  2061. case DMA_RX_RDSETUP_LEN_ODD_ERR:
  2062. case DMA_RX_RDSETUP_LEN_ZERO_ERR:
  2063. case DMA_RX_RDSETUP_LEN_OVER_ERR:
  2064. case DMA_RX_RDSETUP_OFFSET_ERR:
  2065. case DMA_RX_RDSETUP_ACTIVE_ERR:
  2066. case DMA_RX_RDSETUP_ESTATUS_ERR:
  2067. case DMA_RX_UNKNOWN_FRM_ERR:
  2068. case TRANS_RX_SSP_FRM_LEN_ERR:
  2069. case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
  2070. {
  2071. slot->abort = 1;
  2072. ts->stat = SAS_PHY_DOWN;
  2073. break;
  2074. }
  2075. default:
  2076. {
  2077. ts->stat = SAS_PROTO_RESPONSE;
  2078. break;
  2079. }
  2080. }
  2081. hisi_sas_sata_done(task, slot);
  2082. }
  2083. break;
  2084. default:
  2085. break;
  2086. }
  2087. }
  2088. static void slot_complete_v2_hw(struct hisi_hba *hisi_hba,
  2089. struct hisi_sas_slot *slot)
  2090. {
  2091. struct sas_task *task = slot->task;
  2092. struct hisi_sas_device *sas_dev;
  2093. struct device *dev = hisi_hba->dev;
  2094. struct task_status_struct *ts;
  2095. struct domain_device *device;
  2096. struct sas_ha_struct *ha;
  2097. struct hisi_sas_complete_v2_hdr *complete_queue =
  2098. hisi_hba->complete_hdr[slot->cmplt_queue];
  2099. struct hisi_sas_complete_v2_hdr *complete_hdr =
  2100. &complete_queue[slot->cmplt_queue_slot];
  2101. unsigned long flags;
  2102. bool is_internal = slot->is_internal;
  2103. u32 dw0;
  2104. if (unlikely(!task || !task->lldd_task || !task->dev))
  2105. return;
  2106. ts = &task->task_status;
  2107. device = task->dev;
  2108. ha = device->port->ha;
  2109. sas_dev = device->lldd_dev;
  2110. spin_lock_irqsave(&task->task_state_lock, flags);
  2111. task->task_state_flags &=
  2112. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  2113. spin_unlock_irqrestore(&task->task_state_lock, flags);
  2114. memset(ts, 0, sizeof(*ts));
  2115. ts->resp = SAS_TASK_COMPLETE;
  2116. if (unlikely(!sas_dev)) {
  2117. dev_dbg(dev, "slot complete: port has no device\n");
  2118. ts->stat = SAS_PHY_DOWN;
  2119. goto out;
  2120. }
  2121. /* Use SAS+TMF status codes */
  2122. dw0 = le32_to_cpu(complete_hdr->dw0);
  2123. switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
  2124. CMPLT_HDR_ABORT_STAT_OFF) {
  2125. case STAT_IO_ABORTED:
  2126. /* this io has been aborted by abort command */
  2127. ts->stat = SAS_ABORTED_TASK;
  2128. goto out;
  2129. case STAT_IO_COMPLETE:
  2130. /* internal abort command complete */
  2131. ts->stat = TMF_RESP_FUNC_SUCC;
  2132. del_timer(&slot->internal_abort_timer);
  2133. goto out;
  2134. case STAT_IO_NO_DEVICE:
  2135. ts->stat = TMF_RESP_FUNC_COMPLETE;
  2136. del_timer(&slot->internal_abort_timer);
  2137. goto out;
  2138. case STAT_IO_NOT_VALID:
  2139. /* abort single io, controller don't find
  2140. * the io need to abort
  2141. */
  2142. ts->stat = TMF_RESP_FUNC_FAILED;
  2143. del_timer(&slot->internal_abort_timer);
  2144. goto out;
  2145. default:
  2146. break;
  2147. }
  2148. if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
  2149. u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
  2150. >> CMPLT_HDR_ERR_PHASE_OFF;
  2151. u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
  2152. /* Analyse error happens on which phase TX or RX */
  2153. if (ERR_ON_TX_PHASE(err_phase))
  2154. slot_err_v2_hw(hisi_hba, task, slot, 1);
  2155. else if (ERR_ON_RX_PHASE(err_phase))
  2156. slot_err_v2_hw(hisi_hba, task, slot, 2);
  2157. if (ts->stat != SAS_DATA_UNDERRUN)
  2158. dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
  2159. slot->idx, task, sas_dev->device_id,
  2160. complete_hdr->dw0, complete_hdr->dw1,
  2161. complete_hdr->act, complete_hdr->dw3,
  2162. error_info[0], error_info[1],
  2163. error_info[2], error_info[3]);
  2164. if (unlikely(slot->abort)) {
  2165. sas_task_abort(task);
  2166. return;
  2167. }
  2168. goto out;
  2169. }
  2170. switch (task->task_proto) {
  2171. case SAS_PROTOCOL_SSP:
  2172. {
  2173. struct hisi_sas_status_buffer *status_buffer =
  2174. hisi_sas_status_buf_addr_mem(slot);
  2175. struct ssp_response_iu *iu = (struct ssp_response_iu *)
  2176. &status_buffer->iu[0];
  2177. sas_ssp_task_response(dev, task, iu);
  2178. break;
  2179. }
  2180. case SAS_PROTOCOL_SMP:
  2181. {
  2182. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  2183. void *to = page_address(sg_page(sg_resp));
  2184. ts->stat = SAM_STAT_GOOD;
  2185. dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
  2186. DMA_TO_DEVICE);
  2187. memcpy(to + sg_resp->offset,
  2188. hisi_sas_status_buf_addr_mem(slot) +
  2189. sizeof(struct hisi_sas_err_record),
  2190. sg_resp->length);
  2191. break;
  2192. }
  2193. case SAS_PROTOCOL_SATA:
  2194. case SAS_PROTOCOL_STP:
  2195. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  2196. {
  2197. ts->stat = SAM_STAT_GOOD;
  2198. hisi_sas_sata_done(task, slot);
  2199. break;
  2200. }
  2201. default:
  2202. ts->stat = SAM_STAT_CHECK_CONDITION;
  2203. break;
  2204. }
  2205. if (!slot->port->port_attached) {
  2206. dev_warn(dev, "slot complete: port %d has removed\n",
  2207. slot->port->sas_port.id);
  2208. ts->stat = SAS_PHY_DOWN;
  2209. }
  2210. out:
  2211. spin_lock_irqsave(&task->task_state_lock, flags);
  2212. if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
  2213. spin_unlock_irqrestore(&task->task_state_lock, flags);
  2214. dev_info(dev, "slot complete: task(%pK) aborted\n", task);
  2215. return;
  2216. }
  2217. task->task_state_flags |= SAS_TASK_STATE_DONE;
  2218. spin_unlock_irqrestore(&task->task_state_lock, flags);
  2219. hisi_sas_slot_task_free(hisi_hba, task, slot);
  2220. if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
  2221. spin_lock_irqsave(&device->done_lock, flags);
  2222. if (test_bit(SAS_HA_FROZEN, &ha->state)) {
  2223. spin_unlock_irqrestore(&device->done_lock, flags);
  2224. dev_info(dev, "slot complete: task(%pK) ignored\n",
  2225. task);
  2226. return;
  2227. }
  2228. spin_unlock_irqrestore(&device->done_lock, flags);
  2229. }
  2230. if (task->task_done)
  2231. task->task_done(task);
  2232. }
  2233. static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
  2234. struct hisi_sas_slot *slot)
  2235. {
  2236. struct sas_task *task = slot->task;
  2237. struct domain_device *device = task->dev;
  2238. struct domain_device *parent_dev = device->parent;
  2239. struct hisi_sas_device *sas_dev = device->lldd_dev;
  2240. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  2241. struct asd_sas_port *sas_port = device->port;
  2242. struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
  2243. struct hisi_sas_tmf_task *tmf = slot->tmf;
  2244. u8 *buf_cmd;
  2245. int has_data = 0, hdr_tag = 0;
  2246. u32 dw0, dw1 = 0, dw2 = 0;
  2247. /* create header */
  2248. /* dw0 */
  2249. dw0 = port->id << CMD_HDR_PORT_OFF;
  2250. if (parent_dev && dev_is_expander(parent_dev->dev_type))
  2251. dw0 |= 3 << CMD_HDR_CMD_OFF;
  2252. else
  2253. dw0 |= 4 << CMD_HDR_CMD_OFF;
  2254. if (tmf && tmf->force_phy) {
  2255. dw0 |= CMD_HDR_FORCE_PHY_MSK;
  2256. dw0 |= (1 << tmf->phy_id) << CMD_HDR_PHY_ID_OFF;
  2257. }
  2258. hdr->dw0 = cpu_to_le32(dw0);
  2259. /* dw1 */
  2260. switch (task->data_dir) {
  2261. case DMA_TO_DEVICE:
  2262. has_data = 1;
  2263. dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
  2264. break;
  2265. case DMA_FROM_DEVICE:
  2266. has_data = 1;
  2267. dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
  2268. break;
  2269. default:
  2270. dw1 &= ~CMD_HDR_DIR_MSK;
  2271. }
  2272. if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
  2273. (task->ata_task.fis.control & ATA_SRST))
  2274. dw1 |= 1 << CMD_HDR_RESET_OFF;
  2275. dw1 |= (hisi_sas_get_ata_protocol(
  2276. &task->ata_task.fis, task->data_dir))
  2277. << CMD_HDR_FRAME_TYPE_OFF;
  2278. dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
  2279. hdr->dw1 = cpu_to_le32(dw1);
  2280. /* dw2 */
  2281. if (task->ata_task.use_ncq) {
  2282. struct ata_queued_cmd *qc = task->uldd_task;
  2283. hdr_tag = qc->tag;
  2284. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  2285. dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
  2286. }
  2287. dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
  2288. 2 << CMD_HDR_SG_MOD_OFF;
  2289. hdr->dw2 = cpu_to_le32(dw2);
  2290. /* dw3 */
  2291. hdr->transfer_tags = cpu_to_le32(slot->idx);
  2292. if (has_data)
  2293. prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
  2294. slot->n_elem);
  2295. hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
  2296. hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
  2297. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  2298. buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
  2299. if (likely(!task->ata_task.device_control_reg_update))
  2300. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  2301. /* fill in command FIS */
  2302. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  2303. }
  2304. static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
  2305. {
  2306. struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
  2307. struct hisi_sas_port *port = slot->port;
  2308. struct asd_sas_port *asd_sas_port;
  2309. struct asd_sas_phy *sas_phy;
  2310. if (!port)
  2311. return;
  2312. asd_sas_port = &port->sas_port;
  2313. /* Kick the hardware - send break command */
  2314. list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
  2315. struct hisi_sas_phy *phy = sas_phy->lldd_phy;
  2316. struct hisi_hba *hisi_hba = phy->hisi_hba;
  2317. int phy_no = sas_phy->id;
  2318. u32 link_dfx2;
  2319. link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
  2320. if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
  2321. (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
  2322. u32 txid_auto;
  2323. txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
  2324. TXID_AUTO);
  2325. txid_auto |= TXID_AUTO_CTB_MSK;
  2326. hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
  2327. txid_auto);
  2328. return;
  2329. }
  2330. }
  2331. }
  2332. static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
  2333. struct hisi_sas_slot *slot,
  2334. int device_id, int abort_flag, int tag_to_abort)
  2335. {
  2336. struct sas_task *task = slot->task;
  2337. struct domain_device *dev = task->dev;
  2338. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  2339. struct hisi_sas_port *port = slot->port;
  2340. struct timer_list *timer = &slot->internal_abort_timer;
  2341. /* setup the quirk timer */
  2342. timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
  2343. /* Set the timeout to 10ms less than internal abort timeout */
  2344. mod_timer(timer, jiffies + msecs_to_jiffies(100));
  2345. /* dw0 */
  2346. hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
  2347. (port->id << CMD_HDR_PORT_OFF) |
  2348. (dev_is_sata(dev) <<
  2349. CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
  2350. (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
  2351. /* dw1 */
  2352. hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
  2353. /* dw7 */
  2354. hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
  2355. hdr->transfer_tags = cpu_to_le32(slot->idx);
  2356. }
  2357. static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
  2358. {
  2359. int i, res = IRQ_HANDLED;
  2360. u32 port_id, link_rate;
  2361. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  2362. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  2363. struct device *dev = hisi_hba->dev;
  2364. u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
  2365. struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
  2366. unsigned long flags;
  2367. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
  2368. if (is_sata_phy_v2_hw(hisi_hba, phy_no))
  2369. goto end;
  2370. del_timer(&phy->timer);
  2371. if (phy_no == 8) {
  2372. u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
  2373. port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
  2374. PORT_STATE_PHY8_PORT_NUM_OFF;
  2375. link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
  2376. PORT_STATE_PHY8_CONN_RATE_OFF;
  2377. } else {
  2378. port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
  2379. port_id = (port_id >> (4 * phy_no)) & 0xf;
  2380. link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
  2381. link_rate = (link_rate >> (phy_no * 4)) & 0xf;
  2382. }
  2383. if (port_id == 0xf) {
  2384. dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
  2385. res = IRQ_NONE;
  2386. goto end;
  2387. }
  2388. for (i = 0; i < 6; i++) {
  2389. u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
  2390. RX_IDAF_DWORD0 + (i * 4));
  2391. frame_rcvd[i] = __swab32(idaf);
  2392. }
  2393. sas_phy->linkrate = link_rate;
  2394. sas_phy->oob_mode = SAS_OOB_MODE;
  2395. memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
  2396. dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
  2397. phy->port_id = port_id;
  2398. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  2399. phy->phy_type |= PORT_TYPE_SAS;
  2400. phy->phy_attached = 1;
  2401. phy->identify.device_type = id->dev_type;
  2402. phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
  2403. if (phy->identify.device_type == SAS_END_DEVICE)
  2404. phy->identify.target_port_protocols =
  2405. SAS_PROTOCOL_SSP;
  2406. else if (phy->identify.device_type != SAS_PHY_UNUSED) {
  2407. phy->identify.target_port_protocols =
  2408. SAS_PROTOCOL_SMP;
  2409. if (!timer_pending(&hisi_hba->timer))
  2410. set_link_timer_quirk(hisi_hba);
  2411. }
  2412. hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
  2413. spin_lock_irqsave(&phy->lock, flags);
  2414. if (phy->reset_completion) {
  2415. phy->in_reset = 0;
  2416. complete(phy->reset_completion);
  2417. }
  2418. spin_unlock_irqrestore(&phy->lock, flags);
  2419. end:
  2420. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
  2421. CHL_INT0_SL_PHY_ENABLE_MSK);
  2422. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
  2423. return res;
  2424. }
  2425. static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
  2426. {
  2427. u32 port_state;
  2428. port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
  2429. if (port_state & 0x1ff)
  2430. return true;
  2431. return false;
  2432. }
  2433. static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
  2434. {
  2435. u32 phy_state, sl_ctrl, txid_auto;
  2436. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  2437. struct hisi_sas_port *port = phy->port;
  2438. struct device *dev = hisi_hba->dev;
  2439. del_timer(&phy->timer);
  2440. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
  2441. phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
  2442. dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
  2443. hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
  2444. sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  2445. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
  2446. sl_ctrl & ~SL_CONTROL_CTA_MSK);
  2447. if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
  2448. if (!check_any_wideports_v2_hw(hisi_hba) &&
  2449. timer_pending(&hisi_hba->timer))
  2450. del_timer(&hisi_hba->timer);
  2451. txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
  2452. hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
  2453. txid_auto | TXID_AUTO_CT3_MSK);
  2454. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
  2455. hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
  2456. return IRQ_HANDLED;
  2457. }
  2458. static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
  2459. {
  2460. struct hisi_hba *hisi_hba = p;
  2461. u32 irq_msk;
  2462. int phy_no = 0;
  2463. irqreturn_t res = IRQ_NONE;
  2464. irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
  2465. >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
  2466. while (irq_msk) {
  2467. if (irq_msk & 1) {
  2468. u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
  2469. CHL_INT0);
  2470. switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
  2471. CHL_INT0_SL_PHY_ENABLE_MSK)) {
  2472. case CHL_INT0_SL_PHY_ENABLE_MSK:
  2473. /* phy up */
  2474. if (phy_up_v2_hw(phy_no, hisi_hba) ==
  2475. IRQ_HANDLED)
  2476. res = IRQ_HANDLED;
  2477. break;
  2478. case CHL_INT0_NOT_RDY_MSK:
  2479. /* phy down */
  2480. if (phy_down_v2_hw(phy_no, hisi_hba) ==
  2481. IRQ_HANDLED)
  2482. res = IRQ_HANDLED;
  2483. break;
  2484. case (CHL_INT0_NOT_RDY_MSK |
  2485. CHL_INT0_SL_PHY_ENABLE_MSK):
  2486. reg_value = hisi_sas_read32(hisi_hba,
  2487. PHY_STATE);
  2488. if (reg_value & BIT(phy_no)) {
  2489. /* phy up */
  2490. if (phy_up_v2_hw(phy_no, hisi_hba) ==
  2491. IRQ_HANDLED)
  2492. res = IRQ_HANDLED;
  2493. } else {
  2494. /* phy down */
  2495. if (phy_down_v2_hw(phy_no, hisi_hba) ==
  2496. IRQ_HANDLED)
  2497. res = IRQ_HANDLED;
  2498. }
  2499. break;
  2500. default:
  2501. break;
  2502. }
  2503. }
  2504. irq_msk >>= 1;
  2505. phy_no++;
  2506. }
  2507. return res;
  2508. }
  2509. static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
  2510. {
  2511. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  2512. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  2513. u32 bcast_status;
  2514. hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
  2515. bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
  2516. if ((bcast_status & RX_BCAST_CHG_MSK) &&
  2517. !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
  2518. sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  2519. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
  2520. CHL_INT0_SL_RX_BCST_ACK_MSK);
  2521. hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
  2522. }
  2523. static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
  2524. {
  2525. .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
  2526. .msg = "dmac_tx_ecc_bad_err",
  2527. },
  2528. {
  2529. .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
  2530. .msg = "dmac_rx_ecc_bad_err",
  2531. },
  2532. {
  2533. .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
  2534. .msg = "dma_tx_axi_wr_err",
  2535. },
  2536. {
  2537. .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
  2538. .msg = "dma_tx_axi_rd_err",
  2539. },
  2540. {
  2541. .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
  2542. .msg = "dma_rx_axi_wr_err",
  2543. },
  2544. {
  2545. .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
  2546. .msg = "dma_rx_axi_rd_err",
  2547. },
  2548. };
  2549. static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
  2550. {
  2551. struct hisi_hba *hisi_hba = p;
  2552. struct device *dev = hisi_hba->dev;
  2553. u32 ent_msk, ent_tmp, irq_msk;
  2554. int phy_no = 0;
  2555. ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
  2556. ent_tmp = ent_msk;
  2557. ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
  2558. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
  2559. irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
  2560. HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
  2561. while (irq_msk) {
  2562. u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
  2563. CHL_INT0);
  2564. u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
  2565. CHL_INT1);
  2566. u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
  2567. CHL_INT2);
  2568. if ((irq_msk & (1 << phy_no)) && irq_value1) {
  2569. int i;
  2570. for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
  2571. const struct hisi_sas_hw_error *error =
  2572. &port_ecc_axi_error[i];
  2573. if (!(irq_value1 & error->irq_msk))
  2574. continue;
  2575. dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
  2576. error->msg, phy_no, irq_value1);
  2577. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  2578. }
  2579. hisi_sas_phy_write32(hisi_hba, phy_no,
  2580. CHL_INT1, irq_value1);
  2581. }
  2582. if ((irq_msk & (1 << phy_no)) && irq_value2) {
  2583. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  2584. if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
  2585. dev_warn(dev, "phy%d identify timeout\n",
  2586. phy_no);
  2587. hisi_sas_notify_phy_event(phy,
  2588. HISI_PHYE_LINK_RESET);
  2589. }
  2590. hisi_sas_phy_write32(hisi_hba, phy_no,
  2591. CHL_INT2, irq_value2);
  2592. }
  2593. if ((irq_msk & (1 << phy_no)) && irq_value0) {
  2594. if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
  2595. phy_bcast_v2_hw(phy_no, hisi_hba);
  2596. if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
  2597. hisi_sas_phy_oob_ready(hisi_hba, phy_no);
  2598. hisi_sas_phy_write32(hisi_hba, phy_no,
  2599. CHL_INT0, irq_value0
  2600. & (~CHL_INT0_HOTPLUG_TOUT_MSK)
  2601. & (~CHL_INT0_SL_PHY_ENABLE_MSK)
  2602. & (~CHL_INT0_NOT_RDY_MSK));
  2603. }
  2604. irq_msk &= ~(1 << phy_no);
  2605. phy_no++;
  2606. }
  2607. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
  2608. return IRQ_HANDLED;
  2609. }
  2610. static void
  2611. one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
  2612. {
  2613. struct device *dev = hisi_hba->dev;
  2614. const struct hisi_sas_hw_error *ecc_error;
  2615. u32 val;
  2616. int i;
  2617. for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
  2618. ecc_error = &one_bit_ecc_errors[i];
  2619. if (irq_value & ecc_error->irq_msk) {
  2620. val = hisi_sas_read32(hisi_hba, ecc_error->reg);
  2621. val &= ecc_error->msk;
  2622. val >>= ecc_error->shift;
  2623. dev_warn(dev, "%s found: mem addr is 0x%08X\n",
  2624. ecc_error->msg, val);
  2625. }
  2626. }
  2627. }
  2628. static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
  2629. u32 irq_value)
  2630. {
  2631. struct device *dev = hisi_hba->dev;
  2632. const struct hisi_sas_hw_error *ecc_error;
  2633. u32 val;
  2634. int i;
  2635. for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
  2636. ecc_error = &multi_bit_ecc_errors[i];
  2637. if (irq_value & ecc_error->irq_msk) {
  2638. val = hisi_sas_read32(hisi_hba, ecc_error->reg);
  2639. val &= ecc_error->msk;
  2640. val >>= ecc_error->shift;
  2641. dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
  2642. ecc_error->msg, irq_value, val);
  2643. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  2644. }
  2645. }
  2646. return;
  2647. }
  2648. static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
  2649. {
  2650. struct hisi_hba *hisi_hba = p;
  2651. u32 irq_value, irq_msk;
  2652. irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
  2653. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
  2654. irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
  2655. if (irq_value) {
  2656. one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
  2657. multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
  2658. }
  2659. hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
  2660. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
  2661. return IRQ_HANDLED;
  2662. }
  2663. static const struct hisi_sas_hw_error axi_error[] = {
  2664. { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
  2665. { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
  2666. { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
  2667. { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
  2668. { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
  2669. { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
  2670. { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
  2671. { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
  2672. {}
  2673. };
  2674. static const struct hisi_sas_hw_error fifo_error[] = {
  2675. { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
  2676. { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
  2677. { .msk = BIT(10), .msg = "GETDQE_FIFO" },
  2678. { .msk = BIT(11), .msg = "CMDP_FIFO" },
  2679. { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
  2680. {}
  2681. };
  2682. static const struct hisi_sas_hw_error fatal_axi_errors[] = {
  2683. {
  2684. .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
  2685. .msg = "write pointer and depth",
  2686. },
  2687. {
  2688. .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
  2689. .msg = "iptt no match slot",
  2690. },
  2691. {
  2692. .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
  2693. .msg = "read pointer and depth",
  2694. },
  2695. {
  2696. .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
  2697. .reg = HGC_AXI_FIFO_ERR_INFO,
  2698. .sub = axi_error,
  2699. },
  2700. {
  2701. .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
  2702. .reg = HGC_AXI_FIFO_ERR_INFO,
  2703. .sub = fifo_error,
  2704. },
  2705. {
  2706. .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
  2707. .msg = "LM add/fetch list",
  2708. },
  2709. {
  2710. .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
  2711. .msg = "SAS_HGC_ABT fetch LM list",
  2712. },
  2713. };
  2714. static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
  2715. {
  2716. struct hisi_hba *hisi_hba = p;
  2717. u32 irq_value, irq_msk, err_value;
  2718. struct device *dev = hisi_hba->dev;
  2719. const struct hisi_sas_hw_error *axi_error;
  2720. int i;
  2721. irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
  2722. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
  2723. irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
  2724. for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
  2725. axi_error = &fatal_axi_errors[i];
  2726. if (!(irq_value & axi_error->irq_msk))
  2727. continue;
  2728. hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
  2729. 1 << axi_error->shift);
  2730. if (axi_error->sub) {
  2731. const struct hisi_sas_hw_error *sub = axi_error->sub;
  2732. err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
  2733. for (; sub->msk || sub->msg; sub++) {
  2734. if (!(err_value & sub->msk))
  2735. continue;
  2736. dev_err(dev, "%s (0x%x) found!\n",
  2737. sub->msg, irq_value);
  2738. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  2739. }
  2740. } else {
  2741. dev_err(dev, "%s (0x%x) found!\n",
  2742. axi_error->msg, irq_value);
  2743. queue_work(hisi_hba->wq, &hisi_hba->rst_work);
  2744. }
  2745. }
  2746. if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
  2747. u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
  2748. u32 dev_id = reg_val & ITCT_DEV_MSK;
  2749. struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
  2750. hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
  2751. dev_dbg(dev, "clear ITCT ok\n");
  2752. complete(sas_dev->completion);
  2753. }
  2754. hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
  2755. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
  2756. return IRQ_HANDLED;
  2757. }
  2758. static irqreturn_t cq_thread_v2_hw(int irq_no, void *p)
  2759. {
  2760. struct hisi_sas_cq *cq = p;
  2761. struct hisi_hba *hisi_hba = cq->hisi_hba;
  2762. struct hisi_sas_slot *slot;
  2763. struct hisi_sas_itct *itct;
  2764. struct hisi_sas_complete_v2_hdr *complete_queue;
  2765. u32 rd_point = cq->rd_point, wr_point, dev_id;
  2766. int queue = cq->id;
  2767. if (unlikely(hisi_hba->reject_stp_links_msk))
  2768. phys_try_accept_stp_links_v2_hw(hisi_hba);
  2769. complete_queue = hisi_hba->complete_hdr[queue];
  2770. wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
  2771. (0x14 * queue));
  2772. while (rd_point != wr_point) {
  2773. struct hisi_sas_complete_v2_hdr *complete_hdr;
  2774. int iptt;
  2775. complete_hdr = &complete_queue[rd_point];
  2776. /* Check for NCQ completion */
  2777. if (complete_hdr->act) {
  2778. u32 act_tmp = le32_to_cpu(complete_hdr->act);
  2779. int ncq_tag_count = ffs(act_tmp);
  2780. u32 dw1 = le32_to_cpu(complete_hdr->dw1);
  2781. dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
  2782. CMPLT_HDR_DEV_ID_OFF;
  2783. itct = &hisi_hba->itct[dev_id];
  2784. /* The NCQ tags are held in the itct header */
  2785. while (ncq_tag_count) {
  2786. __le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
  2787. u64 ncq_tag;
  2788. ncq_tag_count--;
  2789. __ncq_tag = _ncq_tag[ncq_tag_count / 5];
  2790. ncq_tag = le64_to_cpu(__ncq_tag);
  2791. iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
  2792. 0xfff;
  2793. slot = &hisi_hba->slot_info[iptt];
  2794. slot->cmplt_queue_slot = rd_point;
  2795. slot->cmplt_queue = queue;
  2796. slot_complete_v2_hw(hisi_hba, slot);
  2797. act_tmp &= ~(1 << ncq_tag_count);
  2798. ncq_tag_count = ffs(act_tmp);
  2799. }
  2800. } else {
  2801. u32 dw1 = le32_to_cpu(complete_hdr->dw1);
  2802. iptt = dw1 & CMPLT_HDR_IPTT_MSK;
  2803. slot = &hisi_hba->slot_info[iptt];
  2804. slot->cmplt_queue_slot = rd_point;
  2805. slot->cmplt_queue = queue;
  2806. slot_complete_v2_hw(hisi_hba, slot);
  2807. }
  2808. if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
  2809. rd_point = 0;
  2810. }
  2811. /* update rd_point */
  2812. cq->rd_point = rd_point;
  2813. hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
  2814. return IRQ_HANDLED;
  2815. }
  2816. static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
  2817. {
  2818. struct hisi_sas_cq *cq = p;
  2819. struct hisi_hba *hisi_hba = cq->hisi_hba;
  2820. int queue = cq->id;
  2821. hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
  2822. return IRQ_WAKE_THREAD;
  2823. }
  2824. static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
  2825. {
  2826. struct hisi_sas_phy *phy = p;
  2827. struct hisi_hba *hisi_hba = phy->hisi_hba;
  2828. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  2829. struct device *dev = hisi_hba->dev;
  2830. struct hisi_sas_initial_fis *initial_fis;
  2831. struct dev_to_host_fis *fis;
  2832. u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
  2833. irqreturn_t res = IRQ_HANDLED;
  2834. u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
  2835. unsigned long flags;
  2836. int phy_no, offset;
  2837. del_timer(&phy->timer);
  2838. phy_no = sas_phy->id;
  2839. initial_fis = &hisi_hba->initial_fis[phy_no];
  2840. fis = &initial_fis->fis;
  2841. offset = 4 * (phy_no / 4);
  2842. ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
  2843. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
  2844. ent_msk | 1 << ((phy_no % 4) * 8));
  2845. ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
  2846. ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
  2847. (phy_no % 4)));
  2848. ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
  2849. if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
  2850. dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
  2851. res = IRQ_NONE;
  2852. goto end;
  2853. }
  2854. /* check ERR bit of Status Register */
  2855. if (fis->status & ATA_ERR) {
  2856. dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
  2857. fis->status);
  2858. hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
  2859. res = IRQ_NONE;
  2860. goto end;
  2861. }
  2862. if (unlikely(phy_no == 8)) {
  2863. u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
  2864. port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
  2865. PORT_STATE_PHY8_PORT_NUM_OFF;
  2866. link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
  2867. PORT_STATE_PHY8_CONN_RATE_OFF;
  2868. } else {
  2869. port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
  2870. port_id = (port_id >> (4 * phy_no)) & 0xf;
  2871. link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
  2872. link_rate = (link_rate >> (phy_no * 4)) & 0xf;
  2873. }
  2874. if (port_id == 0xf) {
  2875. dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
  2876. res = IRQ_NONE;
  2877. goto end;
  2878. }
  2879. sas_phy->linkrate = link_rate;
  2880. hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
  2881. HARD_PHY_LINKRATE);
  2882. phy->maximum_linkrate = hard_phy_linkrate & 0xf;
  2883. phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
  2884. sas_phy->oob_mode = SATA_OOB_MODE;
  2885. /* Make up some unique SAS address */
  2886. attached_sas_addr[0] = 0x50;
  2887. attached_sas_addr[6] = hisi_hba->shost->host_no;
  2888. attached_sas_addr[7] = phy_no;
  2889. memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
  2890. memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
  2891. dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
  2892. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  2893. phy->port_id = port_id;
  2894. phy->phy_type |= PORT_TYPE_SATA;
  2895. phy->phy_attached = 1;
  2896. phy->identify.device_type = SAS_SATA_DEV;
  2897. phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
  2898. phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
  2899. hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
  2900. spin_lock_irqsave(&phy->lock, flags);
  2901. if (phy->reset_completion) {
  2902. phy->in_reset = 0;
  2903. complete(phy->reset_completion);
  2904. }
  2905. spin_unlock_irqrestore(&phy->lock, flags);
  2906. end:
  2907. hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
  2908. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
  2909. return res;
  2910. }
  2911. static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
  2912. int_phy_updown_v2_hw,
  2913. int_chnl_int_v2_hw,
  2914. };
  2915. static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
  2916. fatal_ecc_int_v2_hw,
  2917. fatal_axi_int_v2_hw
  2918. };
  2919. /*
  2920. * There is a limitation in the hip06 chipset that we need
  2921. * to map in all mbigen interrupts, even if they are not used.
  2922. */
  2923. static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
  2924. {
  2925. struct platform_device *pdev = hisi_hba->platform_dev;
  2926. struct device *dev = &pdev->dev;
  2927. int irq, rc = 0, irq_map[128];
  2928. int i, phy_no, fatal_no, queue_no;
  2929. for (i = 0; i < 128; i++)
  2930. irq_map[i] = platform_get_irq(pdev, i);
  2931. for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
  2932. irq = irq_map[i + 1]; /* Phy up/down is irq1 */
  2933. rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
  2934. DRV_NAME " phy", hisi_hba);
  2935. if (rc) {
  2936. dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
  2937. irq, rc);
  2938. rc = -ENOENT;
  2939. goto err_out;
  2940. }
  2941. }
  2942. for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
  2943. struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
  2944. irq = irq_map[phy_no + 72];
  2945. rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
  2946. DRV_NAME " sata", phy);
  2947. if (rc) {
  2948. dev_err(dev, "irq init: could not request sata interrupt %d, rc=%d\n",
  2949. irq, rc);
  2950. rc = -ENOENT;
  2951. goto err_out;
  2952. }
  2953. }
  2954. for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
  2955. irq = irq_map[fatal_no + 81];
  2956. rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
  2957. DRV_NAME " fatal", hisi_hba);
  2958. if (rc) {
  2959. dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
  2960. irq, rc);
  2961. rc = -ENOENT;
  2962. goto err_out;
  2963. }
  2964. }
  2965. for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
  2966. struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
  2967. cq->irq_no = irq_map[queue_no + 96];
  2968. rc = devm_request_threaded_irq(dev, cq->irq_no,
  2969. cq_interrupt_v2_hw,
  2970. cq_thread_v2_hw, IRQF_ONESHOT,
  2971. DRV_NAME " cq", cq);
  2972. if (rc) {
  2973. dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
  2974. irq, rc);
  2975. rc = -ENOENT;
  2976. goto err_out;
  2977. }
  2978. }
  2979. hisi_hba->cq_nvecs = hisi_hba->queue_count;
  2980. err_out:
  2981. return rc;
  2982. }
  2983. static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
  2984. {
  2985. int rc;
  2986. memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
  2987. rc = hw_init_v2_hw(hisi_hba);
  2988. if (rc)
  2989. return rc;
  2990. rc = interrupt_init_v2_hw(hisi_hba);
  2991. if (rc)
  2992. return rc;
  2993. return 0;
  2994. }
  2995. static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
  2996. {
  2997. struct platform_device *pdev = hisi_hba->platform_dev;
  2998. int i;
  2999. for (i = 0; i < hisi_hba->queue_count; i++)
  3000. hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
  3001. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
  3002. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
  3003. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
  3004. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
  3005. for (i = 0; i < hisi_hba->n_phy; i++) {
  3006. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
  3007. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
  3008. }
  3009. for (i = 0; i < 128; i++)
  3010. synchronize_irq(platform_get_irq(pdev, i));
  3011. }
  3012. static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
  3013. {
  3014. return hisi_sas_read32(hisi_hba, PHY_STATE);
  3015. }
  3016. static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
  3017. {
  3018. struct device *dev = hisi_hba->dev;
  3019. int rc, cnt;
  3020. interrupt_disable_v2_hw(hisi_hba);
  3021. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
  3022. hisi_sas_stop_phys(hisi_hba);
  3023. mdelay(10);
  3024. hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
  3025. /* wait until bus idle */
  3026. cnt = 0;
  3027. while (1) {
  3028. u32 status = hisi_sas_read32_relaxed(hisi_hba,
  3029. AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
  3030. if (status == 0x3)
  3031. break;
  3032. udelay(10);
  3033. if (cnt++ > 10) {
  3034. dev_err(dev, "wait axi bus state to idle timeout!\n");
  3035. return -1;
  3036. }
  3037. }
  3038. hisi_sas_init_mem(hisi_hba);
  3039. rc = hw_init_v2_hw(hisi_hba);
  3040. if (rc)
  3041. return rc;
  3042. phys_reject_stp_links_v2_hw(hisi_hba);
  3043. return 0;
  3044. }
  3045. static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
  3046. u8 reg_index, u8 reg_count, u8 *write_data)
  3047. {
  3048. struct device *dev = hisi_hba->dev;
  3049. int phy_no, count;
  3050. if (!hisi_hba->sgpio_regs)
  3051. return -EOPNOTSUPP;
  3052. switch (reg_type) {
  3053. case SAS_GPIO_REG_TX:
  3054. count = reg_count * 4;
  3055. count = min(count, hisi_hba->n_phy);
  3056. for (phy_no = 0; phy_no < count; phy_no++) {
  3057. /*
  3058. * GPIO_TX[n] register has the highest numbered drive
  3059. * of the four in the first byte and the lowest
  3060. * numbered drive in the fourth byte.
  3061. * See SFF-8485 Rev. 0.7 Table 24.
  3062. */
  3063. void __iomem *reg_addr = hisi_hba->sgpio_regs +
  3064. reg_index * 4 + phy_no;
  3065. int data_idx = phy_no + 3 - (phy_no % 4) * 2;
  3066. writeb(write_data[data_idx], reg_addr);
  3067. }
  3068. break;
  3069. default:
  3070. dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
  3071. reg_type);
  3072. return -EINVAL;
  3073. }
  3074. return 0;
  3075. }
  3076. static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
  3077. int delay_ms, int timeout_ms)
  3078. {
  3079. struct device *dev = hisi_hba->dev;
  3080. int entries, entries_old = 0, time;
  3081. for (time = 0; time < timeout_ms; time += delay_ms) {
  3082. entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
  3083. if (entries == entries_old)
  3084. break;
  3085. entries_old = entries;
  3086. msleep(delay_ms);
  3087. }
  3088. if (time >= timeout_ms) {
  3089. dev_dbg(dev, "Wait commands complete timeout!\n");
  3090. return;
  3091. }
  3092. dev_dbg(dev, "wait commands complete %dms\n", time);
  3093. }
  3094. static struct device_attribute *host_attrs_v2_hw[] = {
  3095. &dev_attr_phy_event_threshold,
  3096. NULL
  3097. };
  3098. static struct scsi_host_template sht_v2_hw = {
  3099. .name = DRV_NAME,
  3100. .proc_name = DRV_NAME,
  3101. .module = THIS_MODULE,
  3102. .queuecommand = sas_queuecommand,
  3103. .dma_need_drain = ata_scsi_dma_need_drain,
  3104. .target_alloc = sas_target_alloc,
  3105. .slave_configure = hisi_sas_slave_configure,
  3106. .scan_finished = hisi_sas_scan_finished,
  3107. .scan_start = hisi_sas_scan_start,
  3108. .change_queue_depth = sas_change_queue_depth,
  3109. .bios_param = sas_bios_param,
  3110. .this_id = -1,
  3111. .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
  3112. .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
  3113. .eh_device_reset_handler = sas_eh_device_reset_handler,
  3114. .eh_target_reset_handler = sas_eh_target_reset_handler,
  3115. .slave_alloc = sas_slave_alloc,
  3116. .target_destroy = sas_target_destroy,
  3117. .ioctl = sas_ioctl,
  3118. #ifdef CONFIG_COMPAT
  3119. .compat_ioctl = sas_ioctl,
  3120. #endif
  3121. .shost_attrs = host_attrs_v2_hw,
  3122. .host_reset = hisi_sas_host_reset,
  3123. };
  3124. static const struct hisi_sas_hw hisi_sas_v2_hw = {
  3125. .hw_init = hisi_sas_v2_init,
  3126. .setup_itct = setup_itct_v2_hw,
  3127. .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
  3128. .alloc_dev = alloc_dev_quirk_v2_hw,
  3129. .sl_notify_ssp = sl_notify_ssp_v2_hw,
  3130. .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
  3131. .clear_itct = clear_itct_v2_hw,
  3132. .free_device = free_device_v2_hw,
  3133. .prep_smp = prep_smp_v2_hw,
  3134. .prep_ssp = prep_ssp_v2_hw,
  3135. .prep_stp = prep_ata_v2_hw,
  3136. .prep_abort = prep_abort_v2_hw,
  3137. .start_delivery = start_delivery_v2_hw,
  3138. .phys_init = phys_init_v2_hw,
  3139. .phy_start = start_phy_v2_hw,
  3140. .phy_disable = disable_phy_v2_hw,
  3141. .phy_hard_reset = phy_hard_reset_v2_hw,
  3142. .get_events = phy_get_events_v2_hw,
  3143. .phy_set_linkrate = phy_set_linkrate_v2_hw,
  3144. .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
  3145. .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
  3146. .soft_reset = soft_reset_v2_hw,
  3147. .get_phys_state = get_phys_state_v2_hw,
  3148. .write_gpio = write_gpio_v2_hw,
  3149. .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
  3150. .sht = &sht_v2_hw,
  3151. };
  3152. static int hisi_sas_v2_probe(struct platform_device *pdev)
  3153. {
  3154. /*
  3155. * Check if we should defer the probe before we probe the
  3156. * upper layer, as it's hard to defer later on.
  3157. */
  3158. int ret = platform_get_irq(pdev, 0);
  3159. if (ret < 0) {
  3160. if (ret != -EPROBE_DEFER)
  3161. dev_err(&pdev->dev, "cannot obtain irq\n");
  3162. return ret;
  3163. }
  3164. return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
  3165. }
  3166. static int hisi_sas_v2_remove(struct platform_device *pdev)
  3167. {
  3168. return hisi_sas_remove(pdev);
  3169. }
  3170. static const struct of_device_id sas_v2_of_match[] = {
  3171. { .compatible = "hisilicon,hip06-sas-v2",},
  3172. { .compatible = "hisilicon,hip07-sas-v2",},
  3173. {},
  3174. };
  3175. MODULE_DEVICE_TABLE(of, sas_v2_of_match);
  3176. static const struct acpi_device_id sas_v2_acpi_match[] = {
  3177. { "HISI0162", 0 },
  3178. { }
  3179. };
  3180. MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
  3181. static struct platform_driver hisi_sas_v2_driver = {
  3182. .probe = hisi_sas_v2_probe,
  3183. .remove = hisi_sas_v2_remove,
  3184. .driver = {
  3185. .name = DRV_NAME,
  3186. .of_match_table = sas_v2_of_match,
  3187. .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
  3188. },
  3189. };
  3190. module_platform_driver(hisi_sas_v2_driver);
  3191. MODULE_LICENSE("GPL");
  3192. MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
  3193. MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
  3194. MODULE_ALIAS("platform:" DRV_NAME);