hisi_sas_v1_hw.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2015 Linaro Ltd.
  4. * Copyright (c) 2015 Hisilicon Limited.
  5. */
  6. #include "hisi_sas.h"
  7. #define DRV_NAME "hisi_sas_v1_hw"
  8. /* global registers need init*/
  9. #define DLVRY_QUEUE_ENABLE 0x0
  10. #define IOST_BASE_ADDR_LO 0x8
  11. #define IOST_BASE_ADDR_HI 0xc
  12. #define ITCT_BASE_ADDR_LO 0x10
  13. #define ITCT_BASE_ADDR_HI 0x14
  14. #define BROKEN_MSG_ADDR_LO 0x18
  15. #define BROKEN_MSG_ADDR_HI 0x1c
  16. #define PHY_CONTEXT 0x20
  17. #define PHY_STATE 0x24
  18. #define PHY_PORT_NUM_MA 0x28
  19. #define PORT_STATE 0x2c
  20. #define PHY_CONN_RATE 0x30
  21. #define HGC_TRANS_TASK_CNT_LIMIT 0x38
  22. #define AXI_AHB_CLK_CFG 0x3c
  23. #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84
  24. #define HGC_GET_ITV_TIME 0x90
  25. #define DEVICE_MSG_WORK_MODE 0x94
  26. #define I_T_NEXUS_LOSS_TIME 0xa0
  27. #define BUS_INACTIVE_LIMIT_TIME 0xa8
  28. #define REJECT_TO_OPEN_LIMIT_TIME 0xac
  29. #define CFG_AGING_TIME 0xbc
  30. #define CFG_AGING_TIME_ITCT_REL_OFF 0
  31. #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
  32. #define HGC_DFX_CFG2 0xc0
  33. #define FIS_LIST_BADDR_L 0xc4
  34. #define CFG_1US_TIMER_TRSH 0xcc
  35. #define CFG_SAS_CONFIG 0xd4
  36. #define HGC_IOST_ECC_ADDR 0x140
  37. #define HGC_IOST_ECC_ADDR_BAD_OFF 16
  38. #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
  39. #define HGC_DQ_ECC_ADDR 0x144
  40. #define HGC_DQ_ECC_ADDR_BAD_OFF 16
  41. #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
  42. #define HGC_INVLD_DQE_INFO 0x148
  43. #define HGC_INVLD_DQE_INFO_DQ_OFF 0
  44. #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
  45. #define HGC_INVLD_DQE_INFO_TYPE_OFF 16
  46. #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
  47. #define HGC_INVLD_DQE_INFO_FORCE_OFF 17
  48. #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
  49. #define HGC_INVLD_DQE_INFO_PHY_OFF 18
  50. #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
  51. #define HGC_INVLD_DQE_INFO_ABORT_OFF 19
  52. #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
  53. #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20
  54. #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
  55. #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21
  56. #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
  57. #define HGC_INVLD_DQE_INFO_OFL_OFF 22
  58. #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
  59. #define HGC_ITCT_ECC_ADDR 0x150
  60. #define HGC_ITCT_ECC_ADDR_BAD_OFF 16
  61. #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
  62. #define HGC_AXI_FIFO_ERR_INFO 0x154
  63. #define INT_COAL_EN 0x1bc
  64. #define OQ_INT_COAL_TIME 0x1c0
  65. #define OQ_INT_COAL_CNT 0x1c4
  66. #define ENT_INT_COAL_TIME 0x1c8
  67. #define ENT_INT_COAL_CNT 0x1cc
  68. #define OQ_INT_SRC 0x1d0
  69. #define OQ_INT_SRC_MSK 0x1d4
  70. #define ENT_INT_SRC1 0x1d8
  71. #define ENT_INT_SRC2 0x1dc
  72. #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25
  73. #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
  74. #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27
  75. #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
  76. #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28
  77. #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
  78. #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
  79. #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
  80. #define ENT_INT_SRC_MSK1 0x1e0
  81. #define ENT_INT_SRC_MSK2 0x1e4
  82. #define SAS_ECC_INTR 0x1e8
  83. #define SAS_ECC_INTR_DQ_ECC1B_OFF 0
  84. #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
  85. #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1
  86. #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
  87. #define SAS_ECC_INTR_IOST_ECC1B_OFF 2
  88. #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
  89. #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3
  90. #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
  91. #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4
  92. #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
  93. #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5
  94. #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
  95. #define SAS_ECC_INTR_MSK 0x1ec
  96. #define HGC_ERR_STAT_EN 0x238
  97. #define DLVRY_Q_0_BASE_ADDR_LO 0x260
  98. #define DLVRY_Q_0_BASE_ADDR_HI 0x264
  99. #define DLVRY_Q_0_DEPTH 0x268
  100. #define DLVRY_Q_0_WR_PTR 0x26c
  101. #define DLVRY_Q_0_RD_PTR 0x270
  102. #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
  103. #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
  104. #define COMPL_Q_0_DEPTH 0x4e8
  105. #define COMPL_Q_0_WR_PTR 0x4ec
  106. #define COMPL_Q_0_RD_PTR 0x4f0
  107. #define HGC_ECC_ERR 0x7d0
  108. /* phy registers need init */
  109. #define PORT_BASE (0x800)
  110. #define PHY_CFG (PORT_BASE + 0x0)
  111. #define PHY_CFG_ENA_OFF 0
  112. #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
  113. #define PHY_CFG_DC_OPT_OFF 2
  114. #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
  115. #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
  116. #define PROG_PHY_LINK_RATE_MAX_OFF 0
  117. #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
  118. #define PROG_PHY_LINK_RATE_MIN_OFF 4
  119. #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
  120. #define PROG_PHY_LINK_RATE_OOB_OFF 8
  121. #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
  122. #define PHY_CTRL (PORT_BASE + 0x14)
  123. #define PHY_CTRL_RESET_OFF 0
  124. #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
  125. #define PHY_RATE_NEGO (PORT_BASE + 0x30)
  126. #define PHY_PCN (PORT_BASE + 0x44)
  127. #define SL_TOUT_CFG (PORT_BASE + 0x8c)
  128. #define SL_CONTROL (PORT_BASE + 0x94)
  129. #define SL_CONTROL_NOTIFY_EN_OFF 0
  130. #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
  131. #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
  132. #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
  133. #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
  134. #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
  135. #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
  136. #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
  137. #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
  138. #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
  139. #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
  140. #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
  141. #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
  142. #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
  143. #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
  144. #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
  145. #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
  146. #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c)
  147. #define CON_CFG_DRIVER (PORT_BASE + 0x130)
  148. #define PHY_CONFIG2 (PORT_BASE + 0x1a8)
  149. #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3
  150. #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
  151. #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24
  152. #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
  153. #define CHL_INT0 (PORT_BASE + 0x1b0)
  154. #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0
  155. #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
  156. #define CHL_INT0_SN_FAIL_NGR_OFF 2
  157. #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
  158. #define CHL_INT0_DWS_LOST_OFF 4
  159. #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF)
  160. #define CHL_INT0_SL_IDAF_FAIL_OFF 10
  161. #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
  162. #define CHL_INT0_ID_TIMEOUT_OFF 11
  163. #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
  164. #define CHL_INT0_SL_OPAF_FAIL_OFF 12
  165. #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
  166. #define CHL_INT0_SL_PS_FAIL_OFF 21
  167. #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
  168. #define CHL_INT1 (PORT_BASE + 0x1b4)
  169. #define CHL_INT2 (PORT_BASE + 0x1b8)
  170. #define CHL_INT2_SL_RX_BC_ACK_OFF 2
  171. #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
  172. #define CHL_INT2_SL_PHY_ENA_OFF 6
  173. #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
  174. #define CHL_INT0_MSK (PORT_BASE + 0x1bc)
  175. #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
  176. #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
  177. #define CHL_INT1_MSK (PORT_BASE + 0x1c0)
  178. #define CHL_INT2_MSK (PORT_BASE + 0x1c4)
  179. #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
  180. #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
  181. #define DMA_TX_STATUS_BUSY_OFF 0
  182. #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
  183. #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
  184. #define DMA_RX_STATUS_BUSY_OFF 0
  185. #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
  186. #define AXI_CFG 0x5100
  187. #define RESET_VALUE 0x7ffff
  188. /* HW dma structures */
  189. /* Delivery queue header */
  190. /* dw0 */
  191. #define CMD_HDR_RESP_REPORT_OFF 5
  192. #define CMD_HDR_RESP_REPORT_MSK 0x20
  193. #define CMD_HDR_TLR_CTRL_OFF 6
  194. #define CMD_HDR_TLR_CTRL_MSK 0xc0
  195. #define CMD_HDR_PORT_OFF 17
  196. #define CMD_HDR_PORT_MSK 0xe0000
  197. #define CMD_HDR_PRIORITY_OFF 27
  198. #define CMD_HDR_PRIORITY_MSK 0x8000000
  199. #define CMD_HDR_MODE_OFF 28
  200. #define CMD_HDR_MODE_MSK 0x10000000
  201. #define CMD_HDR_CMD_OFF 29
  202. #define CMD_HDR_CMD_MSK 0xe0000000
  203. /* dw1 */
  204. #define CMD_HDR_VERIFY_DTL_OFF 10
  205. #define CMD_HDR_VERIFY_DTL_MSK 0x400
  206. #define CMD_HDR_SSP_FRAME_TYPE_OFF 13
  207. #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000
  208. #define CMD_HDR_DEVICE_ID_OFF 16
  209. #define CMD_HDR_DEVICE_ID_MSK 0xffff0000
  210. /* dw2 */
  211. #define CMD_HDR_CFL_OFF 0
  212. #define CMD_HDR_CFL_MSK 0x1ff
  213. #define CMD_HDR_MRFL_OFF 15
  214. #define CMD_HDR_MRFL_MSK 0xff8000
  215. #define CMD_HDR_FIRST_BURST_OFF 25
  216. #define CMD_HDR_FIRST_BURST_MSK 0x2000000
  217. /* dw3 */
  218. #define CMD_HDR_IPTT_OFF 0
  219. #define CMD_HDR_IPTT_MSK 0xffff
  220. /* dw6 */
  221. #define CMD_HDR_DATA_SGL_LEN_OFF 16
  222. #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000
  223. /* Completion header */
  224. #define CMPLT_HDR_IPTT_OFF 0
  225. #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
  226. #define CMPLT_HDR_CMD_CMPLT_OFF 17
  227. #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
  228. #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18
  229. #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
  230. #define CMPLT_HDR_RSPNS_XFRD_OFF 19
  231. #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
  232. #define CMPLT_HDR_IO_CFG_ERR_OFF 27
  233. #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
  234. /* ITCT header */
  235. /* qw0 */
  236. #define ITCT_HDR_DEV_TYPE_OFF 0
  237. #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF)
  238. #define ITCT_HDR_VALID_OFF 2
  239. #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF)
  240. #define ITCT_HDR_AWT_CONTROL_OFF 4
  241. #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)
  242. #define ITCT_HDR_MAX_CONN_RATE_OFF 5
  243. #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)
  244. #define ITCT_HDR_VALID_LINK_NUM_OFF 9
  245. #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)
  246. #define ITCT_HDR_PORT_ID_OFF 13
  247. #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF)
  248. #define ITCT_HDR_SMP_TIMEOUT_OFF 16
  249. #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)
  250. /* qw1 */
  251. #define ITCT_HDR_MAX_SAS_ADDR_OFF 0
  252. #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \
  253. ITCT_HDR_MAX_SAS_ADDR_OFF)
  254. /* qw2 */
  255. #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0
  256. #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \
  257. ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
  258. #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16
  259. #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \
  260. ITCT_HDR_BUS_INACTIVE_TL_OFF)
  261. #define ITCT_HDR_MAX_CONN_TL_OFF 32
  262. #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \
  263. ITCT_HDR_MAX_CONN_TL_OFF)
  264. #define ITCT_HDR_REJ_OPEN_TL_OFF 48
  265. #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \
  266. ITCT_HDR_REJ_OPEN_TL_OFF)
  267. /* Err record header */
  268. #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0
  269. #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
  270. #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16
  271. #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
  272. struct hisi_sas_complete_v1_hdr {
  273. __le32 data;
  274. };
  275. struct hisi_sas_err_record_v1 {
  276. /* dw0 */
  277. __le32 dma_err_type;
  278. /* dw1 */
  279. __le32 trans_tx_fail_type;
  280. /* dw2 */
  281. __le32 trans_rx_fail_type;
  282. /* dw3 */
  283. u32 rsvd;
  284. };
  285. enum {
  286. HISI_SAS_PHY_BCAST_ACK = 0,
  287. HISI_SAS_PHY_SL_PHY_ENABLED,
  288. HISI_SAS_PHY_INT_ABNORMAL,
  289. HISI_SAS_PHY_INT_NR
  290. };
  291. enum {
  292. DMA_TX_ERR_BASE = 0x0,
  293. DMA_RX_ERR_BASE = 0x100,
  294. TRANS_TX_FAIL_BASE = 0x200,
  295. TRANS_RX_FAIL_BASE = 0x300,
  296. /* dma tx */
  297. DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
  298. DMA_TX_DIF_APP_ERR, /* 0x1 */
  299. DMA_TX_DIF_RPP_ERR, /* 0x2 */
  300. DMA_TX_AXI_BUS_ERR, /* 0x3 */
  301. DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
  302. DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
  303. DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
  304. DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
  305. DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
  306. DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
  307. /* dma rx */
  308. DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
  309. DMA_RX_DIF_CRC_ERR, /* 0x101 */
  310. DMA_RX_DIF_APP_ERR, /* 0x102 */
  311. DMA_RX_DIF_RPP_ERR, /* 0x103 */
  312. DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
  313. DMA_RX_AXI_BUS_ERR, /* 0x105 */
  314. DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
  315. DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
  316. DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
  317. DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
  318. DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
  319. DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
  320. DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
  321. /* trans tx */
  322. TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
  323. TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
  324. TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
  325. TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
  326. TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
  327. TRANS_TX_RSVD1_ERR, /* 0x205 */
  328. TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
  329. TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
  330. TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
  331. TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
  332. TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
  333. TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
  334. TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
  335. TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
  336. TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
  337. TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
  338. TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
  339. TRANS_TX_RSVD2_ERR, /* 0x211 */
  340. TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
  341. TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
  342. TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
  343. TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
  344. TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
  345. TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
  346. TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
  347. TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
  348. TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
  349. TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
  350. TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
  351. TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
  352. TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
  353. TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
  354. /* trans rx */
  355. TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
  356. TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
  357. TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
  358. TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
  359. TRANS_RX_RSVD0_ERR, /* 0x304 */
  360. TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
  361. TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
  362. TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
  363. TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
  364. TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
  365. TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
  366. TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
  367. TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
  368. TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
  369. TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
  370. TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
  371. TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
  372. TRANS_RX_BAD_HASH_ERR, /* 0x311 */
  373. TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
  374. TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
  375. TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
  376. TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
  377. TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
  378. TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
  379. TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
  380. TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
  381. TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
  382. };
  383. #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
  384. #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
  385. #define HISI_SAS_FATAL_INT_NR (2)
  386. #define HISI_SAS_MAX_INT_NR \
  387. (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
  388. HISI_SAS_FATAL_INT_NR)
  389. static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
  390. {
  391. void __iomem *regs = hisi_hba->regs + off;
  392. return readl(regs);
  393. }
  394. static void hisi_sas_write32(struct hisi_hba *hisi_hba,
  395. u32 off, u32 val)
  396. {
  397. void __iomem *regs = hisi_hba->regs + off;
  398. writel(val, regs);
  399. }
  400. static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
  401. int phy_no, u32 off, u32 val)
  402. {
  403. void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
  404. writel(val, regs);
  405. }
  406. static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
  407. int phy_no, u32 off)
  408. {
  409. void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
  410. return readl(regs);
  411. }
  412. static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  413. {
  414. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  415. cfg &= ~PHY_CFG_DC_OPT_MSK;
  416. cfg |= 1 << PHY_CFG_DC_OPT_OFF;
  417. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  418. }
  419. static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  420. {
  421. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
  422. cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
  423. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
  424. }
  425. static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  426. {
  427. struct sas_identify_frame identify_frame;
  428. u32 *identify_buffer;
  429. memset(&identify_frame, 0, sizeof(identify_frame));
  430. identify_frame.dev_type = SAS_END_DEVICE;
  431. identify_frame.frame_type = 0;
  432. identify_frame._un1 = 1;
  433. identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
  434. identify_frame.target_bits = SAS_PROTOCOL_NONE;
  435. memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
  436. memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
  437. identify_frame.phy_id = phy_no;
  438. identify_buffer = (u32 *)(&identify_frame);
  439. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
  440. __swab32(identify_buffer[0]));
  441. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
  442. __swab32(identify_buffer[1]));
  443. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
  444. __swab32(identify_buffer[2]));
  445. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
  446. __swab32(identify_buffer[3]));
  447. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
  448. __swab32(identify_buffer[4]));
  449. hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
  450. __swab32(identify_buffer[5]));
  451. }
  452. static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
  453. struct hisi_sas_device *sas_dev)
  454. {
  455. struct domain_device *device = sas_dev->sas_device;
  456. struct device *dev = hisi_hba->dev;
  457. u64 qw0, device_id = sas_dev->device_id;
  458. struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
  459. struct asd_sas_port *sas_port = device->port;
  460. struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
  461. u64 sas_addr;
  462. memset(itct, 0, sizeof(*itct));
  463. /* qw0 */
  464. qw0 = 0;
  465. switch (sas_dev->dev_type) {
  466. case SAS_END_DEVICE:
  467. case SAS_EDGE_EXPANDER_DEVICE:
  468. case SAS_FANOUT_EXPANDER_DEVICE:
  469. qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
  470. break;
  471. default:
  472. dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
  473. sas_dev->dev_type);
  474. }
  475. qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
  476. (1 << ITCT_HDR_AWT_CONTROL_OFF) |
  477. (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
  478. (1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
  479. (port->id << ITCT_HDR_PORT_ID_OFF));
  480. itct->qw0 = cpu_to_le64(qw0);
  481. /* qw1 */
  482. memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
  483. itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
  484. /* qw2 */
  485. itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
  486. (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) |
  487. (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) |
  488. (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
  489. }
  490. static int clear_itct_v1_hw(struct hisi_hba *hisi_hba,
  491. struct hisi_sas_device *sas_dev)
  492. {
  493. u64 dev_id = sas_dev->device_id;
  494. struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
  495. u64 qw0;
  496. u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
  497. reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
  498. hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
  499. /* free itct */
  500. udelay(1);
  501. reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
  502. reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
  503. hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
  504. qw0 = le64_to_cpu(itct->qw0);
  505. qw0 &= ~ITCT_HDR_VALID_MSK;
  506. itct->qw0 = cpu_to_le64(qw0);
  507. return 0;
  508. }
  509. static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
  510. {
  511. int i;
  512. unsigned long end_time;
  513. u32 val;
  514. struct device *dev = hisi_hba->dev;
  515. for (i = 0; i < hisi_hba->n_phy; i++) {
  516. u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
  517. phy_ctrl |= PHY_CTRL_RESET_MSK;
  518. hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
  519. }
  520. msleep(1); /* It is safe to wait for 50us */
  521. /* Ensure DMA tx & rx idle */
  522. for (i = 0; i < hisi_hba->n_phy; i++) {
  523. u32 dma_tx_status, dma_rx_status;
  524. end_time = jiffies + msecs_to_jiffies(1000);
  525. while (1) {
  526. dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
  527. DMA_TX_STATUS);
  528. dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
  529. DMA_RX_STATUS);
  530. if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
  531. !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
  532. break;
  533. msleep(20);
  534. if (time_after(jiffies, end_time))
  535. return -EIO;
  536. }
  537. }
  538. /* Ensure axi bus idle */
  539. end_time = jiffies + msecs_to_jiffies(1000);
  540. while (1) {
  541. u32 axi_status =
  542. hisi_sas_read32(hisi_hba, AXI_CFG);
  543. if (axi_status == 0)
  544. break;
  545. msleep(20);
  546. if (time_after(jiffies, end_time))
  547. return -EIO;
  548. }
  549. if (ACPI_HANDLE(dev)) {
  550. acpi_status s;
  551. s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
  552. if (ACPI_FAILURE(s)) {
  553. dev_err(dev, "Reset failed\n");
  554. return -EIO;
  555. }
  556. } else if (hisi_hba->ctrl) {
  557. /* Apply reset and disable clock */
  558. /* clk disable reg is offset by +4 bytes from clk enable reg */
  559. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
  560. RESET_VALUE);
  561. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
  562. RESET_VALUE);
  563. msleep(1);
  564. regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
  565. if (RESET_VALUE != (val & RESET_VALUE)) {
  566. dev_err(dev, "Reset failed\n");
  567. return -EIO;
  568. }
  569. /* De-reset and enable clock */
  570. /* deassert rst reg is offset by +4 bytes from assert reg */
  571. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
  572. RESET_VALUE);
  573. regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
  574. RESET_VALUE);
  575. msleep(1);
  576. regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
  577. if (val & RESET_VALUE) {
  578. dev_err(dev, "De-reset failed\n");
  579. return -EIO;
  580. }
  581. } else {
  582. dev_warn(dev, "no reset method\n");
  583. return -EINVAL;
  584. }
  585. return 0;
  586. }
  587. static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
  588. {
  589. int i;
  590. /* Global registers init*/
  591. hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
  592. (u32)((1ULL << hisi_hba->queue_count) - 1));
  593. hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
  594. hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
  595. hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
  596. hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
  597. hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
  598. hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
  599. hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
  600. hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
  601. hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
  602. hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
  603. hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
  604. hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
  605. hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
  606. hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
  607. hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
  608. hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
  609. hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
  610. hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
  611. hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
  612. hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
  613. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
  614. hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
  615. hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
  616. hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
  617. hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
  618. hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
  619. for (i = 0; i < hisi_hba->n_phy; i++) {
  620. hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
  621. hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
  622. hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
  623. hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
  624. hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
  625. hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
  626. hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
  627. hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
  628. hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
  629. hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
  630. hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
  631. }
  632. for (i = 0; i < hisi_hba->queue_count; i++) {
  633. /* Delivery queue */
  634. hisi_sas_write32(hisi_hba,
  635. DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
  636. upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
  637. hisi_sas_write32(hisi_hba,
  638. DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
  639. lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
  640. hisi_sas_write32(hisi_hba,
  641. DLVRY_Q_0_DEPTH + (i * 0x14),
  642. HISI_SAS_QUEUE_SLOTS);
  643. /* Completion queue */
  644. hisi_sas_write32(hisi_hba,
  645. COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
  646. upper_32_bits(hisi_hba->complete_hdr_dma[i]));
  647. hisi_sas_write32(hisi_hba,
  648. COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
  649. lower_32_bits(hisi_hba->complete_hdr_dma[i]));
  650. hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
  651. HISI_SAS_QUEUE_SLOTS);
  652. }
  653. /* itct */
  654. hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
  655. lower_32_bits(hisi_hba->itct_dma));
  656. hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
  657. upper_32_bits(hisi_hba->itct_dma));
  658. /* iost */
  659. hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
  660. lower_32_bits(hisi_hba->iost_dma));
  661. hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
  662. upper_32_bits(hisi_hba->iost_dma));
  663. /* breakpoint */
  664. hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
  665. lower_32_bits(hisi_hba->breakpoint_dma));
  666. hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
  667. upper_32_bits(hisi_hba->breakpoint_dma));
  668. }
  669. static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
  670. {
  671. struct device *dev = hisi_hba->dev;
  672. int rc;
  673. rc = reset_hw_v1_hw(hisi_hba);
  674. if (rc) {
  675. dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
  676. return rc;
  677. }
  678. msleep(100);
  679. init_reg_v1_hw(hisi_hba);
  680. return 0;
  681. }
  682. static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  683. {
  684. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  685. cfg |= PHY_CFG_ENA_MSK;
  686. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  687. }
  688. static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  689. {
  690. u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
  691. cfg &= ~PHY_CFG_ENA_MSK;
  692. hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
  693. }
  694. static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  695. {
  696. config_id_frame_v1_hw(hisi_hba, phy_no);
  697. config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
  698. config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
  699. enable_phy_v1_hw(hisi_hba, phy_no);
  700. }
  701. static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  702. {
  703. hisi_sas_phy_enable(hisi_hba, phy_no, 0);
  704. msleep(100);
  705. hisi_sas_phy_enable(hisi_hba, phy_no, 1);
  706. }
  707. static void start_phys_v1_hw(struct timer_list *t)
  708. {
  709. struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
  710. int i;
  711. for (i = 0; i < hisi_hba->n_phy; i++) {
  712. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
  713. hisi_sas_phy_enable(hisi_hba, i, 1);
  714. }
  715. }
  716. static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
  717. {
  718. int i;
  719. struct timer_list *timer = &hisi_hba->timer;
  720. for (i = 0; i < hisi_hba->n_phy; i++) {
  721. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
  722. hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
  723. }
  724. timer_setup(timer, start_phys_v1_hw, 0);
  725. mod_timer(timer, jiffies + HZ);
  726. }
  727. static void sl_notify_ssp_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
  728. {
  729. u32 sl_control;
  730. sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  731. sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
  732. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
  733. msleep(1);
  734. sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
  735. sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
  736. hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
  737. }
  738. static enum sas_linkrate phy_get_max_linkrate_v1_hw(void)
  739. {
  740. return SAS_LINK_RATE_6_0_GBPS;
  741. }
  742. static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no,
  743. struct sas_phy_linkrates *r)
  744. {
  745. enum sas_linkrate max = r->maximum_linkrate;
  746. u32 prog_phy_link_rate = 0x800;
  747. prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
  748. hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
  749. prog_phy_link_rate);
  750. }
  751. static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
  752. {
  753. int i, bitmap = 0;
  754. u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
  755. for (i = 0; i < hisi_hba->n_phy; i++)
  756. if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
  757. bitmap |= 1 << i;
  758. return bitmap;
  759. }
  760. /* DQ lock must be taken here */
  761. static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
  762. {
  763. struct hisi_hba *hisi_hba = dq->hisi_hba;
  764. struct hisi_sas_slot *s, *s1, *s2 = NULL;
  765. int dlvry_queue = dq->id;
  766. int wp;
  767. list_for_each_entry_safe(s, s1, &dq->list, delivery) {
  768. if (!s->ready)
  769. break;
  770. s2 = s;
  771. list_del(&s->delivery);
  772. }
  773. if (!s2)
  774. return;
  775. /*
  776. * Ensure that memories for slots built on other CPUs is observed.
  777. */
  778. smp_rmb();
  779. wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
  780. hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
  781. }
  782. static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
  783. struct hisi_sas_slot *slot,
  784. struct hisi_sas_cmd_hdr *hdr,
  785. struct scatterlist *scatter,
  786. int n_elem)
  787. {
  788. struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
  789. struct scatterlist *sg;
  790. int i;
  791. for_each_sg(scatter, sg, n_elem, i) {
  792. struct hisi_sas_sge *entry = &sge_page->sge[i];
  793. entry->addr = cpu_to_le64(sg_dma_address(sg));
  794. entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
  795. entry->data_len = cpu_to_le32(sg_dma_len(sg));
  796. entry->data_off = 0;
  797. }
  798. hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
  799. hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
  800. }
  801. static void prep_smp_v1_hw(struct hisi_hba *hisi_hba,
  802. struct hisi_sas_slot *slot)
  803. {
  804. struct sas_task *task = slot->task;
  805. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  806. struct domain_device *device = task->dev;
  807. struct hisi_sas_port *port = slot->port;
  808. struct scatterlist *sg_req;
  809. struct hisi_sas_device *sas_dev = device->lldd_dev;
  810. dma_addr_t req_dma_addr;
  811. unsigned int req_len;
  812. /* req */
  813. sg_req = &task->smp_task.smp_req;
  814. req_len = sg_dma_len(sg_req);
  815. req_dma_addr = sg_dma_address(sg_req);
  816. /* create header */
  817. /* dw0 */
  818. hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
  819. (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
  820. (1 << CMD_HDR_MODE_OFF) | /* ini mode */
  821. (2 << CMD_HDR_CMD_OFF)); /* smp */
  822. /* map itct entry */
  823. hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
  824. /* dw2 */
  825. hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
  826. (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
  827. CMD_HDR_MRFL_OFF));
  828. hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
  829. hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
  830. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  831. }
  832. static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
  833. struct hisi_sas_slot *slot)
  834. {
  835. struct sas_task *task = slot->task;
  836. struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
  837. struct domain_device *device = task->dev;
  838. struct hisi_sas_device *sas_dev = device->lldd_dev;
  839. struct hisi_sas_port *port = slot->port;
  840. struct sas_ssp_task *ssp_task = &task->ssp_task;
  841. struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
  842. struct hisi_sas_tmf_task *tmf = slot->tmf;
  843. int has_data = 0, priority = !!tmf;
  844. u8 *buf_cmd, fburst = 0;
  845. u32 dw1, dw2;
  846. /* create header */
  847. hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
  848. (0x2 << CMD_HDR_TLR_CTRL_OFF) |
  849. (port->id << CMD_HDR_PORT_OFF) |
  850. (priority << CMD_HDR_PRIORITY_OFF) |
  851. (1 << CMD_HDR_MODE_OFF) | /* ini mode */
  852. (1 << CMD_HDR_CMD_OFF)); /* ssp */
  853. dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
  854. if (tmf) {
  855. dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
  856. } else {
  857. switch (scsi_cmnd->sc_data_direction) {
  858. case DMA_TO_DEVICE:
  859. dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
  860. has_data = 1;
  861. break;
  862. case DMA_FROM_DEVICE:
  863. dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
  864. has_data = 1;
  865. break;
  866. default:
  867. dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
  868. }
  869. }
  870. /* map itct entry */
  871. dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
  872. hdr->dw1 = cpu_to_le32(dw1);
  873. if (tmf) {
  874. dw2 = ((sizeof(struct ssp_tmf_iu) +
  875. sizeof(struct ssp_frame_hdr)+3)/4) <<
  876. CMD_HDR_CFL_OFF;
  877. } else {
  878. dw2 = ((sizeof(struct ssp_command_iu) +
  879. sizeof(struct ssp_frame_hdr)+3)/4) <<
  880. CMD_HDR_CFL_OFF;
  881. }
  882. dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
  883. hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
  884. if (has_data)
  885. prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
  886. slot->n_elem);
  887. hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
  888. hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
  889. hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
  890. buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
  891. sizeof(struct ssp_frame_hdr);
  892. if (task->ssp_task.enable_first_burst) {
  893. fburst = (1 << 7);
  894. dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
  895. }
  896. hdr->dw2 = cpu_to_le32(dw2);
  897. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  898. if (!tmf) {
  899. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  900. (task->ssp_task.task_prio << 3);
  901. memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
  902. task->ssp_task.cmd->cmd_len);
  903. } else {
  904. buf_cmd[10] = tmf->tmf;
  905. switch (tmf->tmf) {
  906. case TMF_ABORT_TASK:
  907. case TMF_QUERY_TASK:
  908. buf_cmd[12] =
  909. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  910. buf_cmd[13] =
  911. tmf->tag_of_task_to_be_managed & 0xff;
  912. break;
  913. default:
  914. break;
  915. }
  916. }
  917. }
  918. /* by default, task resp is complete */
  919. static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
  920. struct sas_task *task,
  921. struct hisi_sas_slot *slot)
  922. {
  923. struct task_status_struct *ts = &task->task_status;
  924. struct hisi_sas_err_record_v1 *err_record =
  925. hisi_sas_status_buf_addr_mem(slot);
  926. struct device *dev = hisi_hba->dev;
  927. switch (task->task_proto) {
  928. case SAS_PROTOCOL_SSP:
  929. {
  930. int error = -1;
  931. u32 dma_err_type = le32_to_cpu(err_record->dma_err_type);
  932. u32 dma_tx_err_type = ((dma_err_type &
  933. ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
  934. ERR_HDR_DMA_TX_ERR_TYPE_OFF;
  935. u32 dma_rx_err_type = ((dma_err_type &
  936. ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
  937. ERR_HDR_DMA_RX_ERR_TYPE_OFF;
  938. u32 trans_tx_fail_type =
  939. le32_to_cpu(err_record->trans_tx_fail_type);
  940. u32 trans_rx_fail_type =
  941. le32_to_cpu(err_record->trans_rx_fail_type);
  942. if (dma_tx_err_type) {
  943. /* dma tx err */
  944. error = ffs(dma_tx_err_type)
  945. - 1 + DMA_TX_ERR_BASE;
  946. } else if (dma_rx_err_type) {
  947. /* dma rx err */
  948. error = ffs(dma_rx_err_type)
  949. - 1 + DMA_RX_ERR_BASE;
  950. } else if (trans_tx_fail_type) {
  951. /* trans tx err */
  952. error = ffs(trans_tx_fail_type)
  953. - 1 + TRANS_TX_FAIL_BASE;
  954. } else if (trans_rx_fail_type) {
  955. /* trans rx err */
  956. error = ffs(trans_rx_fail_type)
  957. - 1 + TRANS_RX_FAIL_BASE;
  958. }
  959. switch (error) {
  960. case DMA_TX_DATA_UNDERFLOW_ERR:
  961. case DMA_RX_DATA_UNDERFLOW_ERR:
  962. {
  963. ts->residual = 0;
  964. ts->stat = SAS_DATA_UNDERRUN;
  965. break;
  966. }
  967. case DMA_TX_DATA_SGL_OVERFLOW_ERR:
  968. case DMA_TX_DIF_SGL_OVERFLOW_ERR:
  969. case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
  970. case DMA_RX_DATA_OVERFLOW_ERR:
  971. case TRANS_RX_FRAME_OVERRUN_ERR:
  972. case TRANS_RX_LINK_BUF_OVERRUN_ERR:
  973. {
  974. ts->stat = SAS_DATA_OVERRUN;
  975. ts->residual = 0;
  976. break;
  977. }
  978. case TRANS_TX_PHY_NOT_ENABLE_ERR:
  979. {
  980. ts->stat = SAS_PHY_DOWN;
  981. break;
  982. }
  983. case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
  984. case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
  985. case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
  986. case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
  987. case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
  988. case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
  989. case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
  990. case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
  991. case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
  992. case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
  993. case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
  994. case TRANS_TX_OPEN_RETRY_ERR:
  995. {
  996. ts->stat = SAS_OPEN_REJECT;
  997. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  998. break;
  999. }
  1000. case TRANS_TX_OPEN_TIMEOUT_ERR:
  1001. {
  1002. ts->stat = SAS_OPEN_TO;
  1003. break;
  1004. }
  1005. case TRANS_TX_NAK_RECEIVE_ERR:
  1006. case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
  1007. {
  1008. ts->stat = SAS_NAK_R_ERR;
  1009. break;
  1010. }
  1011. case TRANS_TX_CREDIT_TIMEOUT_ERR:
  1012. case TRANS_TX_CLOSE_NORMAL_ERR:
  1013. {
  1014. /* This will request a retry */
  1015. ts->stat = SAS_QUEUE_FULL;
  1016. slot->abort = 1;
  1017. break;
  1018. }
  1019. default:
  1020. {
  1021. ts->stat = SAM_STAT_CHECK_CONDITION;
  1022. break;
  1023. }
  1024. }
  1025. }
  1026. break;
  1027. case SAS_PROTOCOL_SMP:
  1028. ts->stat = SAM_STAT_CHECK_CONDITION;
  1029. break;
  1030. case SAS_PROTOCOL_SATA:
  1031. case SAS_PROTOCOL_STP:
  1032. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1033. {
  1034. dev_err(dev, "slot err: SATA/STP not supported\n");
  1035. }
  1036. break;
  1037. default:
  1038. break;
  1039. }
  1040. }
  1041. static void slot_complete_v1_hw(struct hisi_hba *hisi_hba,
  1042. struct hisi_sas_slot *slot)
  1043. {
  1044. struct sas_task *task = slot->task;
  1045. struct hisi_sas_device *sas_dev;
  1046. struct device *dev = hisi_hba->dev;
  1047. struct task_status_struct *ts;
  1048. struct domain_device *device;
  1049. struct hisi_sas_complete_v1_hdr *complete_queue =
  1050. hisi_hba->complete_hdr[slot->cmplt_queue];
  1051. struct hisi_sas_complete_v1_hdr *complete_hdr;
  1052. unsigned long flags;
  1053. u32 cmplt_hdr_data;
  1054. complete_hdr = &complete_queue[slot->cmplt_queue_slot];
  1055. cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
  1056. if (unlikely(!task || !task->lldd_task || !task->dev))
  1057. return;
  1058. ts = &task->task_status;
  1059. device = task->dev;
  1060. sas_dev = device->lldd_dev;
  1061. spin_lock_irqsave(&task->task_state_lock, flags);
  1062. task->task_state_flags &=
  1063. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1064. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1065. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1066. memset(ts, 0, sizeof(*ts));
  1067. ts->resp = SAS_TASK_COMPLETE;
  1068. if (unlikely(!sas_dev)) {
  1069. dev_dbg(dev, "slot complete: port has no device\n");
  1070. ts->stat = SAS_PHY_DOWN;
  1071. goto out;
  1072. }
  1073. if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
  1074. u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
  1075. if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
  1076. dev_err(dev, "slot complete: [%d:%d] has dq IPTT err\n",
  1077. slot->cmplt_queue, slot->cmplt_queue_slot);
  1078. if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
  1079. dev_err(dev, "slot complete: [%d:%d] has dq type err\n",
  1080. slot->cmplt_queue, slot->cmplt_queue_slot);
  1081. if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
  1082. dev_err(dev, "slot complete: [%d:%d] has dq force phy err\n",
  1083. slot->cmplt_queue, slot->cmplt_queue_slot);
  1084. if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
  1085. dev_err(dev, "slot complete: [%d:%d] has dq phy id err\n",
  1086. slot->cmplt_queue, slot->cmplt_queue_slot);
  1087. if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
  1088. dev_err(dev, "slot complete: [%d:%d] has dq abort flag err\n",
  1089. slot->cmplt_queue, slot->cmplt_queue_slot);
  1090. if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
  1091. dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err\n",
  1092. slot->cmplt_queue, slot->cmplt_queue_slot);
  1093. if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
  1094. dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err\n",
  1095. slot->cmplt_queue, slot->cmplt_queue_slot);
  1096. if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
  1097. dev_err(dev, "slot complete: [%d:%d] has dq order frame len err\n",
  1098. slot->cmplt_queue, slot->cmplt_queue_slot);
  1099. ts->stat = SAS_OPEN_REJECT;
  1100. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1101. goto out;
  1102. }
  1103. if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK &&
  1104. !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
  1105. slot_err_v1_hw(hisi_hba, task, slot);
  1106. if (unlikely(slot->abort)) {
  1107. sas_task_abort(task);
  1108. return;
  1109. }
  1110. goto out;
  1111. }
  1112. switch (task->task_proto) {
  1113. case SAS_PROTOCOL_SSP:
  1114. {
  1115. struct hisi_sas_status_buffer *status_buffer =
  1116. hisi_sas_status_buf_addr_mem(slot);
  1117. struct ssp_response_iu *iu = (struct ssp_response_iu *)
  1118. &status_buffer->iu[0];
  1119. sas_ssp_task_response(dev, task, iu);
  1120. break;
  1121. }
  1122. case SAS_PROTOCOL_SMP:
  1123. {
  1124. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1125. void *to = page_address(sg_page(sg_resp));
  1126. ts->stat = SAM_STAT_GOOD;
  1127. dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
  1128. DMA_TO_DEVICE);
  1129. memcpy(to + sg_resp->offset,
  1130. hisi_sas_status_buf_addr_mem(slot) +
  1131. sizeof(struct hisi_sas_err_record),
  1132. sg_resp->length);
  1133. break;
  1134. }
  1135. case SAS_PROTOCOL_SATA:
  1136. case SAS_PROTOCOL_STP:
  1137. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1138. dev_err(dev, "slot complete: SATA/STP not supported\n");
  1139. break;
  1140. default:
  1141. ts->stat = SAM_STAT_CHECK_CONDITION;
  1142. break;
  1143. }
  1144. if (!slot->port->port_attached) {
  1145. dev_err(dev, "slot complete: port %d has removed\n",
  1146. slot->port->sas_port.id);
  1147. ts->stat = SAS_PHY_DOWN;
  1148. }
  1149. out:
  1150. hisi_sas_slot_task_free(hisi_hba, task, slot);
  1151. if (task->task_done)
  1152. task->task_done(task);
  1153. }
  1154. /* Interrupts */
  1155. static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
  1156. {
  1157. struct hisi_sas_phy *phy = p;
  1158. struct hisi_hba *hisi_hba = phy->hisi_hba;
  1159. struct device *dev = hisi_hba->dev;
  1160. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1161. int i, phy_no = sas_phy->id;
  1162. u32 irq_value, context, port_id, link_rate;
  1163. u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
  1164. struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
  1165. irqreturn_t res = IRQ_HANDLED;
  1166. unsigned long flags;
  1167. irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
  1168. if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
  1169. dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
  1170. irq_value);
  1171. res = IRQ_NONE;
  1172. goto end;
  1173. }
  1174. context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
  1175. if (context & 1 << phy_no) {
  1176. dev_err(dev, "phyup: phy%d SATA attached equipment\n",
  1177. phy_no);
  1178. goto end;
  1179. }
  1180. port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
  1181. & 0xf;
  1182. if (port_id == 0xf) {
  1183. dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
  1184. res = IRQ_NONE;
  1185. goto end;
  1186. }
  1187. for (i = 0; i < 6; i++) {
  1188. u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
  1189. RX_IDAF_DWORD0 + (i * 4));
  1190. frame_rcvd[i] = __swab32(idaf);
  1191. }
  1192. /* Get the linkrate */
  1193. link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
  1194. link_rate = (link_rate >> (phy_no * 4)) & 0xf;
  1195. sas_phy->linkrate = link_rate;
  1196. sas_phy->oob_mode = SAS_OOB_MODE;
  1197. memcpy(sas_phy->attached_sas_addr,
  1198. &id->sas_addr, SAS_ADDR_SIZE);
  1199. dev_info(dev, "phyup: phy%d link_rate=%d\n",
  1200. phy_no, link_rate);
  1201. phy->port_id = port_id;
  1202. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  1203. phy->phy_type |= PORT_TYPE_SAS;
  1204. phy->phy_attached = 1;
  1205. phy->identify.device_type = id->dev_type;
  1206. phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
  1207. if (phy->identify.device_type == SAS_END_DEVICE)
  1208. phy->identify.target_port_protocols =
  1209. SAS_PROTOCOL_SSP;
  1210. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  1211. phy->identify.target_port_protocols =
  1212. SAS_PROTOCOL_SMP;
  1213. hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
  1214. spin_lock_irqsave(&phy->lock, flags);
  1215. if (phy->reset_completion) {
  1216. phy->in_reset = 0;
  1217. complete(phy->reset_completion);
  1218. }
  1219. spin_unlock_irqrestore(&phy->lock, flags);
  1220. end:
  1221. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
  1222. CHL_INT2_SL_PHY_ENA_MSK);
  1223. if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
  1224. u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
  1225. chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
  1226. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
  1227. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
  1228. }
  1229. return res;
  1230. }
  1231. static irqreturn_t int_bcast_v1_hw(int irq, void *p)
  1232. {
  1233. struct hisi_sas_phy *phy = p;
  1234. struct hisi_hba *hisi_hba = phy->hisi_hba;
  1235. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1236. struct device *dev = hisi_hba->dev;
  1237. int phy_no = sas_phy->id;
  1238. u32 irq_value;
  1239. irqreturn_t res = IRQ_HANDLED;
  1240. irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
  1241. if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
  1242. dev_err(dev, "bcast: irq_value = %x not set enable bit\n",
  1243. irq_value);
  1244. res = IRQ_NONE;
  1245. goto end;
  1246. }
  1247. if (!test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
  1248. sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  1249. end:
  1250. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
  1251. CHL_INT2_SL_RX_BC_ACK_MSK);
  1252. return res;
  1253. }
  1254. static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
  1255. {
  1256. struct hisi_sas_phy *phy = p;
  1257. struct hisi_hba *hisi_hba = phy->hisi_hba;
  1258. struct device *dev = hisi_hba->dev;
  1259. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1260. u32 irq_value, irq_mask_old;
  1261. int phy_no = sas_phy->id;
  1262. /* mask_int0 */
  1263. irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
  1264. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
  1265. /* read int0 */
  1266. irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
  1267. if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
  1268. u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
  1269. hisi_sas_phy_down(hisi_hba, phy_no,
  1270. (phy_state & 1 << phy_no) ? 1 : 0);
  1271. }
  1272. if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
  1273. dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
  1274. phy_no);
  1275. if (irq_value & CHL_INT0_DWS_LOST_MSK)
  1276. dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
  1277. if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
  1278. dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
  1279. phy_no);
  1280. if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
  1281. irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
  1282. dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
  1283. phy_no);
  1284. if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
  1285. dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
  1286. /* write to zero */
  1287. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
  1288. if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
  1289. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
  1290. 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
  1291. else
  1292. hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
  1293. irq_mask_old);
  1294. return IRQ_HANDLED;
  1295. }
  1296. static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
  1297. {
  1298. struct hisi_sas_cq *cq = p;
  1299. struct hisi_hba *hisi_hba = cq->hisi_hba;
  1300. struct hisi_sas_slot *slot;
  1301. int queue = cq->id;
  1302. struct hisi_sas_complete_v1_hdr *complete_queue =
  1303. (struct hisi_sas_complete_v1_hdr *)
  1304. hisi_hba->complete_hdr[queue];
  1305. u32 rd_point = cq->rd_point, wr_point;
  1306. spin_lock(&hisi_hba->lock);
  1307. hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
  1308. wr_point = hisi_sas_read32(hisi_hba,
  1309. COMPL_Q_0_WR_PTR + (0x14 * queue));
  1310. while (rd_point != wr_point) {
  1311. struct hisi_sas_complete_v1_hdr *complete_hdr;
  1312. int idx;
  1313. u32 cmplt_hdr_data;
  1314. complete_hdr = &complete_queue[rd_point];
  1315. cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
  1316. idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
  1317. CMPLT_HDR_IPTT_OFF;
  1318. slot = &hisi_hba->slot_info[idx];
  1319. /* The completion queue and queue slot index are not
  1320. * necessarily the same as the delivery queue and
  1321. * queue slot index.
  1322. */
  1323. slot->cmplt_queue_slot = rd_point;
  1324. slot->cmplt_queue = queue;
  1325. slot_complete_v1_hw(hisi_hba, slot);
  1326. if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
  1327. rd_point = 0;
  1328. }
  1329. /* update rd_point */
  1330. cq->rd_point = rd_point;
  1331. hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
  1332. spin_unlock(&hisi_hba->lock);
  1333. return IRQ_HANDLED;
  1334. }
  1335. static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
  1336. {
  1337. struct hisi_hba *hisi_hba = p;
  1338. struct device *dev = hisi_hba->dev;
  1339. u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
  1340. if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
  1341. u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
  1342. panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
  1343. dev_name(dev), ecc_err);
  1344. }
  1345. if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
  1346. u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
  1347. HGC_DQ_ECC_ADDR_BAD_MSK) >>
  1348. HGC_DQ_ECC_ADDR_BAD_OFF;
  1349. panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
  1350. dev_name(dev), addr);
  1351. }
  1352. if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
  1353. u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
  1354. panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
  1355. dev_name(dev), ecc_err);
  1356. }
  1357. if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
  1358. u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
  1359. HGC_IOST_ECC_ADDR_BAD_MSK) >>
  1360. HGC_IOST_ECC_ADDR_BAD_OFF;
  1361. panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
  1362. dev_name(dev), addr);
  1363. }
  1364. if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
  1365. u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
  1366. HGC_ITCT_ECC_ADDR_BAD_MSK) >>
  1367. HGC_ITCT_ECC_ADDR_BAD_OFF;
  1368. panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
  1369. dev_name(dev), addr);
  1370. }
  1371. if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
  1372. u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
  1373. panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
  1374. dev_name(dev), ecc_err);
  1375. }
  1376. hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
  1377. return IRQ_HANDLED;
  1378. }
  1379. static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
  1380. {
  1381. struct hisi_hba *hisi_hba = p;
  1382. struct device *dev = hisi_hba->dev;
  1383. u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
  1384. u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
  1385. if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
  1386. panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
  1387. dev_name(dev), axi_info);
  1388. if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
  1389. panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
  1390. dev_name(dev), axi_info);
  1391. if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
  1392. panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
  1393. dev_name(dev), axi_info);
  1394. if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
  1395. panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
  1396. dev_name(dev), axi_info);
  1397. hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
  1398. return IRQ_HANDLED;
  1399. }
  1400. static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
  1401. int_bcast_v1_hw,
  1402. int_phyup_v1_hw,
  1403. int_abnormal_v1_hw
  1404. };
  1405. static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
  1406. fatal_ecc_int_v1_hw,
  1407. fatal_axi_int_v1_hw
  1408. };
  1409. static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
  1410. {
  1411. struct platform_device *pdev = hisi_hba->platform_dev;
  1412. struct device *dev = &pdev->dev;
  1413. int i, j, irq, rc, idx;
  1414. for (i = 0; i < hisi_hba->n_phy; i++) {
  1415. struct hisi_sas_phy *phy = &hisi_hba->phy[i];
  1416. idx = i * HISI_SAS_PHY_INT_NR;
  1417. for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
  1418. irq = platform_get_irq(pdev, idx);
  1419. if (irq < 0) {
  1420. dev_err(dev, "irq init: fail map phy interrupt %d\n",
  1421. idx);
  1422. return irq;
  1423. }
  1424. rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
  1425. DRV_NAME " phy", phy);
  1426. if (rc) {
  1427. dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
  1428. irq, rc);
  1429. return rc;
  1430. }
  1431. }
  1432. }
  1433. idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
  1434. for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
  1435. irq = platform_get_irq(pdev, idx);
  1436. if (irq < 0) {
  1437. dev_err(dev, "irq init: could not map cq interrupt %d\n",
  1438. idx);
  1439. return irq;
  1440. }
  1441. rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
  1442. DRV_NAME " cq", &hisi_hba->cq[i]);
  1443. if (rc) {
  1444. dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
  1445. irq, rc);
  1446. return rc;
  1447. }
  1448. }
  1449. idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
  1450. for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
  1451. irq = platform_get_irq(pdev, idx);
  1452. if (irq < 0) {
  1453. dev_err(dev, "irq init: could not map fatal interrupt %d\n",
  1454. idx);
  1455. return irq;
  1456. }
  1457. rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
  1458. DRV_NAME " fatal", hisi_hba);
  1459. if (rc) {
  1460. dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
  1461. irq, rc);
  1462. return rc;
  1463. }
  1464. }
  1465. hisi_hba->cq_nvecs = hisi_hba->queue_count;
  1466. return 0;
  1467. }
  1468. static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
  1469. {
  1470. int i;
  1471. u32 val;
  1472. for (i = 0; i < hisi_hba->n_phy; i++) {
  1473. /* Clear interrupt status */
  1474. val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
  1475. hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
  1476. val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
  1477. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
  1478. val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
  1479. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
  1480. /* Unmask interrupt */
  1481. hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
  1482. hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
  1483. hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
  1484. /* bypass chip bug mask abnormal intr */
  1485. hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK,
  1486. 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
  1487. }
  1488. return 0;
  1489. }
  1490. static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
  1491. {
  1492. int rc;
  1493. rc = hw_init_v1_hw(hisi_hba);
  1494. if (rc)
  1495. return rc;
  1496. rc = interrupt_init_v1_hw(hisi_hba);
  1497. if (rc)
  1498. return rc;
  1499. rc = interrupt_openall_v1_hw(hisi_hba);
  1500. if (rc)
  1501. return rc;
  1502. return 0;
  1503. }
  1504. static struct device_attribute *host_attrs_v1_hw[] = {
  1505. &dev_attr_phy_event_threshold,
  1506. NULL
  1507. };
  1508. static struct scsi_host_template sht_v1_hw = {
  1509. .name = DRV_NAME,
  1510. .proc_name = DRV_NAME,
  1511. .module = THIS_MODULE,
  1512. .queuecommand = sas_queuecommand,
  1513. .dma_need_drain = ata_scsi_dma_need_drain,
  1514. .target_alloc = sas_target_alloc,
  1515. .slave_configure = hisi_sas_slave_configure,
  1516. .scan_finished = hisi_sas_scan_finished,
  1517. .scan_start = hisi_sas_scan_start,
  1518. .change_queue_depth = sas_change_queue_depth,
  1519. .bios_param = sas_bios_param,
  1520. .this_id = -1,
  1521. .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
  1522. .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
  1523. .eh_device_reset_handler = sas_eh_device_reset_handler,
  1524. .eh_target_reset_handler = sas_eh_target_reset_handler,
  1525. .slave_alloc = sas_slave_alloc,
  1526. .target_destroy = sas_target_destroy,
  1527. .ioctl = sas_ioctl,
  1528. #ifdef CONFIG_COMPAT
  1529. .compat_ioctl = sas_ioctl,
  1530. #endif
  1531. .shost_attrs = host_attrs_v1_hw,
  1532. .host_reset = hisi_sas_host_reset,
  1533. };
  1534. static const struct hisi_sas_hw hisi_sas_v1_hw = {
  1535. .hw_init = hisi_sas_v1_init,
  1536. .setup_itct = setup_itct_v1_hw,
  1537. .sl_notify_ssp = sl_notify_ssp_v1_hw,
  1538. .clear_itct = clear_itct_v1_hw,
  1539. .prep_smp = prep_smp_v1_hw,
  1540. .prep_ssp = prep_ssp_v1_hw,
  1541. .start_delivery = start_delivery_v1_hw,
  1542. .phys_init = phys_init_v1_hw,
  1543. .phy_start = start_phy_v1_hw,
  1544. .phy_disable = disable_phy_v1_hw,
  1545. .phy_hard_reset = phy_hard_reset_v1_hw,
  1546. .phy_set_linkrate = phy_set_linkrate_v1_hw,
  1547. .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw,
  1548. .get_wideport_bitmap = get_wideport_bitmap_v1_hw,
  1549. .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
  1550. .sht = &sht_v1_hw,
  1551. };
  1552. static int hisi_sas_v1_probe(struct platform_device *pdev)
  1553. {
  1554. return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
  1555. }
  1556. static int hisi_sas_v1_remove(struct platform_device *pdev)
  1557. {
  1558. return hisi_sas_remove(pdev);
  1559. }
  1560. static const struct of_device_id sas_v1_of_match[] = {
  1561. { .compatible = "hisilicon,hip05-sas-v1",},
  1562. {},
  1563. };
  1564. MODULE_DEVICE_TABLE(of, sas_v1_of_match);
  1565. static const struct acpi_device_id sas_v1_acpi_match[] = {
  1566. { "HISI0161", 0 },
  1567. { }
  1568. };
  1569. MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match);
  1570. static struct platform_driver hisi_sas_v1_driver = {
  1571. .probe = hisi_sas_v1_probe,
  1572. .remove = hisi_sas_v1_remove,
  1573. .driver = {
  1574. .name = DRV_NAME,
  1575. .of_match_table = sas_v1_of_match,
  1576. .acpi_match_table = ACPI_PTR(sas_v1_acpi_match),
  1577. },
  1578. };
  1579. module_platform_driver(hisi_sas_v1_driver);
  1580. MODULE_LICENSE("GPL");
  1581. MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
  1582. MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
  1583. MODULE_ALIAS("platform:" DRV_NAME);