gdth.h 44 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _GDTH_H
  3. #define _GDTH_H
  4. /*
  5. * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux
  6. *
  7. * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner
  8. * See gdth.c for further informations and
  9. * below for supported controller types
  10. *
  11. * <achim_leubner@adaptec.com>
  12. *
  13. * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $
  14. */
  15. #include <linux/types.h>
  16. #ifndef TRUE
  17. #define TRUE 1
  18. #endif
  19. #ifndef FALSE
  20. #define FALSE 0
  21. #endif
  22. /* defines, macros */
  23. /* driver version */
  24. #define GDTH_VERSION_STR "3.05"
  25. #define GDTH_VERSION 3
  26. #define GDTH_SUBVERSION 5
  27. /* protocol version */
  28. #define PROTOCOL_VERSION 1
  29. /* OEM IDs */
  30. #define OEM_ID_ICP 0x941c
  31. #define OEM_ID_INTEL 0x8000
  32. /* controller classes */
  33. #define GDT_PCI 0x03 /* PCI controller */
  34. #define GDT_PCINEW 0x04 /* new PCI controller */
  35. #define GDT_PCIMPR 0x05 /* PCI MPR controller */
  36. #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
  37. /* GDT_PCI */
  38. #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
  39. #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
  40. /* GDT_PCINEW */
  41. #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
  42. #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
  43. #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
  44. #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
  45. /* GDT_PCINEW, wide/ultra SCSI controllers */
  46. #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
  47. #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
  48. #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
  49. #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
  50. /* GDT_PCINEW, wide SCSI controllers */
  51. #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
  52. #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
  53. #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
  54. #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
  55. #endif
  56. #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
  57. /* GDT_MPR, RP series, wide/ultra SCSI */
  58. #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
  59. #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
  60. #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
  61. #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
  62. /* GDT_MPR, RP series, narrow/ultra SCSI */
  63. #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
  64. #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
  65. #endif
  66. #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
  67. /* GDT_MPR, RD series, wide/ultra SCSI */
  68. #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
  69. #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
  70. #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
  71. #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
  72. /* GDT_MPR, RD series, narrow/ultra SCSI */
  73. #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
  74. #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
  75. /* GDT_MPR, RD series, wide/ultra2 SCSI */
  76. #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
  77. GDT6618RD */
  78. #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
  79. GDT6628RD */
  80. #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
  81. #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
  82. /* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
  83. #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
  84. GDT7618RN */
  85. #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
  86. GDT7628RN */
  87. #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
  88. #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
  89. #endif
  90. #ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
  91. /* GDT_MPR, RD series, Fibre Channel */
  92. #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
  93. #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
  94. /* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
  95. #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
  96. #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
  97. #endif
  98. #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
  99. /* GDT_MPR, last device ID */
  100. #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
  101. #endif
  102. #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
  103. /* new GDT Rx Controller */
  104. #define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300
  105. #endif
  106. #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2
  107. /* new(2) GDT Rx Controller */
  108. #define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301
  109. #endif
  110. #ifndef PCI_DEVICE_ID_INTEL_SRC
  111. /* Intel Storage RAID Controller */
  112. #define PCI_DEVICE_ID_INTEL_SRC 0x600
  113. #endif
  114. #ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE
  115. /* Intel Storage RAID Controller */
  116. #define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601
  117. #endif
  118. /* limits */
  119. #define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */
  120. #define GDTH_MAXCMDS 120
  121. #define GDTH_MAXC_P_L 16 /* max. cmds per lun */
  122. #define GDTH_MAX_RAW 2 /* max. cmds per raw device */
  123. #define MAXOFFSETS 128
  124. #define MAXHA 16
  125. #define MAXID 127
  126. #define MAXLUN 8
  127. #define MAXBUS 6
  128. #define MAX_EVENTS 100 /* event buffer count */
  129. #define MAX_RES_ARGS 40 /* device reservation,
  130. must be a multiple of 4 */
  131. #define MAXCYLS 1024
  132. #define HEADS 64
  133. #define SECS 32 /* mapping 64*32 */
  134. #define MEDHEADS 127
  135. #define MEDSECS 63 /* mapping 127*63 */
  136. #define BIGHEADS 255
  137. #define BIGSECS 63 /* mapping 255*63 */
  138. /* special command ptr. */
  139. #define UNUSED_CMND ((struct scsi_cmnd *)-1)
  140. #define INTERNAL_CMND ((struct scsi_cmnd *)-2)
  141. #define SCREEN_CMND ((struct scsi_cmnd *)-3)
  142. #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
  143. /* controller services */
  144. #define SCSIRAWSERVICE 3
  145. #define CACHESERVICE 9
  146. #define SCREENSERVICE 11
  147. /* screenservice defines */
  148. #define MSG_INV_HANDLE -1 /* special message handle */
  149. #define MSGLEN 16 /* size of message text */
  150. #define MSG_SIZE 34 /* size of message structure */
  151. #define MSG_REQUEST 0 /* async. event: message */
  152. /* DPMEM constants */
  153. #define DPMEM_MAGIC 0xC0FFEE11
  154. #define IC_HEADER_BYTES 48
  155. #define IC_QUEUE_BYTES 4
  156. #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
  157. /* cluster_type constants */
  158. #define CLUSTER_DRIVE 1
  159. #define CLUSTER_MOUNTED 2
  160. #define CLUSTER_RESERVED 4
  161. #define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
  162. /* commands for all services, cache service */
  163. #define GDT_INIT 0 /* service initialization */
  164. #define GDT_READ 1 /* read command */
  165. #define GDT_WRITE 2 /* write command */
  166. #define GDT_INFO 3 /* information about devices */
  167. #define GDT_FLUSH 4 /* flush dirty cache buffers */
  168. #define GDT_IOCTL 5 /* ioctl command */
  169. #define GDT_DEVTYPE 9 /* additional information */
  170. #define GDT_MOUNT 10 /* mount cache device */
  171. #define GDT_UNMOUNT 11 /* unmount cache device */
  172. #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
  173. #define GDT_GET_FEAT 13 /* get features */
  174. #define GDT_WRITE_THR 16 /* write through */
  175. #define GDT_READ_THR 17 /* read through */
  176. #define GDT_EXT_INFO 18 /* extended info */
  177. #define GDT_RESET 19 /* controller reset */
  178. #define GDT_RESERVE_DRV 20 /* reserve host drive */
  179. #define GDT_RELEASE_DRV 21 /* release host drive */
  180. #define GDT_CLUST_INFO 22 /* cluster info */
  181. #define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/
  182. #define GDT_CLUST_RESET 24 /* releases the cluster drives*/
  183. #define GDT_FREEZE_IO 25 /* freezes all IOs */
  184. #define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */
  185. #define GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */
  186. #define GDT_X_INFO 30 /* ext. info for drives>2TB */
  187. /* raw service commands */
  188. #define GDT_RESERVE 14 /* reserve dev. to raw serv. */
  189. #define GDT_RELEASE 15 /* release device */
  190. #define GDT_RESERVE_ALL 16 /* reserve all devices */
  191. #define GDT_RELEASE_ALL 17 /* release all devices */
  192. #define GDT_RESET_BUS 18 /* reset bus */
  193. #define GDT_SCAN_START 19 /* start device scan */
  194. #define GDT_SCAN_END 20 /* stop device scan */
  195. #define GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */
  196. /* screen service commands */
  197. #define GDT_REALTIME 3 /* realtime clock to screens. */
  198. #define GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */
  199. /* IOCTL command defines */
  200. #define SCSI_DR_INFO 0x00 /* SCSI drive info */
  201. #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
  202. #define SCSI_DR_LIST 0x06 /* SCSI drive list */
  203. #define SCSI_DEF_CNT 0x15 /* grown/primary defects */
  204. #define DSK_STATISTICS 0x4b /* SCSI disk statistics */
  205. #define IOCHAN_DESC 0x5d /* description of IO channel */
  206. #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */
  207. #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
  208. #define ARRAY_INFO 0x12 /* array drive info */
  209. #define ARRAY_DRV_LIST 0x0f /* array drive list */
  210. #define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */
  211. #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
  212. #define CACHE_DRV_CNT 0x01 /* cache drive count */
  213. #define CACHE_DRV_LIST 0x02 /* cache drive list */
  214. #define CACHE_INFO 0x04 /* cache info */
  215. #define CACHE_CONFIG 0x05 /* cache configuration */
  216. #define CACHE_DRV_INFO 0x07 /* cache drive info */
  217. #define BOARD_FEATURES 0x15 /* controller features */
  218. #define BOARD_INFO 0x28 /* controller info */
  219. #define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */
  220. #define GET_PERF_MODES 0x83 /* get mode */
  221. #define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */
  222. #define HOST_GET 0x10001L /* get host drive list */
  223. #define IO_CHANNEL 0x00020000L /* default IO channel */
  224. #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
  225. /* service errors */
  226. #define S_OK 1 /* no error */
  227. #define S_GENERR 6 /* general error */
  228. #define S_BSY 7 /* controller busy */
  229. #define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */
  230. #define S_RAW_SCSI 12 /* raw serv.: target error */
  231. #define S_RAW_ILL 0xff /* raw serv.: illegal */
  232. #define S_NOFUNC -2 /* unknown function */
  233. #define S_CACHE_RESERV -24 /* cache: reserv. conflict */
  234. /* timeout values */
  235. #define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */
  236. #define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */
  237. #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
  238. /* priorities */
  239. #define DEFAULT_PRI 0x20
  240. #define IOCTL_PRI 0x10
  241. #define HIGH_PRI 0x08
  242. /* data directions */
  243. #define GDTH_DATA_IN 0x01000000L /* data from target */
  244. #define GDTH_DATA_OUT 0x00000000L /* data to target */
  245. /* other defines */
  246. #define LINUX_OS 8 /* used for cache optim. */
  247. #define SECS32 0x1f /* round capacity */
  248. #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
  249. #define LOCALBOARD 0 /* board node always 0 */
  250. #define ASYNCINDEX 0 /* cmd index async. event */
  251. #define SPEZINDEX 1 /* cmd index unknown service */
  252. #define COALINDEX (GDTH_MAXCMDS + 2)
  253. /* features */
  254. #define SCATTER_GATHER 1 /* s/g feature */
  255. #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
  256. #define GDT_64BIT 0x200 /* 64bit / drv>2TB support */
  257. #include "gdth_ioctl.h"
  258. /* screenservice message */
  259. typedef struct {
  260. u32 msg_handle; /* message handle */
  261. u32 msg_len; /* size of message */
  262. u32 msg_alen; /* answer length */
  263. u8 msg_answer; /* answer flag */
  264. u8 msg_ext; /* more messages */
  265. u8 msg_reserved[2];
  266. char msg_text[MSGLEN+2]; /* the message text */
  267. } __attribute__((packed)) gdth_msg_str;
  268. /* IOCTL data structures */
  269. /* Status coalescing buffer for returning multiple requests per interrupt */
  270. typedef struct {
  271. u32 status;
  272. u32 ext_status;
  273. u32 info0;
  274. u32 info1;
  275. } __attribute__((packed)) gdth_coal_status;
  276. /* performance mode data structure */
  277. typedef struct {
  278. u32 version; /* The version of this IOCTL structure. */
  279. u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */
  280. u32 st_buff_addr1; /* physical address of status buffer 1 */
  281. u32 st_buff_u_addr1; /* reserved for 64 bit addressing */
  282. u32 st_buff_indx1; /* reserved command idx. for this buffer */
  283. u32 st_buff_addr2; /* physical address of status buffer 1 */
  284. u32 st_buff_u_addr2; /* reserved for 64 bit addressing */
  285. u32 st_buff_indx2; /* reserved command idx. for this buffer */
  286. u32 st_buff_size; /* size of each buffer in bytes */
  287. u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */
  288. u32 cmd_buff_addr1; /* physical address of cmd buffer 1 */
  289. u32 cmd_buff_u_addr1; /* reserved for 64 bit addressing */
  290. u32 cmd_buff_indx1; /* cmd buf addr1 unique identifier */
  291. u32 cmd_buff_addr2; /* physical address of cmd buffer 1 */
  292. u32 cmd_buff_u_addr2; /* reserved for 64 bit addressing */
  293. u32 cmd_buff_indx2; /* cmd buf addr1 unique identifier */
  294. u32 cmd_buff_size; /* size of each cmd buffer in bytes */
  295. u32 reserved1;
  296. u32 reserved2;
  297. } __attribute__((packed)) gdth_perf_modes;
  298. /* SCSI drive info */
  299. typedef struct {
  300. u8 vendor[8]; /* vendor string */
  301. u8 product[16]; /* product string */
  302. u8 revision[4]; /* revision */
  303. u32 sy_rate; /* current rate for sync. tr. */
  304. u32 sy_max_rate; /* max. rate for sync. tr. */
  305. u32 no_ldrive; /* belongs to this log. drv.*/
  306. u32 blkcnt; /* number of blocks */
  307. u16 blksize; /* size of block in bytes */
  308. u8 available; /* flag: access is available */
  309. u8 init; /* medium is initialized */
  310. u8 devtype; /* SCSI devicetype */
  311. u8 rm_medium; /* medium is removable */
  312. u8 wp_medium; /* medium is write protected */
  313. u8 ansi; /* SCSI I/II or III? */
  314. u8 protocol; /* same as ansi */
  315. u8 sync; /* flag: sync. transfer enab. */
  316. u8 disc; /* flag: disconnect enabled */
  317. u8 queueing; /* flag: command queing enab. */
  318. u8 cached; /* flag: caching enabled */
  319. u8 target_id; /* target ID of device */
  320. u8 lun; /* LUN id of device */
  321. u8 orphan; /* flag: drive fragment */
  322. u32 last_error; /* sense key or drive state */
  323. u32 last_result; /* result of last command */
  324. u32 check_errors; /* err. in last surface check */
  325. u8 percent; /* progress for surface check */
  326. u8 last_check; /* IOCTRL operation */
  327. u8 res[2];
  328. u32 flags; /* from 1.19/2.19: raw reserv.*/
  329. u8 multi_bus; /* multi bus dev? (fibre ch.) */
  330. u8 mb_status; /* status: available? */
  331. u8 res2[2];
  332. u8 mb_alt_status; /* status on second bus */
  333. u8 mb_alt_bid; /* number of second bus */
  334. u8 mb_alt_tid; /* target id on second bus */
  335. u8 res3;
  336. u8 fc_flag; /* from 1.22/2.22: info valid?*/
  337. u8 res4;
  338. u16 fc_frame_size; /* frame size (bytes) */
  339. char wwn[8]; /* world wide name */
  340. } __attribute__((packed)) gdth_diskinfo_str;
  341. /* get SCSI channel count */
  342. typedef struct {
  343. u32 channel_no; /* number of channel */
  344. u32 drive_cnt; /* drive count */
  345. u8 siop_id; /* SCSI processor ID */
  346. u8 siop_state; /* SCSI processor state */
  347. } __attribute__((packed)) gdth_getch_str;
  348. /* get SCSI drive numbers */
  349. typedef struct {
  350. u32 sc_no; /* SCSI channel */
  351. u32 sc_cnt; /* sc_list[] elements */
  352. u32 sc_list[MAXID]; /* minor device numbers */
  353. } __attribute__((packed)) gdth_drlist_str;
  354. /* get grown/primary defect count */
  355. typedef struct {
  356. u8 sddc_type; /* 0x08: grown, 0x10: prim. */
  357. u8 sddc_format; /* list entry format */
  358. u8 sddc_len; /* list entry length */
  359. u8 sddc_res;
  360. u32 sddc_cnt; /* entry count */
  361. } __attribute__((packed)) gdth_defcnt_str;
  362. /* disk statistics */
  363. typedef struct {
  364. u32 bid; /* SCSI channel */
  365. u32 first; /* first SCSI disk */
  366. u32 entries; /* number of elements */
  367. u32 count; /* (R) number of init. el. */
  368. u32 mon_time; /* time stamp */
  369. struct {
  370. u8 tid; /* target ID */
  371. u8 lun; /* LUN */
  372. u8 res[2];
  373. u32 blk_size; /* block size in bytes */
  374. u32 rd_count; /* bytes read */
  375. u32 wr_count; /* bytes written */
  376. u32 rd_blk_count; /* blocks read */
  377. u32 wr_blk_count; /* blocks written */
  378. u32 retries; /* retries */
  379. u32 reassigns; /* reassigns */
  380. } __attribute__((packed)) list[1];
  381. } __attribute__((packed)) gdth_dskstat_str;
  382. /* IO channel header */
  383. typedef struct {
  384. u32 version; /* version (-1UL: newest) */
  385. u8 list_entries; /* list entry count */
  386. u8 first_chan; /* first channel number */
  387. u8 last_chan; /* last channel number */
  388. u8 chan_count; /* (R) channel count */
  389. u32 list_offset; /* offset of list[0] */
  390. } __attribute__((packed)) gdth_iochan_header;
  391. /* get IO channel description */
  392. typedef struct {
  393. gdth_iochan_header hdr;
  394. struct {
  395. u32 address; /* channel address */
  396. u8 type; /* type (SCSI, FCAL) */
  397. u8 local_no; /* local number */
  398. u16 features; /* channel features */
  399. } __attribute__((packed)) list[MAXBUS];
  400. } __attribute__((packed)) gdth_iochan_str;
  401. /* get raw IO channel description */
  402. typedef struct {
  403. gdth_iochan_header hdr;
  404. struct {
  405. u8 proc_id; /* processor id */
  406. u8 proc_defect; /* defect ? */
  407. u8 reserved[2];
  408. } __attribute__((packed)) list[MAXBUS];
  409. } __attribute__((packed)) gdth_raw_iochan_str;
  410. /* array drive component */
  411. typedef struct {
  412. u32 al_controller; /* controller ID */
  413. u8 al_cache_drive; /* cache drive number */
  414. u8 al_status; /* cache drive state */
  415. u8 al_res[2];
  416. } __attribute__((packed)) gdth_arraycomp_str;
  417. /* array drive information */
  418. typedef struct {
  419. u8 ai_type; /* array type (RAID0,4,5) */
  420. u8 ai_cache_drive_cnt; /* active cachedrives */
  421. u8 ai_state; /* array drive state */
  422. u8 ai_master_cd; /* master cachedrive */
  423. u32 ai_master_controller; /* ID of master controller */
  424. u32 ai_size; /* user capacity [sectors] */
  425. u32 ai_striping_size; /* striping size [sectors] */
  426. u32 ai_secsize; /* sector size [bytes] */
  427. u32 ai_err_info; /* failed cache drive */
  428. u8 ai_name[8]; /* name of the array drive */
  429. u8 ai_controller_cnt; /* number of controllers */
  430. u8 ai_removable; /* flag: removable */
  431. u8 ai_write_protected; /* flag: write protected */
  432. u8 ai_devtype; /* type: always direct access */
  433. gdth_arraycomp_str ai_drives[35]; /* drive components: */
  434. u8 ai_drive_entries; /* number of drive components */
  435. u8 ai_protected; /* protection flag */
  436. u8 ai_verify_state; /* state of a parity verify */
  437. u8 ai_ext_state; /* extended array drive state */
  438. u8 ai_expand_state; /* array expand state (>=2.18)*/
  439. u8 ai_reserved[3];
  440. } __attribute__((packed)) gdth_arrayinf_str;
  441. /* get array drive list */
  442. typedef struct {
  443. u32 controller_no; /* controller no. */
  444. u8 cd_handle; /* master cachedrive */
  445. u8 is_arrayd; /* Flag: is array drive? */
  446. u8 is_master; /* Flag: is array master? */
  447. u8 is_parity; /* Flag: is parity drive? */
  448. u8 is_hotfix; /* Flag: is hotfix drive? */
  449. u8 res[3];
  450. } __attribute__((packed)) gdth_alist_str;
  451. typedef struct {
  452. u32 entries_avail; /* allocated entries */
  453. u32 entries_init; /* returned entries */
  454. u32 first_entry; /* first entry number */
  455. u32 list_offset; /* offset of following list */
  456. gdth_alist_str list[1]; /* list */
  457. } __attribute__((packed)) gdth_arcdl_str;
  458. /* cache info/config IOCTL */
  459. typedef struct {
  460. u32 version; /* firmware version */
  461. u16 state; /* cache state (on/off) */
  462. u16 strategy; /* cache strategy */
  463. u16 write_back; /* write back state (on/off) */
  464. u16 block_size; /* cache block size */
  465. } __attribute__((packed)) gdth_cpar_str;
  466. typedef struct {
  467. u32 csize; /* cache size */
  468. u32 read_cnt; /* read/write counter */
  469. u32 write_cnt;
  470. u32 tr_hits; /* hits */
  471. u32 sec_hits;
  472. u32 sec_miss; /* misses */
  473. } __attribute__((packed)) gdth_cstat_str;
  474. typedef struct {
  475. gdth_cpar_str cpar;
  476. gdth_cstat_str cstat;
  477. } __attribute__((packed)) gdth_cinfo_str;
  478. /* cache drive info */
  479. typedef struct {
  480. u8 cd_name[8]; /* cache drive name */
  481. u32 cd_devtype; /* SCSI devicetype */
  482. u32 cd_ldcnt; /* number of log. drives */
  483. u32 cd_last_error; /* last error */
  484. u8 cd_initialized; /* drive is initialized */
  485. u8 cd_removable; /* media is removable */
  486. u8 cd_write_protected; /* write protected */
  487. u8 cd_flags; /* Pool Hot Fix? */
  488. u32 ld_blkcnt; /* number of blocks */
  489. u32 ld_blksize; /* blocksize */
  490. u32 ld_dcnt; /* number of disks */
  491. u32 ld_slave; /* log. drive index */
  492. u32 ld_dtype; /* type of logical drive */
  493. u32 ld_last_error; /* last error */
  494. u8 ld_name[8]; /* log. drive name */
  495. u8 ld_error; /* error */
  496. } __attribute__((packed)) gdth_cdrinfo_str;
  497. /* OEM string */
  498. typedef struct {
  499. u32 ctl_version;
  500. u32 file_major_version;
  501. u32 file_minor_version;
  502. u32 buffer_size;
  503. u32 cpy_count;
  504. u32 ext_error;
  505. u32 oem_id;
  506. u32 board_id;
  507. } __attribute__((packed)) gdth_oem_str_params;
  508. typedef struct {
  509. u8 product_0_1_name[16];
  510. u8 product_4_5_name[16];
  511. u8 product_cluster_name[16];
  512. u8 product_reserved[16];
  513. u8 scsi_cluster_target_vendor_id[16];
  514. u8 cluster_raid_fw_name[16];
  515. u8 oem_brand_name[16];
  516. u8 oem_raid_type[16];
  517. u8 bios_type[13];
  518. u8 bios_title[50];
  519. u8 oem_company_name[37];
  520. u32 pci_id_1;
  521. u32 pci_id_2;
  522. u8 validation_status[80];
  523. u8 reserved_1[4];
  524. u8 scsi_host_drive_inquiry_vendor_id[16];
  525. u8 library_file_template[16];
  526. u8 reserved_2[16];
  527. u8 tool_name_1[32];
  528. u8 tool_name_2[32];
  529. u8 tool_name_3[32];
  530. u8 oem_contact_1[84];
  531. u8 oem_contact_2[84];
  532. u8 oem_contact_3[84];
  533. } __attribute__((packed)) gdth_oem_str;
  534. typedef struct {
  535. gdth_oem_str_params params;
  536. gdth_oem_str text;
  537. } __attribute__((packed)) gdth_oem_str_ioctl;
  538. /* board features */
  539. typedef struct {
  540. u8 chaining; /* Chaining supported */
  541. u8 striping; /* Striping (RAID-0) supp. */
  542. u8 mirroring; /* Mirroring (RAID-1) supp. */
  543. u8 raid; /* RAID-4/5/10 supported */
  544. } __attribute__((packed)) gdth_bfeat_str;
  545. /* board info IOCTL */
  546. typedef struct {
  547. u32 ser_no; /* serial no. */
  548. u8 oem_id[2]; /* OEM ID */
  549. u16 ep_flags; /* eprom flags */
  550. u32 proc_id; /* processor ID */
  551. u32 memsize; /* memory size (bytes) */
  552. u8 mem_banks; /* memory banks */
  553. u8 chan_type; /* channel type */
  554. u8 chan_count; /* channel count */
  555. u8 rdongle_pres; /* dongle present? */
  556. u32 epr_fw_ver; /* (eprom) firmware version */
  557. u32 upd_fw_ver; /* (update) firmware version */
  558. u32 upd_revision; /* update revision */
  559. char type_string[16]; /* controller name */
  560. char raid_string[16]; /* RAID firmware name */
  561. u8 update_pres; /* update present? */
  562. u8 xor_pres; /* XOR engine present? */
  563. u8 prom_type; /* ROM type (eprom/flash) */
  564. u8 prom_count; /* number of ROM devices */
  565. u32 dup_pres; /* duplexing module present? */
  566. u32 chan_pres; /* number of expansion chn. */
  567. u32 mem_pres; /* memory expansion inst. ? */
  568. u8 ft_bus_system; /* fault bus supported? */
  569. u8 subtype_valid; /* board_subtype valid? */
  570. u8 board_subtype; /* subtype/hardware level */
  571. u8 ramparity_pres; /* RAM parity check hardware? */
  572. } __attribute__((packed)) gdth_binfo_str;
  573. /* get host drive info */
  574. typedef struct {
  575. char name[8]; /* host drive name */
  576. u32 size; /* size (sectors) */
  577. u8 host_drive; /* host drive number */
  578. u8 log_drive; /* log. drive (master) */
  579. u8 reserved;
  580. u8 rw_attribs; /* r/w attribs */
  581. u32 start_sec; /* start sector */
  582. } __attribute__((packed)) gdth_hentry_str;
  583. typedef struct {
  584. u32 entries; /* entry count */
  585. u32 offset; /* offset of entries */
  586. u8 secs_p_head; /* sectors/head */
  587. u8 heads_p_cyl; /* heads/cylinder */
  588. u8 reserved;
  589. u8 clust_drvtype; /* cluster drive type */
  590. u32 location; /* controller number */
  591. gdth_hentry_str entry[MAX_HDRIVES]; /* entries */
  592. } __attribute__((packed)) gdth_hget_str;
  593. /* DPRAM structures */
  594. /* interface area ISA/PCI */
  595. typedef struct {
  596. u8 S_Cmd_Indx; /* special command */
  597. u8 volatile S_Status; /* status special command */
  598. u16 reserved1;
  599. u32 S_Info[4]; /* add. info special command */
  600. u8 volatile Sema0; /* command semaphore */
  601. u8 reserved2[3];
  602. u8 Cmd_Index; /* command number */
  603. u8 reserved3[3];
  604. u16 volatile Status; /* command status */
  605. u16 Service; /* service(for async.events) */
  606. u32 Info[2]; /* additional info */
  607. struct {
  608. u16 offset; /* command offs. in the DPRAM*/
  609. u16 serv_id; /* service */
  610. } __attribute__((packed)) comm_queue[MAXOFFSETS]; /* command queue */
  611. u32 bios_reserved[2];
  612. u8 gdt_dpr_cmd[1]; /* commands */
  613. } __attribute__((packed)) gdt_dpr_if;
  614. /* SRAM structure PCI controllers */
  615. typedef struct {
  616. u32 magic; /* controller ID from BIOS */
  617. u16 need_deinit; /* switch betw. BIOS/driver */
  618. u8 switch_support; /* see need_deinit */
  619. u8 padding[9];
  620. u8 os_used[16]; /* OS code per service */
  621. u8 unused[28];
  622. u8 fw_magic; /* contr. ID from firmware */
  623. } __attribute__((packed)) gdt_pci_sram;
  624. /* DPRAM ISA controllers */
  625. typedef struct {
  626. union {
  627. struct {
  628. u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
  629. u16 need_deinit; /* switch betw. BIOS/driver */
  630. u8 switch_support; /* see need_deinit */
  631. u8 padding[9];
  632. u8 os_used[16]; /* OS code per service */
  633. } __attribute__((packed)) dp_sram;
  634. u8 bios_area[0x4000]; /* 16KB reserved for BIOS */
  635. } bu;
  636. union {
  637. gdt_dpr_if ic; /* interface area */
  638. u8 if_area[0x3000]; /* 12KB for interface */
  639. } u;
  640. struct {
  641. u8 memlock; /* write protection DPRAM */
  642. u8 event; /* release event */
  643. u8 irqen; /* board interrupts enable */
  644. u8 irqdel; /* acknowledge board int. */
  645. u8 volatile Sema1; /* status semaphore */
  646. u8 rq; /* IRQ/DRQ configuration */
  647. } __attribute__((packed)) io;
  648. } __attribute__((packed)) gdt2_dpram_str;
  649. /* DPRAM PCI controllers */
  650. typedef struct {
  651. union {
  652. gdt_dpr_if ic; /* interface area */
  653. u8 if_area[0xff0-sizeof(gdt_pci_sram)];
  654. } u;
  655. gdt_pci_sram gdt6sr; /* SRAM structure */
  656. struct {
  657. u8 unused0[1];
  658. u8 volatile Sema1; /* command semaphore */
  659. u8 unused1[3];
  660. u8 irqen; /* board interrupts enable */
  661. u8 unused2[2];
  662. u8 event; /* release event */
  663. u8 unused3[3];
  664. u8 irqdel; /* acknowledge board int. */
  665. u8 unused4[3];
  666. } __attribute__((packed)) io;
  667. } __attribute__((packed)) gdt6_dpram_str;
  668. /* PLX register structure (new PCI controllers) */
  669. typedef struct {
  670. u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
  671. u8 unused1[0x3f];
  672. u8 volatile sema0_reg; /* command semaphore */
  673. u8 volatile sema1_reg; /* status semaphore */
  674. u8 unused2[2];
  675. u16 volatile status; /* command status */
  676. u16 service; /* service */
  677. u32 info[2]; /* additional info */
  678. u8 unused3[0x10];
  679. u8 ldoor_reg; /* PCI to local doorbell */
  680. u8 unused4[3];
  681. u8 volatile edoor_reg; /* local to PCI doorbell */
  682. u8 unused5[3];
  683. u8 control0; /* control0 register(unused) */
  684. u8 control1; /* board interrupts enable */
  685. u8 unused6[0x16];
  686. } __attribute__((packed)) gdt6c_plx_regs;
  687. /* DPRAM new PCI controllers */
  688. typedef struct {
  689. union {
  690. gdt_dpr_if ic; /* interface area */
  691. u8 if_area[0x4000-sizeof(gdt_pci_sram)];
  692. } u;
  693. gdt_pci_sram gdt6sr; /* SRAM structure */
  694. } __attribute__((packed)) gdt6c_dpram_str;
  695. /* i960 register structure (PCI MPR controllers) */
  696. typedef struct {
  697. u8 unused1[16];
  698. u8 volatile sema0_reg; /* command semaphore */
  699. u8 unused2;
  700. u8 volatile sema1_reg; /* status semaphore */
  701. u8 unused3;
  702. u16 volatile status; /* command status */
  703. u16 service; /* service */
  704. u32 info[2]; /* additional info */
  705. u8 ldoor_reg; /* PCI to local doorbell */
  706. u8 unused4[11];
  707. u8 volatile edoor_reg; /* local to PCI doorbell */
  708. u8 unused5[7];
  709. u8 edoor_en_reg; /* board interrupts enable */
  710. u8 unused6[27];
  711. u32 unused7[939];
  712. u32 severity;
  713. char evt_str[256]; /* event string */
  714. } __attribute__((packed)) gdt6m_i960_regs;
  715. /* DPRAM PCI MPR controllers */
  716. typedef struct {
  717. gdt6m_i960_regs i960r; /* 4KB i960 registers */
  718. union {
  719. gdt_dpr_if ic; /* interface area */
  720. u8 if_area[0x3000-sizeof(gdt_pci_sram)];
  721. } u;
  722. gdt_pci_sram gdt6sr; /* SRAM structure */
  723. } __attribute__((packed)) gdt6m_dpram_str;
  724. /* PCI resources */
  725. typedef struct {
  726. struct pci_dev *pdev;
  727. unsigned long dpmem; /* DPRAM address */
  728. unsigned long io; /* IO address */
  729. } gdth_pci_str;
  730. /* controller information structure */
  731. typedef struct {
  732. struct Scsi_Host *shost;
  733. struct list_head list;
  734. u16 hanum;
  735. u16 oem_id; /* OEM */
  736. u16 type; /* controller class */
  737. u32 stype; /* subtype (PCI: device ID) */
  738. u16 fw_vers; /* firmware version */
  739. u16 cache_feat; /* feat. cache serv. (s/g,..)*/
  740. u16 raw_feat; /* feat. raw service (s/g,..)*/
  741. u16 screen_feat; /* feat. raw service (s/g,..)*/
  742. void __iomem *brd; /* DPRAM address */
  743. u32 brd_phys; /* slot number/BIOS address */
  744. gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
  745. gdth_cmd_str cmdext;
  746. gdth_cmd_str *pccb; /* address command structure */
  747. u32 ccb_phys; /* phys. address */
  748. #ifdef INT_COAL
  749. gdth_coal_status *coal_stat; /* buffer for coalescing int.*/
  750. u64 coal_stat_phys; /* phys. address */
  751. #endif
  752. char *pscratch; /* scratch (DMA) buffer */
  753. u64 scratch_phys; /* phys. address */
  754. u8 scratch_busy; /* in use? */
  755. u8 dma64_support; /* 64-bit DMA supported? */
  756. gdth_msg_str *pmsg; /* message buffer */
  757. u64 msg_phys; /* phys. address */
  758. u8 scan_mode; /* current scan mode */
  759. u8 irq; /* IRQ */
  760. u8 drq; /* DRQ (ISA controllers) */
  761. u16 status; /* command status */
  762. u16 service; /* service/firmware ver./.. */
  763. u32 info;
  764. u32 info2; /* additional info */
  765. struct scsi_cmnd *req_first; /* top of request queue */
  766. struct {
  767. u8 present; /* Flag: host drive present? */
  768. u8 is_logdrv; /* Flag: log. drive (master)? */
  769. u8 is_arraydrv; /* Flag: array drive? */
  770. u8 is_master; /* Flag: array drive master? */
  771. u8 is_parity; /* Flag: parity drive? */
  772. u8 is_hotfix; /* Flag: hotfix drive? */
  773. u8 master_no; /* number of master drive */
  774. u8 lock; /* drive locked? (hot plug) */
  775. u8 heads; /* mapping */
  776. u8 secs;
  777. u16 devtype; /* further information */
  778. u64 size; /* capacity */
  779. u8 ldr_no; /* log. drive no. */
  780. u8 rw_attribs; /* r/w attributes */
  781. u8 cluster_type; /* cluster properties */
  782. u8 media_changed; /* Flag:MOUNT/UNMOUNT occurred */
  783. u32 start_sec; /* start sector */
  784. } hdr[MAX_LDRIVES]; /* host drives */
  785. struct {
  786. u8 lock; /* channel locked? (hot plug) */
  787. u8 pdev_cnt; /* physical device count */
  788. u8 local_no; /* local channel number */
  789. u8 io_cnt[MAXID]; /* current IO count */
  790. u32 address; /* channel address */
  791. u32 id_list[MAXID]; /* IDs of the phys. devices */
  792. } raw[MAXBUS]; /* SCSI channels */
  793. struct {
  794. struct scsi_cmnd *cmnd; /* pending request */
  795. u16 service; /* service */
  796. } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */
  797. struct gdth_cmndinfo { /* per-command private info */
  798. int index;
  799. int internal_command; /* don't call scsi_done */
  800. gdth_cmd_str *internal_cmd_str; /* crier for internal messages*/
  801. dma_addr_t sense_paddr; /* sense dma-addr */
  802. u8 priority;
  803. int timeout_count; /* # of timeout calls */
  804. volatile int wait_for_completion;
  805. u16 status;
  806. u32 info;
  807. enum dma_data_direction dma_dir;
  808. int phase; /* ???? */
  809. int OpCode;
  810. } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */
  811. u8 bus_cnt; /* SCSI bus count */
  812. u8 tid_cnt; /* Target ID count */
  813. u8 bus_id[MAXBUS]; /* IOP IDs */
  814. u8 virt_bus; /* number of virtual bus */
  815. u8 more_proc; /* more /proc info supported */
  816. u16 cmd_cnt; /* command count in DPRAM */
  817. u16 cmd_len; /* length of actual command */
  818. u16 cmd_offs_dpmem; /* actual offset in DPRAM */
  819. u16 ic_all_size; /* sizeof DPRAM interf. area */
  820. gdth_cpar_str cpar; /* controller cache par. */
  821. gdth_bfeat_str bfeat; /* controller features */
  822. gdth_binfo_str binfo; /* controller info */
  823. gdth_evt_data dvr; /* event structure */
  824. spinlock_t smp_lock;
  825. struct pci_dev *pdev;
  826. char oem_name[8];
  827. #ifdef GDTH_DMA_STATISTICS
  828. unsigned long dma32_cnt, dma64_cnt; /* statistics: DMA buffer */
  829. #endif
  830. struct scsi_device *sdev;
  831. } gdth_ha_str;
  832. static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd)
  833. {
  834. return (struct gdth_cmndinfo *)cmd->host_scribble;
  835. }
  836. /* INQUIRY data format */
  837. typedef struct {
  838. u8 type_qual;
  839. u8 modif_rmb;
  840. u8 version;
  841. u8 resp_aenc;
  842. u8 add_length;
  843. u8 reserved1;
  844. u8 reserved2;
  845. u8 misc;
  846. u8 vendor[8];
  847. u8 product[16];
  848. u8 revision[4];
  849. } __attribute__((packed)) gdth_inq_data;
  850. /* READ_CAPACITY data format */
  851. typedef struct {
  852. u32 last_block_no;
  853. u32 block_length;
  854. } __attribute__((packed)) gdth_rdcap_data;
  855. /* READ_CAPACITY (16) data format */
  856. typedef struct {
  857. u64 last_block_no;
  858. u32 block_length;
  859. } __attribute__((packed)) gdth_rdcap16_data;
  860. /* REQUEST_SENSE data format */
  861. typedef struct {
  862. u8 errorcode;
  863. u8 segno;
  864. u8 key;
  865. u32 info;
  866. u8 add_length;
  867. u32 cmd_info;
  868. u8 adsc;
  869. u8 adsq;
  870. u8 fruc;
  871. u8 key_spec[3];
  872. } __attribute__((packed)) gdth_sense_data;
  873. /* MODE_SENSE data format */
  874. typedef struct {
  875. struct {
  876. u8 data_length;
  877. u8 med_type;
  878. u8 dev_par;
  879. u8 bd_length;
  880. } __attribute__((packed)) hd;
  881. struct {
  882. u8 dens_code;
  883. u8 block_count[3];
  884. u8 reserved;
  885. u8 block_length[3];
  886. } __attribute__((packed)) bd;
  887. } __attribute__((packed)) gdth_modep_data;
  888. /* stack frame */
  889. typedef struct {
  890. unsigned long b[10]; /* 32/64 bit compiler ! */
  891. } __attribute__((packed)) gdth_stackframe;
  892. /* function prototyping */
  893. int gdth_show_info(struct seq_file *, struct Scsi_Host *);
  894. int gdth_set_info(struct Scsi_Host *, char *, int);
  895. #endif