fdomain.h 5.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #define FDOMAIN_REGION_SIZE 0x10
  3. #define FDOMAIN_BIOS_SIZE 0x2000
  4. enum {
  5. in_arbitration = 0x02,
  6. in_selection = 0x04,
  7. in_other = 0x08,
  8. disconnect = 0x10,
  9. aborted = 0x20,
  10. sent_ident = 0x40,
  11. };
  12. /* (@) = not present on TMC1800, (#) = not present on TMC1800 and TMC18C50 */
  13. #define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
  14. #define REG_BSTAT 1 /* R: SCSI Bus Status */
  15. #define BSTAT_BSY BIT(0) /* Busy */
  16. #define BSTAT_MSG BIT(1) /* Message */
  17. #define BSTAT_IO BIT(2) /* Input/Output */
  18. #define BSTAT_CMD BIT(3) /* Command/Data */
  19. #define BSTAT_REQ BIT(4) /* Request and Not Ack */
  20. #define BSTAT_SEL BIT(5) /* Select */
  21. #define BSTAT_ACK BIT(6) /* Acknowledge and Request */
  22. #define BSTAT_ATN BIT(7) /* Attention */
  23. #define REG_BCTL 1 /* W: SCSI Bus Control */
  24. #define BCTL_RST BIT(0) /* Bus Reset */
  25. #define BCTL_SEL BIT(1) /* Select */
  26. #define BCTL_BSY BIT(2) /* Busy */
  27. #define BCTL_ATN BIT(3) /* Attention */
  28. #define BCTL_IO BIT(4) /* Input/Output */
  29. #define BCTL_CMD BIT(5) /* Command/Data */
  30. #define BCTL_MSG BIT(6) /* Message */
  31. #define BCTL_BUSEN BIT(7) /* Enable bus drivers */
  32. #define REG_ASTAT 2 /* R: Adapter Status 1 */
  33. #define ASTAT_IRQ BIT(0) /* Interrupt active */
  34. #define ASTAT_ARB BIT(1) /* Arbitration complete */
  35. #define ASTAT_PARERR BIT(2) /* Parity error */
  36. #define ASTAT_RST BIT(3) /* SCSI reset occurred */
  37. #define ASTAT_FIFODIR BIT(4) /* FIFO direction */
  38. #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
  39. #define ASTAT_PAREN BIT(6) /* Parity enabled */
  40. #define ASTAT_BUSEN BIT(7) /* Bus drivers enabled */
  41. #define REG_ICTL 2 /* W: Interrupt Control */
  42. #define ICTL_FIFO_MASK 0x0f /* FIFO threshold, 1/16 FIFO size */
  43. #define ICTL_FIFO BIT(4) /* Int. on FIFO count */
  44. #define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
  45. #define ICTL_SEL BIT(6) /* Int. on SCSI Select */
  46. #define ICTL_REQ BIT(7) /* Int. on SCSI Request */
  47. #define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
  48. #define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */
  49. #define FSTAT_INOTEMPTY BIT(1) /* Input FIFO not empty */
  50. #define FSTAT_NOTEMPTY BIT(2) /* Main FIFO not empty */
  51. #define FSTAT_NOTFULL BIT(3) /* Main FIFO not full */
  52. #define REG_MCTL 3 /* W: SCSI Data Mode Control */
  53. #define MCTL_ACK_MASK 0x0f /* Acknowledge period */
  54. #define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */
  55. #define MCTL_TARGET BIT(5) /* Enable target mode */
  56. #define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */
  57. #define MCTL_SYNC BIT(7) /* Enable Synchronous */
  58. #define REG_INTCOND 4 /* R: Interrupt Condition - (@) */
  59. #define IRQ_FIFO BIT(1) /* FIFO interrupt */
  60. #define IRQ_REQ BIT(2) /* SCSI Request interrupt */
  61. #define IRQ_SEL BIT(3) /* SCSI Select interrupt */
  62. #define IRQ_ARB BIT(4) /* SCSI Arbitration interrupt */
  63. #define IRQ_RST BIT(5) /* SCSI Reset interrupt */
  64. #define IRQ_FORCED BIT(6) /* Forced interrupt */
  65. #define IRQ_TIMEOUT BIT(7) /* Bus timeout */
  66. #define REG_ACTL 4 /* W: Adapter Control 1 */
  67. #define ACTL_RESET BIT(0) /* Reset FIFO, parity, reset int. */
  68. #define ACTL_FIRQ BIT(1) /* Set Forced interrupt */
  69. #define ACTL_ARB BIT(2) /* Initiate Bus Arbitration */
  70. #define ACTL_PAREN BIT(3) /* Enable SCSI Parity */
  71. #define ACTL_IRQEN BIT(4) /* Enable interrupts */
  72. #define ACTL_CLRFIRQ BIT(5) /* Clear Forced interrupt */
  73. #define ACTL_FIFOWR BIT(6) /* FIFO Direction (1=write) */
  74. #define ACTL_FIFOEN BIT(7) /* Enable FIFO */
  75. #define REG_ID_LSB 5 /* R: ID Code (LSB) */
  76. #define REG_ACTL2 5 /* Adapter Control 2 - (@) */
  77. #define ACTL2_RAMOVRLY BIT(0) /* Enable RAM overlay */
  78. #define ACTL2_SLEEP BIT(7) /* Sleep mode */
  79. #define REG_ID_MSB 6 /* R: ID Code (MSB) */
  80. #define REG_LOOPBACK 7 /* R/W: Loopback */
  81. #define REG_SCSI_DATA_NOACK 8 /* R/W: SCSI Data (no ACK) */
  82. #define REG_ASTAT3 9 /* R: Adapter Status 3 */
  83. #define ASTAT3_ACTDEASS BIT(0) /* Active deassert enabled */
  84. #define ASTAT3_RAMOVRLY BIT(1) /* RAM overlay enabled */
  85. #define ASTAT3_TARGERR BIT(2) /* Target error */
  86. #define ASTAT3_IRQEN BIT(3) /* Interrupts enabled */
  87. #define ASTAT3_IRQMASK 0xf0 /* Enabled interrupts mask */
  88. #define REG_CFG1 10 /* R: Configuration Register 1 */
  89. #define CFG1_BUS BIT(0) /* 0 = ISA */
  90. #define CFG1_IRQ_MASK 0x0e /* IRQ jumpers */
  91. #define CFG1_IO_MASK 0x30 /* I/O base jumpers */
  92. #define CFG1_BIOS_MASK 0xc0 /* BIOS base jumpers */
  93. #define REG_CFG2 11 /* R/W: Configuration Register 2 (@) */
  94. #define CFG2_ROMDIS BIT(0) /* ROM disabled */
  95. #define CFG2_RAMDIS BIT(1) /* RAM disabled */
  96. #define CFG2_IRQEDGE BIT(2) /* Edge-triggered interrupts */
  97. #define CFG2_NOWS BIT(3) /* No wait states */
  98. #define CFG2_32BIT BIT(7) /* 32-bit mode */
  99. #define REG_FIFO 12 /* R/W: FIFO */
  100. #define REG_FIFO_COUNT 14 /* R: FIFO Data Count */
  101. #ifdef CONFIG_PM_SLEEP
  102. static const struct dev_pm_ops __maybe_unused fdomain_pm_ops;
  103. #define FDOMAIN_PM_OPS (&fdomain_pm_ops)
  104. #else
  105. #define FDOMAIN_PM_OPS NULL
  106. #endif /* CONFIG_PM_SLEEP */
  107. struct Scsi_Host *fdomain_create(int base, int irq, int this_id,
  108. struct device *dev);
  109. int fdomain_destroy(struct Scsi_Host *sh);