esp_scsi.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* esp_scsi.h: Defines and structures for the ESP driver.
  3. *
  4. * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
  5. */
  6. #ifndef _ESP_SCSI_H
  7. #define _ESP_SCSI_H
  8. /* Access Description Offset */
  9. #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
  10. #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
  11. #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */
  12. #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */
  13. #define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */
  14. #define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */
  15. #define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */
  16. #define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */
  17. #define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */
  18. #define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */
  19. #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */
  20. #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
  21. #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */
  22. #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */
  23. #define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
  24. #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */
  25. #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */
  26. #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */
  27. #define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */
  28. #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */
  29. #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
  30. #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
  31. #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */
  32. #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
  33. #define SBUS_ESP_REG_SIZE 0x40UL
  34. /* Bitfield meanings for the above registers. */
  35. /* ESP config reg 1, read-write, found on all ESP chips */
  36. #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
  37. #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
  38. #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
  39. #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
  40. #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
  41. #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
  42. /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
  43. #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
  44. #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
  45. #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
  46. #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
  47. #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
  48. #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
  49. #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
  50. #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
  51. #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */
  52. #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
  53. #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
  54. #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
  55. #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
  56. /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
  57. #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
  58. #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
  59. #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
  60. #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
  61. #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
  62. #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
  63. #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
  64. #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
  65. #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
  66. #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
  67. #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
  68. #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
  69. #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
  70. #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
  71. #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
  72. #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
  73. /* ESP config register 4 read-write */
  74. #define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */
  75. #define ESP_CONGIG4_TEST 0x02 /* Transfer counter test mode (fsc) */
  76. #define ESP_CONFIG4_RADE 0x04 /* Active negation (am53c974/fsc) */
  77. #define ESP_CONFIG4_RAE 0x08 /* Act. negation REQ/ACK (am53c974) */
  78. #define ESP_CONFIG4_PWD 0x20 /* Reduced power feature (am53c974) */
  79. #define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 (am53c974) */
  80. #define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 (am53c974) */
  81. #define ESP_CONFIG_GE_12NS (0)
  82. #define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1)
  83. #define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0)
  84. #define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1)
  85. /* ESP command register read-write */
  86. /* Group 1 commands: These may be sent at any point in time to the ESP
  87. * chip. None of them can generate interrupts 'cept
  88. * the "SCSI bus reset" command if you have not disabled
  89. * SCSI reset interrupts in the config1 ESP register.
  90. */
  91. #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
  92. #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
  93. #define ESP_CMD_RC 0x02 /* Chip reset */
  94. #define ESP_CMD_RS 0x03 /* SCSI bus reset */
  95. /* Group 2 commands: ESP must be an initiator and connected to a target
  96. * for these commands to work.
  97. */
  98. #define ESP_CMD_TI 0x10 /* Transfer Information */
  99. #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
  100. #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
  101. #define ESP_CMD_TPAD 0x18 /* Transfer Pad */
  102. #define ESP_CMD_SATN 0x1a /* Set ATN */
  103. #define ESP_CMD_RATN 0x1b /* De-assert ATN */
  104. /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
  105. * to a target as the initiator for these commands to work.
  106. */
  107. #define ESP_CMD_SMSG 0x20 /* Send message */
  108. #define ESP_CMD_SSTAT 0x21 /* Send status */
  109. #define ESP_CMD_SDATA 0x22 /* Send data */
  110. #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
  111. #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
  112. #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
  113. #define ESP_CMD_DCNCT 0x27 /* Disconnect */
  114. #define ESP_CMD_RMSG 0x28 /* Receive Message */
  115. #define ESP_CMD_RCMD 0x29 /* Receive Command */
  116. #define ESP_CMD_RDATA 0x2a /* Receive Data */
  117. #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
  118. /* Group 4 commands: The ESP must be in the disconnected state and must
  119. * not be connected to any targets as initiator for
  120. * these commands to work.
  121. */
  122. #define ESP_CMD_RSEL 0x40 /* Reselect */
  123. #define ESP_CMD_SEL 0x41 /* Select w/o ATN */
  124. #define ESP_CMD_SELA 0x42 /* Select w/ATN */
  125. #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
  126. #define ESP_CMD_ESEL 0x44 /* Enable selection */
  127. #define ESP_CMD_DSEL 0x45 /* Disable selections */
  128. #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
  129. #define ESP_CMD_RSEL3 0x47 /* Reselect3 */
  130. /* This bit enables the ESP's DMA on the SBus */
  131. #define ESP_CMD_DMA 0x80 /* Do DMA? */
  132. /* ESP status register read-only */
  133. #define ESP_STAT_PIO 0x01 /* IO phase bit */
  134. #define ESP_STAT_PCD 0x02 /* CD phase bit */
  135. #define ESP_STAT_PMSG 0x04 /* MSG phase bit */
  136. #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
  137. #define ESP_STAT_TDONE 0x08 /* Transfer Completed */
  138. #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
  139. #define ESP_STAT_PERR 0x20 /* Parity error */
  140. #define ESP_STAT_SPAM 0x40 /* Real bad error */
  141. /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
  142. * bit on other revs of the ESP.
  143. */
  144. #define ESP_STAT_INTR 0x80 /* Interrupt */
  145. /* The status register can be masked with ESP_STAT_PMASK and compared
  146. * with the following values to determine the current phase the ESP
  147. * (at least thinks it) is in. For our purposes we also add our own
  148. * software 'done' bit for our phase management engine.
  149. */
  150. #define ESP_DOP (0) /* Data Out */
  151. #define ESP_DIP (ESP_STAT_PIO) /* Data In */
  152. #define ESP_CMDP (ESP_STAT_PCD) /* Command */
  153. #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
  154. #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
  155. #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
  156. /* HME only: status 2 register */
  157. #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
  158. #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
  159. #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
  160. #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
  161. #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
  162. #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
  163. #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
  164. #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
  165. /* ESP interrupt register read-only */
  166. #define ESP_INTR_S 0x01 /* Select w/o ATN */
  167. #define ESP_INTR_SATN 0x02 /* Select w/ATN */
  168. #define ESP_INTR_RSEL 0x04 /* Reselected */
  169. #define ESP_INTR_FDONE 0x08 /* Function done */
  170. #define ESP_INTR_BSERV 0x10 /* Bus service */
  171. #define ESP_INTR_DC 0x20 /* Disconnect */
  172. #define ESP_INTR_IC 0x40 /* Illegal command given */
  173. #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
  174. /* ESP sequence step register read-only */
  175. #define ESP_STEP_VBITS 0x07 /* Valid bits */
  176. #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
  177. #define ESP_STEP_SID 0x01 /* One msg byte sent */
  178. #define ESP_STEP_NCMD 0x02 /* Was not in command phase */
  179. #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
  180. * bytes to be lost
  181. */
  182. #define ESP_STEP_FINI4 0x04 /* Command was sent ok */
  183. /* Ho hum, some ESP's set the step register to this as well... */
  184. #define ESP_STEP_FINI5 0x05
  185. #define ESP_STEP_FINI6 0x06
  186. #define ESP_STEP_FINI7 0x07
  187. /* ESP chip-test register read-write */
  188. #define ESP_TEST_TARG 0x01 /* Target test mode */
  189. #define ESP_TEST_INI 0x02 /* Initiator test mode */
  190. #define ESP_TEST_TS 0x04 /* Tristate test mode */
  191. /* ESP unique ID register read-only, found on fas236+fas100a only */
  192. #define ESP_UID_FAM 0xf8 /* ESP family bitmask */
  193. #define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3)
  194. /* Values for the ESP family bits */
  195. #define ESP_UID_F100A 0x00 /* ESP FAS100A */
  196. #define ESP_UID_F236 0x02 /* ESP FAS236 */
  197. #define ESP_UID_HME 0x0a /* FAS HME */
  198. #define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */
  199. /* ESP fifo flags register read-only */
  200. /* Note that the following implies a 16 byte FIFO on the ESP. */
  201. #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
  202. #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
  203. #define ESP_FF_SSTEP 0xe0 /* Sequence step */
  204. /* ESP clock conversion factor register write-only */
  205. #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
  206. #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
  207. #define ESP_CCF_F2 0x02 /* 10MHz */
  208. #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
  209. #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
  210. #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
  211. #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
  212. #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
  213. /* HME only... */
  214. #define ESP_BUSID_RESELID 0x10
  215. #define ESP_BUSID_CTR32BIT 0x40
  216. #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */
  217. #define ESP_TIMEO_CONST 8192
  218. #define ESP_NEG_DEFP(mhz, cfact) \
  219. ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
  220. #define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000))
  221. #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
  222. /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
  223. * input clock rates we try to do 10mb/s although I don't think a transfer can
  224. * even run that fast with an ESP even with DMA2 scatter gather pipelining.
  225. */
  226. #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
  227. #define SYNC_DEFP_FAST 0x19 /* 10mb/s */
  228. struct esp_cmd_priv {
  229. int num_sg;
  230. int cur_residue;
  231. struct scatterlist *prv_sg;
  232. struct scatterlist *cur_sg;
  233. int tot_residue;
  234. };
  235. #define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp))
  236. /* NOTE: this enum is ordered based on chip features! */
  237. enum esp_rev {
  238. ESP100, /* NCR53C90 - very broken */
  239. ESP100A, /* NCR53C90A */
  240. ESP236,
  241. FAS236,
  242. PCSCSI, /* AM53c974 */
  243. FSC, /* NCR/Symbios Logic 53CF9x-2 */
  244. FAS100A,
  245. FAST,
  246. FASHME,
  247. };
  248. struct esp_cmd_entry {
  249. struct list_head list;
  250. struct scsi_cmnd *cmd;
  251. unsigned int saved_cur_residue;
  252. struct scatterlist *saved_prv_sg;
  253. struct scatterlist *saved_cur_sg;
  254. unsigned int saved_tot_residue;
  255. u8 flags;
  256. #define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */
  257. #define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */
  258. #define ESP_CMD_FLAG_RESIDUAL 0x08 /* AM53c974 BLAST residual */
  259. u8 tag[2];
  260. u8 orig_tag[2];
  261. u8 status;
  262. u8 message;
  263. unsigned char *sense_ptr;
  264. unsigned char *saved_sense_ptr;
  265. dma_addr_t sense_dma;
  266. struct completion *eh_done;
  267. };
  268. #define ESP_DEFAULT_TAGS 16
  269. #define ESP_MAX_TARGET 16
  270. #define ESP_MAX_LUN 8
  271. #define ESP_MAX_TAG 256
  272. struct esp_lun_data {
  273. struct esp_cmd_entry *non_tagged_cmd;
  274. int num_tagged;
  275. int hold;
  276. struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG];
  277. };
  278. struct esp_target_data {
  279. /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which
  280. * match the currently negotiated settings for this target. The SCSI
  281. * protocol values are maintained in spi_{offset,period,wide}(starget).
  282. */
  283. u8 esp_period;
  284. u8 esp_offset;
  285. u8 esp_config3;
  286. u8 flags;
  287. #define ESP_TGT_WIDE 0x01
  288. #define ESP_TGT_DISCONNECT 0x02
  289. #define ESP_TGT_NEGO_WIDE 0x04
  290. #define ESP_TGT_NEGO_SYNC 0x08
  291. #define ESP_TGT_CHECK_NEGO 0x40
  292. #define ESP_TGT_BROKEN 0x80
  293. /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this
  294. * device we will try to negotiate the following parameters.
  295. */
  296. u8 nego_goal_period;
  297. u8 nego_goal_offset;
  298. u8 nego_goal_width;
  299. u8 nego_goal_tags;
  300. struct scsi_target *starget;
  301. };
  302. struct esp_event_ent {
  303. u8 type;
  304. #define ESP_EVENT_TYPE_EVENT 0x01
  305. #define ESP_EVENT_TYPE_CMD 0x02
  306. u8 val;
  307. u8 sreg;
  308. u8 seqreg;
  309. u8 sreg2;
  310. u8 ireg;
  311. u8 select_state;
  312. u8 event;
  313. u8 __pad;
  314. };
  315. struct esp;
  316. struct esp_driver_ops {
  317. /* Read and write the ESP 8-bit registers. On some
  318. * applications of the ESP chip the registers are at 4-byte
  319. * instead of 1-byte intervals.
  320. */
  321. void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg);
  322. u8 (*esp_read8)(struct esp *esp, unsigned long reg);
  323. /* Return non-zero if there is an IRQ pending. Usually this
  324. * status bit lives in the DMA controller sitting in front of
  325. * the ESP. This has to be accurate or else the ESP interrupt
  326. * handler will not run.
  327. */
  328. int (*irq_pending)(struct esp *esp);
  329. /* Return the maximum allowable size of a DMA transfer for a
  330. * given buffer.
  331. */
  332. u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr,
  333. u32 dma_len);
  334. /* Reset the DMA engine entirely. On return, ESP interrupts
  335. * should be enabled. Often the interrupt enabling is
  336. * controlled in the DMA engine.
  337. */
  338. void (*reset_dma)(struct esp *esp);
  339. /* Drain any pending DMA in the DMA engine after a transfer.
  340. * This is for writes to memory.
  341. */
  342. void (*dma_drain)(struct esp *esp);
  343. /* Invalidate the DMA engine after a DMA transfer. */
  344. void (*dma_invalidate)(struct esp *esp);
  345. /* Setup an ESP command that will use a DMA transfer.
  346. * The 'esp_count' specifies what transfer length should be
  347. * programmed into the ESP transfer counter registers, whereas
  348. * the 'dma_count' is the length that should be programmed into
  349. * the DMA controller. Usually they are the same. If 'write'
  350. * is non-zero, this transfer is a write into memory. 'cmd'
  351. * holds the ESP command that should be issued by calling
  352. * scsi_esp_cmd() at the appropriate time while programming
  353. * the DMA hardware.
  354. */
  355. void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count,
  356. u32 dma_count, int write, u8 cmd);
  357. /* Return non-zero if the DMA engine is reporting an error
  358. * currently.
  359. */
  360. int (*dma_error)(struct esp *esp);
  361. };
  362. #define ESP_MAX_MSG_SZ 8
  363. #define ESP_EVENT_LOG_SZ 32
  364. #define ESP_QUICKIRQ_LIMIT 100
  365. #define ESP_RESELECT_TAG_LIMIT 2500
  366. struct esp {
  367. void __iomem *regs;
  368. void __iomem *dma_regs;
  369. const struct esp_driver_ops *ops;
  370. struct Scsi_Host *host;
  371. struct device *dev;
  372. struct esp_cmd_entry *active_cmd;
  373. struct list_head queued_cmds;
  374. struct list_head active_cmds;
  375. u8 *command_block;
  376. dma_addr_t command_block_dma;
  377. unsigned int data_dma_len;
  378. /* The following are used to determine the cause of an IRQ. Upon every
  379. * IRQ entry we synchronize these with the hardware registers.
  380. */
  381. u8 sreg;
  382. u8 seqreg;
  383. u8 sreg2;
  384. u8 ireg;
  385. u32 prev_hme_dmacsr;
  386. u8 prev_soff;
  387. u8 prev_stp;
  388. u8 prev_cfg3;
  389. u8 num_tags;
  390. struct list_head esp_cmd_pool;
  391. struct esp_target_data target[ESP_MAX_TARGET];
  392. int fifo_cnt;
  393. u8 fifo[16];
  394. struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ];
  395. int esp_event_cur;
  396. u8 msg_out[ESP_MAX_MSG_SZ];
  397. int msg_out_len;
  398. u8 msg_in[ESP_MAX_MSG_SZ];
  399. int msg_in_len;
  400. u8 bursts;
  401. u8 config1;
  402. u8 config2;
  403. u8 config4;
  404. u8 scsi_id;
  405. u32 scsi_id_mask;
  406. enum esp_rev rev;
  407. u32 flags;
  408. #define ESP_FLAG_DIFFERENTIAL 0x00000001
  409. #define ESP_FLAG_RESETTING 0x00000002
  410. #define ESP_FLAG_WIDE_CAPABLE 0x00000008
  411. #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
  412. #define ESP_FLAG_DISABLE_SYNC 0x00000020
  413. #define ESP_FLAG_USE_FIFO 0x00000040
  414. #define ESP_FLAG_NO_DMA_MAP 0x00000080
  415. u8 select_state;
  416. #define ESP_SELECT_NONE 0x00 /* Not selecting */
  417. #define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */
  418. #define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */
  419. /* When we are not selecting, we are expecting an event. */
  420. u8 event;
  421. #define ESP_EVENT_NONE 0x00
  422. #define ESP_EVENT_CMD_START 0x01
  423. #define ESP_EVENT_CMD_DONE 0x02
  424. #define ESP_EVENT_DATA_IN 0x03
  425. #define ESP_EVENT_DATA_OUT 0x04
  426. #define ESP_EVENT_DATA_DONE 0x05
  427. #define ESP_EVENT_MSGIN 0x06
  428. #define ESP_EVENT_MSGIN_MORE 0x07
  429. #define ESP_EVENT_MSGIN_DONE 0x08
  430. #define ESP_EVENT_MSGOUT 0x09
  431. #define ESP_EVENT_MSGOUT_DONE 0x0a
  432. #define ESP_EVENT_STATUS 0x0b
  433. #define ESP_EVENT_FREE_BUS 0x0c
  434. #define ESP_EVENT_CHECK_PHASE 0x0d
  435. #define ESP_EVENT_RESET 0x10
  436. /* Probed in esp_get_clock_params() */
  437. u32 cfact;
  438. u32 cfreq;
  439. u32 ccycle;
  440. u32 ctick;
  441. u32 neg_defp;
  442. u32 sync_defp;
  443. /* Computed in esp_reset_esp() */
  444. u32 max_period;
  445. u32 min_period;
  446. u32 radelay;
  447. /* ESP_CMD_SELAS command state */
  448. u8 *cmd_bytes_ptr;
  449. int cmd_bytes_left;
  450. struct completion *eh_reset;
  451. void *dma;
  452. int dmarev;
  453. /* These are used by esp_send_pio_cmd() */
  454. u8 __iomem *fifo_reg;
  455. int send_cmd_error;
  456. u32 send_cmd_residual;
  457. };
  458. /* A front-end driver for the ESP chip should do the following in
  459. * it's device probe routine:
  460. * 1) Allocate the host and private area using scsi_host_alloc()
  461. * with size 'sizeof(struct esp)'. The first argument to
  462. * scsi_host_alloc() should be &scsi_esp_template.
  463. * 2) Set host->max_id as appropriate.
  464. * 3) Set esp->host to the scsi_host itself, and esp->dev
  465. * to the device object pointer.
  466. * 4) Hook up esp->ops to the front-end implementation.
  467. * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE
  468. * in esp->flags.
  469. * 6) Map the DMA and ESP chip registers.
  470. * 7) DMA map the ESP command block, store the DMA address
  471. * in esp->command_block_dma.
  472. * 8) Register the scsi_esp_intr() interrupt handler.
  473. * 9) Probe for and provide the following chip properties:
  474. * esp->scsi_id (assign to esp->host->this_id too)
  475. * esp->scsi_id_mask
  476. * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL
  477. * esp->cfreq
  478. * DMA burst bit mask in esp->bursts, if necessary
  479. * 10) Perform any actions necessary before the ESP device can
  480. * be programmed for the first time. On some configs, for
  481. * example, the DMA engine has to be reset before ESP can
  482. * be programmed.
  483. * 11) If necessary, call dev_set_drvdata() as needed.
  484. * 12) Call scsi_esp_register() with prepared 'esp' structure.
  485. * 13) Check scsi_esp_register() return value, release all resources
  486. * if an error was returned.
  487. */
  488. extern struct scsi_host_template scsi_esp_template;
  489. extern int scsi_esp_register(struct esp *);
  490. extern void scsi_esp_unregister(struct esp *);
  491. extern irqreturn_t scsi_esp_intr(int, void *);
  492. extern void scsi_esp_cmd(struct esp *, u8);
  493. extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count,
  494. u32 dma_count, int write, u8 cmd);
  495. #endif /* !(_ESP_SCSI_H) */