csio_hw.h 20 KB

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  1. /*
  2. * This file is part of the Chelsio FCoE driver for Linux.
  3. *
  4. * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #ifndef __CSIO_HW_H__
  35. #define __CSIO_HW_H__
  36. #include <linux/kernel.h>
  37. #include <linux/pci.h>
  38. #include <linux/device.h>
  39. #include <linux/workqueue.h>
  40. #include <linux/compiler.h>
  41. #include <linux/cdev.h>
  42. #include <linux/list.h>
  43. #include <linux/mempool.h>
  44. #include <linux/io.h>
  45. #include <linux/spinlock_types.h>
  46. #include <scsi/scsi_device.h>
  47. #include <scsi/scsi_transport_fc.h>
  48. #include "t4_hw.h"
  49. #include "csio_hw_chip.h"
  50. #include "csio_wr.h"
  51. #include "csio_mb.h"
  52. #include "csio_scsi.h"
  53. #include "csio_defs.h"
  54. #include "t4_regs.h"
  55. #include "t4_msg.h"
  56. /*
  57. * An error value used by host. Should not clash with FW defined return values.
  58. */
  59. #define FW_HOSTERROR 255
  60. #define CSIO_HW_NAME "Chelsio FCoE Adapter"
  61. #define CSIO_MAX_PFN 8
  62. #define CSIO_MAX_PPORTS 4
  63. #define CSIO_MAX_LUN 0xFFFF
  64. #define CSIO_MAX_QUEUE 2048
  65. #define CSIO_MAX_CMD_PER_LUN 32
  66. #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
  67. #define CSIO_MAX_SECTOR_SIZE 128
  68. #define CSIO_MIN_T6_FW 0x01102D00 /* FW 1.16.45.0 */
  69. /* Interrupts */
  70. #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
  71. * (Forward intr iq + fw iq) */
  72. #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
  73. #define CSIO_MAX_SCSI_CPU 128
  74. #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
  75. #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
  76. /* Queues */
  77. enum {
  78. CSIO_INTR_WRSIZE = 128,
  79. CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
  80. CSIO_FWEVT_WRSIZE = 128,
  81. CSIO_FWEVT_IQLEN = 128,
  82. CSIO_FWEVT_FLBUFS = 64,
  83. CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
  84. CSIO_HW_NIQ = 1,
  85. CSIO_HW_NFLQ = 1,
  86. CSIO_HW_NEQ = 1,
  87. CSIO_HW_NINTXQ = 1,
  88. };
  89. struct csio_msix_entries {
  90. void *dev_id; /* Priv object associated w/ this msix*/
  91. char desc[24]; /* Description of this vector */
  92. };
  93. struct csio_scsi_qset {
  94. int iq_idx; /* Ingress index */
  95. int eq_idx; /* Egress index */
  96. uint32_t intr_idx; /* MSIX Vector index */
  97. };
  98. struct csio_scsi_cpu_info {
  99. int16_t max_cpus;
  100. };
  101. extern int csio_dbg_level;
  102. extern unsigned int csio_port_mask;
  103. extern int csio_msi;
  104. #define CSIO_VENDOR_ID 0x1425
  105. #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
  106. #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
  107. #define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
  108. EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
  109. PM_TX_F | PM_RX_F | ULP_RX_F | \
  110. CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
  111. /*
  112. * Hard parameters used to initialize the card in the absence of a
  113. * configuration file.
  114. */
  115. enum {
  116. /* General */
  117. CSIO_SGE_DBFIFO_INT_THRESH = 10,
  118. CSIO_SGE_RX_DMA_OFFSET = 2,
  119. CSIO_SGE_FLBUF_SIZE1 = 65536,
  120. CSIO_SGE_FLBUF_SIZE2 = 1536,
  121. CSIO_SGE_FLBUF_SIZE3 = 9024,
  122. CSIO_SGE_FLBUF_SIZE4 = 9216,
  123. CSIO_SGE_FLBUF_SIZE5 = 2048,
  124. CSIO_SGE_FLBUF_SIZE6 = 128,
  125. CSIO_SGE_FLBUF_SIZE7 = 8192,
  126. CSIO_SGE_FLBUF_SIZE8 = 16384,
  127. CSIO_SGE_TIMER_VAL_0 = 5,
  128. CSIO_SGE_TIMER_VAL_1 = 10,
  129. CSIO_SGE_TIMER_VAL_2 = 20,
  130. CSIO_SGE_TIMER_VAL_3 = 50,
  131. CSIO_SGE_TIMER_VAL_4 = 100,
  132. CSIO_SGE_TIMER_VAL_5 = 200,
  133. CSIO_SGE_INT_CNT_VAL_0 = 1,
  134. CSIO_SGE_INT_CNT_VAL_1 = 4,
  135. CSIO_SGE_INT_CNT_VAL_2 = 8,
  136. CSIO_SGE_INT_CNT_VAL_3 = 16,
  137. };
  138. /* Slowpath events */
  139. enum csio_evt {
  140. CSIO_EVT_FW = 0, /* FW event */
  141. CSIO_EVT_MBX, /* MBX event */
  142. CSIO_EVT_SCN, /* State change notification */
  143. CSIO_EVT_DEV_LOSS, /* Device loss event */
  144. CSIO_EVT_MAX, /* Max supported event */
  145. };
  146. #define CSIO_EVT_MSG_SIZE 512
  147. #define CSIO_EVTQ_SIZE 512
  148. /* Event msg */
  149. struct csio_evt_msg {
  150. struct list_head list; /* evt queue*/
  151. enum csio_evt type;
  152. uint8_t data[CSIO_EVT_MSG_SIZE];
  153. };
  154. enum {
  155. SERNUM_LEN = 16, /* Serial # length */
  156. EC_LEN = 16, /* E/C length */
  157. ID_LEN = 16, /* ID length */
  158. };
  159. enum {
  160. SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
  161. };
  162. /* serial flash and firmware constants */
  163. enum {
  164. SF_ATTEMPTS = 10, /* max retries for SF operations */
  165. /* flash command opcodes */
  166. SF_PROG_PAGE = 2, /* program page */
  167. SF_WR_DISABLE = 4, /* disable writes */
  168. SF_RD_STATUS = 5, /* read status register */
  169. SF_WR_ENABLE = 6, /* enable writes */
  170. SF_RD_DATA_FAST = 0xb, /* read flash */
  171. SF_RD_ID = 0x9f, /* read ID */
  172. SF_ERASE_SECTOR = 0xd8, /* erase sector */
  173. };
  174. /* Management module */
  175. enum {
  176. CSIO_MGMT_EQ_WRSIZE = 512,
  177. CSIO_MGMT_IQ_WRSIZE = 128,
  178. CSIO_MGMT_EQLEN = 64,
  179. CSIO_MGMT_IQLEN = 64,
  180. };
  181. #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
  182. #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
  183. /* mgmt module stats */
  184. struct csio_mgmtm_stats {
  185. uint32_t n_abort_req; /* Total abort request */
  186. uint32_t n_abort_rsp; /* Total abort response */
  187. uint32_t n_close_req; /* Total close request */
  188. uint32_t n_close_rsp; /* Total close response */
  189. uint32_t n_err; /* Total Errors */
  190. uint32_t n_drop; /* Total request dropped */
  191. uint32_t n_active; /* Count of active_q */
  192. uint32_t n_cbfn; /* Count of cbfn_q */
  193. };
  194. /* MGMT module */
  195. struct csio_mgmtm {
  196. struct csio_hw *hw; /* Pointer to HW moduel */
  197. int eq_idx; /* Egress queue index */
  198. int iq_idx; /* Ingress queue index */
  199. int msi_vec; /* MSI vector */
  200. struct list_head active_q; /* Outstanding ELS/CT */
  201. struct list_head abort_q; /* Outstanding abort req */
  202. struct list_head cbfn_q; /* Completion queue */
  203. struct list_head mgmt_req_freelist; /* Free poll of reqs */
  204. /* ELSCT request freelist*/
  205. struct timer_list mgmt_timer; /* MGMT timer */
  206. struct csio_mgmtm_stats stats; /* ELS/CT stats */
  207. };
  208. struct csio_adap_desc {
  209. char model_no[16];
  210. char description[32];
  211. };
  212. struct pci_params {
  213. uint16_t vendor_id;
  214. uint16_t device_id;
  215. int vpd_cap_addr;
  216. uint16_t speed;
  217. uint8_t width;
  218. };
  219. /* User configurable hw parameters */
  220. struct csio_hw_params {
  221. uint32_t sf_size; /* serial flash
  222. * size in bytes
  223. */
  224. uint32_t sf_nsec; /* # of flash sectors */
  225. struct pci_params pci;
  226. uint32_t log_level; /* Module-level for
  227. * debug log.
  228. */
  229. };
  230. struct csio_vpd {
  231. uint32_t cclk;
  232. uint8_t ec[EC_LEN + 1];
  233. uint8_t sn[SERNUM_LEN + 1];
  234. uint8_t id[ID_LEN + 1];
  235. };
  236. /* Firmware Port Capabilities types. */
  237. typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
  238. typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
  239. enum fw_caps {
  240. FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
  241. FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
  242. FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
  243. };
  244. enum cc_pause {
  245. PAUSE_RX = 1 << 0,
  246. PAUSE_TX = 1 << 1,
  247. PAUSE_AUTONEG = 1 << 2
  248. };
  249. enum cc_fec {
  250. FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
  251. FEC_RS = 1 << 1, /* Reed-Solomon */
  252. FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
  253. };
  254. struct link_config {
  255. fw_port_cap32_t pcaps; /* link capabilities */
  256. fw_port_cap32_t def_acaps; /* default advertised capabilities */
  257. fw_port_cap32_t acaps; /* advertised capabilities */
  258. fw_port_cap32_t lpacaps; /* peer advertised capabilities */
  259. fw_port_cap32_t speed_caps; /* speed(s) user has requested */
  260. unsigned int speed; /* actual link speed (Mb/s) */
  261. enum cc_pause requested_fc; /* flow control user has requested */
  262. enum cc_pause fc; /* actual link flow control */
  263. enum cc_fec requested_fec; /* Forward Error Correction: */
  264. enum cc_fec fec; /* requested and actual in use */
  265. unsigned char autoneg; /* autonegotiating? */
  266. unsigned char link_ok; /* link up? */
  267. unsigned char link_down_rc; /* link down reason */
  268. };
  269. #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
  270. #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
  271. FW_PORT_CAP32_ANEG)
  272. /* Enable or disable autonegotiation. */
  273. #define AUTONEG_DISABLE 0x00
  274. #define AUTONEG_ENABLE 0x01
  275. struct csio_pport {
  276. uint16_t pcap;
  277. uint16_t acap;
  278. uint8_t portid;
  279. uint8_t link_status;
  280. uint16_t link_speed;
  281. uint8_t mac[6];
  282. uint8_t mod_type;
  283. uint8_t rsvd1;
  284. uint8_t rsvd2;
  285. uint8_t rsvd3;
  286. struct link_config link_cfg;
  287. };
  288. /* fcoe resource information */
  289. struct csio_fcoe_res_info {
  290. uint16_t e_d_tov;
  291. uint16_t r_a_tov_seq;
  292. uint16_t r_a_tov_els;
  293. uint16_t r_r_tov;
  294. uint32_t max_xchgs;
  295. uint32_t max_ssns;
  296. uint32_t used_xchgs;
  297. uint32_t used_ssns;
  298. uint32_t max_fcfs;
  299. uint32_t max_vnps;
  300. uint32_t used_fcfs;
  301. uint32_t used_vnps;
  302. };
  303. /* HW State machine Events */
  304. enum csio_hw_ev {
  305. CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
  306. CSIO_HWE_INIT, /* Config done, start Init */
  307. CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
  308. CSIO_HWE_FATAL, /* Fatal error during initialization */
  309. CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
  310. CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
  311. CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
  312. CSIO_HWE_QUIESCED, /* HBA quiesced */
  313. CSIO_HWE_HBA_RESET, /* HBA reset requested */
  314. CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
  315. CSIO_HWE_FW_DLOAD, /* FW download requested */
  316. CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
  317. CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
  318. CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
  319. CSIO_HWE_MAX, /* Max HW event */
  320. };
  321. /* hw stats */
  322. struct csio_hw_stats {
  323. uint32_t n_evt_activeq; /* Number of event in active Q */
  324. uint32_t n_evt_freeq; /* Number of event in free Q */
  325. uint32_t n_evt_drop; /* Number of event droped */
  326. uint32_t n_evt_unexp; /* Number of unexpected events */
  327. uint32_t n_pcich_offline;/* Number of pci channel offline */
  328. uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
  329. uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
  330. uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
  331. uint32_t n_cpl_unexp; /* Number of unexpected cpl */
  332. uint32_t n_mbint_unexp; /* Number of unexpected mbox */
  333. /* interrupt */
  334. uint32_t n_plint_unexp; /* Number of unexpected PL */
  335. /* interrupt */
  336. uint32_t n_plint_cnt; /* Number of PL interrupt */
  337. uint32_t n_int_stray; /* Number of stray interrupt */
  338. uint32_t n_err; /* Number of hw errors */
  339. uint32_t n_err_fatal; /* Number of fatal errors */
  340. uint32_t n_err_nomem; /* Number of memory alloc failure */
  341. uint32_t n_err_io; /* Number of IO failure */
  342. enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
  343. uint64_t n_reset_start; /* Start time after the reset */
  344. uint32_t rsvd1;
  345. };
  346. /* Defines for hw->flags */
  347. #define CSIO_HWF_MASTER 0x00000001 /* This is the Master
  348. * function for the
  349. * card.
  350. */
  351. #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
  352. * enable bit set?
  353. */
  354. #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
  355. #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
  356. * allocated memory.
  357. */
  358. #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
  359. * allocated in FW.
  360. */
  361. #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
  362. #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
  363. * id cached */
  364. #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
  365. * FW events
  366. */
  367. #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
  368. * params
  369. */
  370. #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
  371. * enabled?
  372. */
  373. #define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400 /* Is PCIe relaxed
  374. * ordering enabled
  375. */
  376. #define csio_is_hw_intr_enabled(__hw) \
  377. ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
  378. #define csio_is_host_intr_enabled(__hw) \
  379. ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
  380. #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
  381. #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
  382. #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
  383. #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
  384. #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
  385. /* Defines for intr_mode */
  386. enum csio_intr_mode {
  387. CSIO_IM_NONE = 0,
  388. CSIO_IM_INTX = 1,
  389. CSIO_IM_MSI = 2,
  390. CSIO_IM_MSIX = 3,
  391. };
  392. /* Master HW structure: One per function */
  393. struct csio_hw {
  394. struct csio_sm sm; /* State machine: should
  395. * be the 1st member.
  396. */
  397. spinlock_t lock; /* Lock for hw */
  398. struct csio_scsim scsim; /* SCSI module*/
  399. struct csio_wrm wrm; /* Work request module*/
  400. struct pci_dev *pdev; /* PCI device */
  401. void __iomem *regstart; /* Virtual address of
  402. * register map
  403. */
  404. /* SCSI queue sets */
  405. uint32_t num_sqsets; /* Number of SCSI
  406. * queue sets */
  407. uint32_t num_scsi_msix_cpus; /* Number of CPUs that
  408. * will be used
  409. * for ingress
  410. * processing.
  411. */
  412. struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
  413. struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
  414. uint32_t evtflag; /* Event flag */
  415. uint32_t flags; /* HW flags */
  416. struct csio_mgmtm mgmtm; /* management module */
  417. struct csio_mbm mbm; /* Mailbox module */
  418. /* Lnodes */
  419. uint32_t num_lns; /* Number of lnodes */
  420. struct csio_lnode *rln; /* Root lnode */
  421. struct list_head sln_head; /* Sibling node list
  422. * list
  423. */
  424. int intr_iq_idx; /* Forward interrupt
  425. * queue.
  426. */
  427. int fwevt_iq_idx; /* FW evt queue */
  428. struct work_struct evtq_work; /* Worker thread for
  429. * HW events.
  430. */
  431. struct list_head evt_free_q; /* freelist of evt
  432. * elements
  433. */
  434. struct list_head evt_active_q; /* active evt queue*/
  435. /* board related info */
  436. char name[32];
  437. char hw_ver[16];
  438. char model_desc[32];
  439. char drv_version[32];
  440. char fwrev_str[32];
  441. uint32_t optrom_ver;
  442. uint32_t fwrev;
  443. uint32_t tp_vers;
  444. char chip_ver;
  445. uint16_t chip_id; /* Tells T4/T5 chip */
  446. enum csio_dev_state fw_state;
  447. struct csio_vpd vpd;
  448. uint8_t pfn; /* Physical Function
  449. * number
  450. */
  451. uint32_t port_vec; /* Port vector */
  452. uint8_t num_pports; /* Number of physical
  453. * ports.
  454. */
  455. uint8_t rst_retries; /* Reset retries */
  456. uint8_t cur_evt; /* current s/m evt */
  457. uint8_t prev_evt; /* Previous s/m evt */
  458. uint32_t dev_num; /* device number */
  459. struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
  460. struct csio_hw_params params; /* Hw parameters */
  461. struct dma_pool *scsi_dma_pool; /* DMA pool for SCSI */
  462. mempool_t *mb_mempool; /* Mailbox memory pool*/
  463. mempool_t *rnode_mempool; /* rnode memory pool */
  464. /* Interrupt */
  465. enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
  466. uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
  467. * index
  468. */
  469. uint32_t nondata_intr_idx; /* nondata MSIX/intr
  470. * idx
  471. */
  472. uint8_t cfg_neq; /* FW configured no of
  473. * egress queues
  474. */
  475. uint8_t cfg_niq; /* FW configured no of
  476. * iq queues.
  477. */
  478. struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
  479. struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
  480. * Operations
  481. */
  482. /* MSIX vectors */
  483. struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
  484. struct dentry *debugfs_root; /* Debug FS */
  485. struct csio_hw_stats stats; /* Hw statistics */
  486. };
  487. /* Register access macros */
  488. #define csio_reg(_b, _r) ((_b) + (_r))
  489. #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
  490. #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
  491. #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
  492. #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
  493. #define csio_wr_reg8(_h, _v, _r) writeb((_v), \
  494. csio_reg((_h)->regstart, (_r)))
  495. #define csio_wr_reg16(_h, _v, _r) writew((_v), \
  496. csio_reg((_h)->regstart, (_r)))
  497. #define csio_wr_reg32(_h, _v, _r) writel((_v), \
  498. csio_reg((_h)->regstart, (_r)))
  499. #define csio_wr_reg64(_h, _v, _r) writeq((_v), \
  500. csio_reg((_h)->regstart, (_r)))
  501. void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
  502. /* Core clocks <==> uSecs */
  503. static inline uint32_t
  504. csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
  505. {
  506. /* add Core Clock / 2 to round ticks to nearest uS */
  507. return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
  508. }
  509. static inline uint32_t
  510. csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
  511. {
  512. return (us * hw->vpd.cclk) / 1000;
  513. }
  514. /* Easy access macros */
  515. #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
  516. #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
  517. #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
  518. #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
  519. #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
  520. #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
  521. #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
  522. #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
  523. #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
  524. #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
  525. #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
  526. /* Printing/logging */
  527. #define CSIO_DEVID(__dev) ((__dev)->dev_num)
  528. #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
  529. #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
  530. #define csio_info(__hw, __fmt, ...) \
  531. dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
  532. #define csio_fatal(__hw, __fmt, ...) \
  533. dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
  534. #define csio_err(__hw, __fmt, ...) \
  535. dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
  536. #define csio_warn(__hw, __fmt, ...) \
  537. dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
  538. #ifdef __CSIO_DEBUG__
  539. #define csio_dbg(__hw, __fmt, ...) \
  540. csio_info((__hw), __fmt, ##__VA_ARGS__);
  541. #else
  542. #define csio_dbg(__hw, __fmt, ...)
  543. #endif
  544. int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
  545. int, int, uint32_t *);
  546. void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
  547. unsigned int, unsigned int);
  548. int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
  549. void csio_hw_intr_disable(struct csio_hw *);
  550. int csio_hw_slow_intr_handler(struct csio_hw *);
  551. int csio_handle_intr_status(struct csio_hw *, unsigned int,
  552. const struct intr_info *);
  553. fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps);
  554. fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
  555. fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32);
  556. fw_port_cap32_t lstatus_to_fwcap(u32 lstatus);
  557. int csio_hw_start(struct csio_hw *);
  558. int csio_hw_stop(struct csio_hw *);
  559. int csio_hw_reset(struct csio_hw *);
  560. int csio_is_hw_ready(struct csio_hw *);
  561. int csio_is_hw_removing(struct csio_hw *);
  562. int csio_fwevtq_handler(struct csio_hw *);
  563. void csio_evtq_worker(struct work_struct *);
  564. int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
  565. void csio_evtq_flush(struct csio_hw *hw);
  566. int csio_request_irqs(struct csio_hw *);
  567. void csio_intr_enable(struct csio_hw *);
  568. void csio_intr_disable(struct csio_hw *, bool);
  569. void csio_hw_fatal_err(struct csio_hw *);
  570. struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
  571. int csio_config_queues(struct csio_hw *);
  572. int csio_hw_init(struct csio_hw *);
  573. void csio_hw_exit(struct csio_hw *);
  574. #endif /* ifndef __CSIO_HW_H__ */