atp870u.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1997 Wu Ching Chen
  4. * 2.1.x update (C) 1998 Krzysztof G. Baranowski
  5. * 2.5.x update (C) 2002 Red Hat
  6. * 2.6.x update (C) 2004 Red Hat
  7. *
  8. * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
  9. *
  10. * Wu Ching Chen : NULL pointer fixes 2000/06/02
  11. * support atp876 chip
  12. * enable 32 bit fifo transfer
  13. * support cdrom & remove device run ultra speed
  14. * fix disconnect bug 2000/12/21
  15. * support atp880 chip lvd u160 2001/05/15
  16. * fix prd table bug 2001/09/12 (7.1)
  17. *
  18. * atp885 support add by ACARD Hao Ping Lian 2005/01/05
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/string.h>
  26. #include <linux/ioport.h>
  27. #include <linux/delay.h>
  28. #include <linux/proc_fs.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/pci.h>
  31. #include <linux/blkdev.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/slab.h>
  34. #include <asm/io.h>
  35. #include <scsi/scsi.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include "atp870u.h"
  40. static struct scsi_host_template atp870u_template;
  41. static void send_s870(struct atp_unit *dev,unsigned char c);
  42. static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, unsigned char lvdmode);
  43. static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val)
  44. {
  45. outb(val, atp->baseport + reg);
  46. }
  47. static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val)
  48. {
  49. outw(val, atp->baseport + reg);
  50. }
  51. static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
  52. {
  53. outb(val, atp->ioport[channel] + reg);
  54. }
  55. static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val)
  56. {
  57. outw(val, atp->ioport[channel] + reg);
  58. }
  59. static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
  60. {
  61. outb(val, atp->pciport[channel] + reg);
  62. }
  63. static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val)
  64. {
  65. outl(val, atp->pciport[channel] + reg);
  66. }
  67. static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg)
  68. {
  69. return inb(atp->baseport + reg);
  70. }
  71. static inline u16 atp_readw_base(struct atp_unit *atp, u8 reg)
  72. {
  73. return inw(atp->baseport + reg);
  74. }
  75. static inline u32 atp_readl_base(struct atp_unit *atp, u8 reg)
  76. {
  77. return inl(atp->baseport + reg);
  78. }
  79. static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg)
  80. {
  81. return inb(atp->ioport[channel] + reg);
  82. }
  83. static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg)
  84. {
  85. return inw(atp->ioport[channel] + reg);
  86. }
  87. static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg)
  88. {
  89. return inb(atp->pciport[channel] + reg);
  90. }
  91. static inline bool is880(struct atp_unit *atp)
  92. {
  93. return atp->pdev->device == ATP880_DEVID1 ||
  94. atp->pdev->device == ATP880_DEVID2;
  95. }
  96. static inline bool is885(struct atp_unit *atp)
  97. {
  98. return atp->pdev->device == ATP885_DEVID;
  99. }
  100. static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
  101. {
  102. unsigned long flags;
  103. unsigned short int id;
  104. unsigned char i, j, c, target_id, lun,cmdp;
  105. unsigned char *prd;
  106. struct scsi_cmnd *workreq;
  107. unsigned long adrcnt, k;
  108. #ifdef ED_DBGP
  109. unsigned long l;
  110. #endif
  111. struct Scsi_Host *host = dev_id;
  112. struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
  113. for (c = 0; c < 2; c++) {
  114. j = atp_readb_io(dev, c, 0x1f);
  115. if ((j & 0x80) != 0)
  116. break;
  117. dev->in_int[c] = 0;
  118. }
  119. if ((j & 0x80) == 0)
  120. return IRQ_NONE;
  121. #ifdef ED_DBGP
  122. printk("atp870u_intr_handle enter\n");
  123. #endif
  124. dev->in_int[c] = 1;
  125. cmdp = atp_readb_io(dev, c, 0x10);
  126. if (dev->working[c] != 0) {
  127. if (is885(dev)) {
  128. if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0)
  129. atp_writeb_io(dev, c, 0x16, (atp_readb_io(dev, c, 0x16) | 0x80));
  130. }
  131. if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0)
  132. {
  133. for (k=0; k < 1000; k++) {
  134. if ((atp_readb_pci(dev, c, 2) & 0x08) == 0)
  135. break;
  136. if ((atp_readb_pci(dev, c, 2) & 0x01) == 0)
  137. break;
  138. }
  139. }
  140. atp_writeb_pci(dev, c, 0, 0x00);
  141. i = atp_readb_io(dev, c, 0x17);
  142. if (is885(dev))
  143. atp_writeb_pci(dev, c, 2, 0x06);
  144. target_id = atp_readb_io(dev, c, 0x15);
  145. /*
  146. * Remap wide devices onto id numbers
  147. */
  148. if ((target_id & 0x40) != 0) {
  149. target_id = (target_id & 0x07) | 0x08;
  150. } else {
  151. target_id &= 0x07;
  152. }
  153. if ((j & 0x40) != 0) {
  154. if (dev->last_cmd[c] == 0xff) {
  155. dev->last_cmd[c] = target_id;
  156. }
  157. dev->last_cmd[c] |= 0x40;
  158. }
  159. if (is885(dev))
  160. dev->r1f[c][target_id] |= j;
  161. #ifdef ED_DBGP
  162. printk("atp870u_intr_handle status = %x\n",i);
  163. #endif
  164. if (i == 0x85) {
  165. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  166. dev->last_cmd[c] = 0xff;
  167. }
  168. if (is885(dev)) {
  169. adrcnt = 0;
  170. ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
  171. ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
  172. ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
  173. if (dev->id[c][target_id].last_len != adrcnt) {
  174. k = dev->id[c][target_id].last_len;
  175. k -= adrcnt;
  176. dev->id[c][target_id].tran_len = k;
  177. dev->id[c][target_id].last_len = adrcnt;
  178. }
  179. #ifdef ED_DBGP
  180. printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
  181. #endif
  182. }
  183. /*
  184. * Flip wide
  185. */
  186. if (dev->wide_id[c] != 0) {
  187. atp_writeb_io(dev, c, 0x1b, 0x01);
  188. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
  189. atp_writeb_io(dev, c, 0x1b, 0x01);
  190. }
  191. /*
  192. * Issue more commands
  193. */
  194. spin_lock_irqsave(dev->host->host_lock, flags);
  195. if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
  196. (dev->in_snd[c] == 0)) {
  197. #ifdef ED_DBGP
  198. printk("Call sent_s870\n");
  199. #endif
  200. send_s870(dev,c);
  201. }
  202. spin_unlock_irqrestore(dev->host->host_lock, flags);
  203. /*
  204. * Done
  205. */
  206. dev->in_int[c] = 0;
  207. #ifdef ED_DBGP
  208. printk("Status 0x85 return\n");
  209. #endif
  210. return IRQ_HANDLED;
  211. }
  212. if (i == 0x40) {
  213. dev->last_cmd[c] |= 0x40;
  214. dev->in_int[c] = 0;
  215. return IRQ_HANDLED;
  216. }
  217. if (i == 0x21) {
  218. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  219. dev->last_cmd[c] = 0xff;
  220. }
  221. adrcnt = 0;
  222. ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
  223. ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
  224. ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
  225. k = dev->id[c][target_id].last_len;
  226. k -= adrcnt;
  227. dev->id[c][target_id].tran_len = k;
  228. dev->id[c][target_id].last_len = adrcnt;
  229. atp_writeb_io(dev, c, 0x10, 0x41);
  230. atp_writeb_io(dev, c, 0x18, 0x08);
  231. dev->in_int[c] = 0;
  232. return IRQ_HANDLED;
  233. }
  234. if (is885(dev)) {
  235. if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
  236. if ((i == 0x4c) || (i == 0x8c))
  237. i=0x48;
  238. else
  239. i=0x49;
  240. }
  241. }
  242. if ((i == 0x80) || (i == 0x8f)) {
  243. #ifdef ED_DBGP
  244. printk(KERN_DEBUG "Device reselect\n");
  245. #endif
  246. lun = 0;
  247. if (cmdp == 0x44 || i == 0x80)
  248. lun = atp_readb_io(dev, c, 0x1d) & 0x07;
  249. else {
  250. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  251. dev->last_cmd[c] = 0xff;
  252. }
  253. if (cmdp == 0x41) {
  254. #ifdef ED_DBGP
  255. printk("cmdp = 0x41\n");
  256. #endif
  257. adrcnt = 0;
  258. ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
  259. ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
  260. ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
  261. k = dev->id[c][target_id].last_len;
  262. k -= adrcnt;
  263. dev->id[c][target_id].tran_len = k;
  264. dev->id[c][target_id].last_len = adrcnt;
  265. atp_writeb_io(dev, c, 0x18, 0x08);
  266. dev->in_int[c] = 0;
  267. return IRQ_HANDLED;
  268. } else {
  269. #ifdef ED_DBGP
  270. printk("cmdp != 0x41\n");
  271. #endif
  272. atp_writeb_io(dev, c, 0x10, 0x46);
  273. dev->id[c][target_id].dirct = 0x00;
  274. atp_writeb_io(dev, c, 0x12, 0x00);
  275. atp_writeb_io(dev, c, 0x13, 0x00);
  276. atp_writeb_io(dev, c, 0x14, 0x00);
  277. atp_writeb_io(dev, c, 0x18, 0x08);
  278. dev->in_int[c] = 0;
  279. return IRQ_HANDLED;
  280. }
  281. }
  282. if (dev->last_cmd[c] != 0xff) {
  283. dev->last_cmd[c] |= 0x40;
  284. }
  285. if (is885(dev)) {
  286. j = atp_readb_base(dev, 0x29) & 0xfe;
  287. atp_writeb_base(dev, 0x29, j);
  288. } else
  289. atp_writeb_io(dev, c, 0x10, 0x45);
  290. target_id = atp_readb_io(dev, c, 0x16);
  291. /*
  292. * Remap wide identifiers
  293. */
  294. if ((target_id & 0x10) != 0) {
  295. target_id = (target_id & 0x07) | 0x08;
  296. } else {
  297. target_id &= 0x07;
  298. }
  299. if (is885(dev))
  300. atp_writeb_io(dev, c, 0x10, 0x45);
  301. workreq = dev->id[c][target_id].curr_req;
  302. #ifdef ED_DBGP
  303. scmd_printk(KERN_DEBUG, workreq, "CDB");
  304. for (l = 0; l < workreq->cmd_len; l++)
  305. printk(KERN_DEBUG " %x",workreq->cmnd[l]);
  306. printk("\n");
  307. #endif
  308. atp_writeb_io(dev, c, 0x0f, lun);
  309. atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
  310. adrcnt = dev->id[c][target_id].tran_len;
  311. k = dev->id[c][target_id].last_len;
  312. atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]);
  313. atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]);
  314. atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]);
  315. #ifdef ED_DBGP
  316. printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, atp_readb_io(dev, c, 0x14), atp_readb_io(dev, c, 0x13), atp_readb_io(dev, c, 0x12));
  317. #endif
  318. /* Remap wide */
  319. j = target_id;
  320. if (target_id > 7) {
  321. j = (j & 0x07) | 0x40;
  322. }
  323. /* Add direction */
  324. j |= dev->id[c][target_id].dirct;
  325. atp_writeb_io(dev, c, 0x15, j);
  326. atp_writeb_io(dev, c, 0x16, 0x80);
  327. /* enable 32 bit fifo transfer */
  328. if (is885(dev)) {
  329. i = atp_readb_pci(dev, c, 1) & 0xf3;
  330. //j=workreq->cmnd[0];
  331. if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
  332. i |= 0x0c;
  333. }
  334. atp_writeb_pci(dev, c, 1, i);
  335. } else if (is880(dev)) {
  336. if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
  337. atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
  338. else
  339. atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f);
  340. } else {
  341. if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
  342. atp_writeb_base(dev, 0x3a, (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08);
  343. else
  344. atp_writeb_base(dev, 0x3a, atp_readb_base(dev, 0x3a) & 0xf3);
  345. }
  346. j = 0;
  347. id = 1;
  348. id = id << target_id;
  349. /*
  350. * Is this a wide device
  351. */
  352. if ((id & dev->wide_id[c]) != 0) {
  353. j |= 0x01;
  354. }
  355. atp_writeb_io(dev, c, 0x1b, j);
  356. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j)
  357. atp_writeb_io(dev, c, 0x1b, j);
  358. if (dev->id[c][target_id].last_len == 0) {
  359. atp_writeb_io(dev, c, 0x18, 0x08);
  360. dev->in_int[c] = 0;
  361. #ifdef ED_DBGP
  362. printk("dev->id[c][target_id].last_len = 0\n");
  363. #endif
  364. return IRQ_HANDLED;
  365. }
  366. #ifdef ED_DBGP
  367. printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
  368. #endif
  369. prd = dev->id[c][target_id].prd_pos;
  370. while (adrcnt != 0) {
  371. id = ((unsigned short int *)prd)[2];
  372. if (id == 0) {
  373. k = 0x10000;
  374. } else {
  375. k = id;
  376. }
  377. if (k > adrcnt) {
  378. ((unsigned short int *)prd)[2] = (unsigned short int)
  379. (k - adrcnt);
  380. ((unsigned long *)prd)[0] += adrcnt;
  381. adrcnt = 0;
  382. dev->id[c][target_id].prd_pos = prd;
  383. } else {
  384. adrcnt -= k;
  385. dev->id[c][target_id].prdaddr += 0x08;
  386. prd += 0x08;
  387. if (adrcnt == 0) {
  388. dev->id[c][target_id].prd_pos = prd;
  389. }
  390. }
  391. }
  392. atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr);
  393. #ifdef ED_DBGP
  394. printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
  395. #endif
  396. if (!is885(dev)) {
  397. atp_writeb_pci(dev, c, 2, 0x06);
  398. atp_writeb_pci(dev, c, 2, 0x00);
  399. }
  400. /*
  401. * Check transfer direction
  402. */
  403. if (dev->id[c][target_id].dirct != 0) {
  404. atp_writeb_io(dev, c, 0x18, 0x08);
  405. atp_writeb_pci(dev, c, 0, 0x01);
  406. dev->in_int[c] = 0;
  407. #ifdef ED_DBGP
  408. printk("status 0x80 return dirct != 0\n");
  409. #endif
  410. return IRQ_HANDLED;
  411. }
  412. atp_writeb_io(dev, c, 0x18, 0x08);
  413. atp_writeb_pci(dev, c, 0, 0x09);
  414. dev->in_int[c] = 0;
  415. #ifdef ED_DBGP
  416. printk("status 0x80 return dirct = 0\n");
  417. #endif
  418. return IRQ_HANDLED;
  419. }
  420. /*
  421. * Current scsi request on this target
  422. */
  423. workreq = dev->id[c][target_id].curr_req;
  424. if (i == 0x42 || i == 0x16) {
  425. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  426. dev->last_cmd[c] = 0xff;
  427. }
  428. if (i == 0x16) {
  429. workreq->result = atp_readb_io(dev, c, 0x0f);
  430. if (((dev->r1f[c][target_id] & 0x10) != 0) && is885(dev)) {
  431. printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
  432. workreq->result = 0x02;
  433. }
  434. } else
  435. workreq->result = 0x02;
  436. if (is885(dev)) {
  437. j = atp_readb_base(dev, 0x29) | 0x01;
  438. atp_writeb_base(dev, 0x29, j);
  439. }
  440. /*
  441. * Complete the command
  442. */
  443. scsi_dma_unmap(workreq);
  444. spin_lock_irqsave(dev->host->host_lock, flags);
  445. (*workreq->scsi_done) (workreq);
  446. #ifdef ED_DBGP
  447. printk("workreq->scsi_done\n");
  448. #endif
  449. /*
  450. * Clear it off the queue
  451. */
  452. dev->id[c][target_id].curr_req = NULL;
  453. dev->working[c]--;
  454. spin_unlock_irqrestore(dev->host->host_lock, flags);
  455. /*
  456. * Take it back wide
  457. */
  458. if (dev->wide_id[c] != 0) {
  459. atp_writeb_io(dev, c, 0x1b, 0x01);
  460. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
  461. atp_writeb_io(dev, c, 0x1b, 0x01);
  462. }
  463. /*
  464. * If there is stuff to send and nothing going then send it
  465. */
  466. spin_lock_irqsave(dev->host->host_lock, flags);
  467. if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
  468. (dev->in_snd[c] == 0)) {
  469. #ifdef ED_DBGP
  470. printk("Call sent_s870(scsi_done)\n");
  471. #endif
  472. send_s870(dev,c);
  473. }
  474. spin_unlock_irqrestore(dev->host->host_lock, flags);
  475. dev->in_int[c] = 0;
  476. return IRQ_HANDLED;
  477. }
  478. if ((dev->last_cmd[c] & 0xf0) != 0x40) {
  479. dev->last_cmd[c] = 0xff;
  480. }
  481. if (i == 0x4f) {
  482. i = 0x89;
  483. }
  484. i &= 0x0f;
  485. if (i == 0x09) {
  486. atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
  487. atp_writeb_pci(dev, c, 2, 0x06);
  488. atp_writeb_pci(dev, c, 2, 0x00);
  489. atp_writeb_io(dev, c, 0x10, 0x41);
  490. if (is885(dev)) {
  491. k = dev->id[c][target_id].last_len;
  492. atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]);
  493. atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]);
  494. atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]);
  495. dev->id[c][target_id].dirct = 0x00;
  496. } else {
  497. dev->id[c][target_id].dirct = 0x00;
  498. }
  499. atp_writeb_io(dev, c, 0x18, 0x08);
  500. atp_writeb_pci(dev, c, 0, 0x09);
  501. dev->in_int[c] = 0;
  502. return IRQ_HANDLED;
  503. }
  504. if (i == 0x08) {
  505. atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
  506. atp_writeb_pci(dev, c, 2, 0x06);
  507. atp_writeb_pci(dev, c, 2, 0x00);
  508. atp_writeb_io(dev, c, 0x10, 0x41);
  509. if (is885(dev)) {
  510. k = dev->id[c][target_id].last_len;
  511. atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]);
  512. atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]);
  513. atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]);
  514. }
  515. atp_writeb_io(dev, c, 0x15, atp_readb_io(dev, c, 0x15) | 0x20);
  516. dev->id[c][target_id].dirct = 0x20;
  517. atp_writeb_io(dev, c, 0x18, 0x08);
  518. atp_writeb_pci(dev, c, 0, 0x01);
  519. dev->in_int[c] = 0;
  520. return IRQ_HANDLED;
  521. }
  522. if (i == 0x0a)
  523. atp_writeb_io(dev, c, 0x10, 0x30);
  524. else
  525. atp_writeb_io(dev, c, 0x10, 0x46);
  526. dev->id[c][target_id].dirct = 0x00;
  527. atp_writeb_io(dev, c, 0x12, 0x00);
  528. atp_writeb_io(dev, c, 0x13, 0x00);
  529. atp_writeb_io(dev, c, 0x14, 0x00);
  530. atp_writeb_io(dev, c, 0x18, 0x08);
  531. }
  532. dev->in_int[c] = 0;
  533. return IRQ_HANDLED;
  534. }
  535. /**
  536. * atp870u_queuecommand - Queue SCSI command
  537. * @req_p: request block
  538. * @done: completion function
  539. *
  540. * Queue a command to the ATP queue. Called with the host lock held.
  541. */
  542. static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p,
  543. void (*done) (struct scsi_cmnd *))
  544. {
  545. unsigned char c;
  546. unsigned int m;
  547. struct atp_unit *dev;
  548. struct Scsi_Host *host;
  549. c = scmd_channel(req_p);
  550. req_p->sense_buffer[0]=0;
  551. scsi_set_resid(req_p, 0);
  552. if (scmd_channel(req_p) > 1) {
  553. req_p->result = 0x00040000;
  554. done(req_p);
  555. #ifdef ED_DBGP
  556. printk("atp870u_queuecommand : req_p->device->channel > 1\n");
  557. #endif
  558. return 0;
  559. }
  560. host = req_p->device->host;
  561. dev = (struct atp_unit *)&host->hostdata;
  562. m = 1;
  563. m = m << scmd_id(req_p);
  564. /*
  565. * Fake a timeout for missing targets
  566. */
  567. if ((m & dev->active_id[c]) == 0) {
  568. req_p->result = 0x00040000;
  569. done(req_p);
  570. return 0;
  571. }
  572. if (done) {
  573. req_p->scsi_done = done;
  574. } else {
  575. #ifdef ED_DBGP
  576. printk( "atp870u_queuecommand: done can't be NULL\n");
  577. #endif
  578. req_p->result = 0;
  579. done(req_p);
  580. return 0;
  581. }
  582. /*
  583. * Count new command
  584. */
  585. dev->quend[c]++;
  586. if (dev->quend[c] >= qcnt) {
  587. dev->quend[c] = 0;
  588. }
  589. /*
  590. * Check queue state
  591. */
  592. if (dev->quhd[c] == dev->quend[c]) {
  593. if (dev->quend[c] == 0) {
  594. dev->quend[c] = qcnt;
  595. }
  596. #ifdef ED_DBGP
  597. printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
  598. #endif
  599. dev->quend[c]--;
  600. req_p->result = 0x00020000;
  601. done(req_p);
  602. return 0;
  603. }
  604. dev->quereq[c][dev->quend[c]] = req_p;
  605. #ifdef ED_DBGP
  606. printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],atp_readb_io(dev, c, 0x1c),c,dev->in_int[c],c,dev->in_snd[c]);
  607. #endif
  608. if ((atp_readb_io(dev, c, 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
  609. #ifdef ED_DBGP
  610. printk("Call sent_s870(atp870u_queuecommand)\n");
  611. #endif
  612. send_s870(dev,c);
  613. }
  614. #ifdef ED_DBGP
  615. printk("atp870u_queuecommand : exit\n");
  616. #endif
  617. return 0;
  618. }
  619. static DEF_SCSI_QCMD(atp870u_queuecommand)
  620. /**
  621. * send_s870 - send a command to the controller
  622. * @host: host
  623. *
  624. * On entry there is work queued to be done. We move some of that work to the
  625. * controller itself.
  626. *
  627. * Caller holds the host lock.
  628. */
  629. static void send_s870(struct atp_unit *dev,unsigned char c)
  630. {
  631. struct scsi_cmnd *workreq = NULL;
  632. unsigned int i;//,k;
  633. unsigned char j, target_id;
  634. unsigned char *prd;
  635. unsigned short int w;
  636. unsigned long l, bttl = 0;
  637. unsigned long sg_count;
  638. if (dev->in_snd[c] != 0) {
  639. #ifdef ED_DBGP
  640. printk("cmnd in_snd\n");
  641. #endif
  642. return;
  643. }
  644. #ifdef ED_DBGP
  645. printk("Sent_s870 enter\n");
  646. #endif
  647. dev->in_snd[c] = 1;
  648. if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
  649. dev->last_cmd[c] &= 0x0f;
  650. workreq = dev->id[c][dev->last_cmd[c]].curr_req;
  651. if (!workreq) {
  652. dev->last_cmd[c] = 0xff;
  653. if (dev->quhd[c] == dev->quend[c]) {
  654. dev->in_snd[c] = 0;
  655. return;
  656. }
  657. }
  658. }
  659. if (!workreq) {
  660. if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
  661. dev->in_snd[c] = 0;
  662. return;
  663. }
  664. dev->working[c]++;
  665. j = dev->quhd[c];
  666. dev->quhd[c]++;
  667. if (dev->quhd[c] >= qcnt)
  668. dev->quhd[c] = 0;
  669. workreq = dev->quereq[c][dev->quhd[c]];
  670. if (dev->id[c][scmd_id(workreq)].curr_req != NULL) {
  671. dev->quhd[c] = j;
  672. dev->working[c]--;
  673. dev->in_snd[c] = 0;
  674. return;
  675. }
  676. dev->id[c][scmd_id(workreq)].curr_req = workreq;
  677. dev->last_cmd[c] = scmd_id(workreq);
  678. }
  679. if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 || atp_readb_io(dev, c, 0x1c) != 0) {
  680. #ifdef ED_DBGP
  681. printk("Abort to Send\n");
  682. #endif
  683. dev->last_cmd[c] |= 0x40;
  684. dev->in_snd[c] = 0;
  685. return;
  686. }
  687. #ifdef ED_DBGP
  688. printk("OK to Send\n");
  689. scmd_printk(KERN_DEBUG, workreq, "CDB");
  690. for(i=0;i<workreq->cmd_len;i++) {
  691. printk(" %x",workreq->cmnd[i]);
  692. }
  693. printk("\n");
  694. #endif
  695. l = scsi_bufflen(workreq);
  696. if (is885(dev)) {
  697. j = atp_readb_base(dev, 0x29) & 0xfe;
  698. atp_writeb_base(dev, 0x29, j);
  699. dev->r1f[c][scmd_id(workreq)] = 0;
  700. }
  701. if (workreq->cmnd[0] == READ_CAPACITY) {
  702. if (l > 8)
  703. l = 8;
  704. }
  705. if (workreq->cmnd[0] == 0x00) {
  706. l = 0;
  707. }
  708. j = 0;
  709. target_id = scmd_id(workreq);
  710. /*
  711. * Wide ?
  712. */
  713. w = 1;
  714. w = w << target_id;
  715. if ((w & dev->wide_id[c]) != 0) {
  716. j |= 0x01;
  717. }
  718. atp_writeb_io(dev, c, 0x1b, j);
  719. while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) {
  720. atp_writeb_pci(dev, c, 0x1b, j);
  721. #ifdef ED_DBGP
  722. printk("send_s870 while loop 1\n");
  723. #endif
  724. }
  725. /*
  726. * Write the command
  727. */
  728. atp_writeb_io(dev, c, 0x00, workreq->cmd_len);
  729. atp_writeb_io(dev, c, 0x01, 0x2c);
  730. if (is885(dev))
  731. atp_writeb_io(dev, c, 0x02, 0x7f);
  732. else
  733. atp_writeb_io(dev, c, 0x02, 0xcf);
  734. for (i = 0; i < workreq->cmd_len; i++)
  735. atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]);
  736. atp_writeb_io(dev, c, 0x0f, workreq->device->lun);
  737. /*
  738. * Write the target
  739. */
  740. atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
  741. #ifdef ED_DBGP
  742. printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
  743. #endif
  744. sg_count = scsi_dma_map(workreq);
  745. /*
  746. * Write transfer size
  747. */
  748. atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]);
  749. atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]);
  750. atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]);
  751. j = target_id;
  752. dev->id[c][j].last_len = l;
  753. dev->id[c][j].tran_len = 0;
  754. #ifdef ED_DBGP
  755. printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
  756. #endif
  757. /*
  758. * Flip the wide bits
  759. */
  760. if ((j & 0x08) != 0) {
  761. j = (j & 0x07) | 0x40;
  762. }
  763. /*
  764. * Check transfer direction
  765. */
  766. if (workreq->sc_data_direction == DMA_TO_DEVICE)
  767. atp_writeb_io(dev, c, 0x15, j | 0x20);
  768. else
  769. atp_writeb_io(dev, c, 0x15, j);
  770. atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80);
  771. atp_writeb_io(dev, c, 0x16, 0x80);
  772. dev->id[c][target_id].dirct = 0;
  773. if (l == 0) {
  774. if (atp_readb_io(dev, c, 0x1c) == 0) {
  775. #ifdef ED_DBGP
  776. printk("change SCSI_CMD_REG 0x08\n");
  777. #endif
  778. atp_writeb_io(dev, c, 0x18, 0x08);
  779. } else
  780. dev->last_cmd[c] |= 0x40;
  781. dev->in_snd[c] = 0;
  782. return;
  783. }
  784. prd = dev->id[c][target_id].prd_table;
  785. dev->id[c][target_id].prd_pos = prd;
  786. /*
  787. * Now write the request list. Either as scatter/gather or as
  788. * a linear chain.
  789. */
  790. if (l) {
  791. struct scatterlist *sgpnt;
  792. i = 0;
  793. scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
  794. bttl = sg_dma_address(sgpnt);
  795. l=sg_dma_len(sgpnt);
  796. #ifdef ED_DBGP
  797. printk("1. bttl %x, l %x\n",bttl, l);
  798. #endif
  799. while (l > 0x10000) {
  800. (((u16 *) (prd))[i + 3]) = 0x0000;
  801. (((u16 *) (prd))[i + 2]) = 0x0000;
  802. (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
  803. l -= 0x10000;
  804. bttl += 0x10000;
  805. i += 0x04;
  806. }
  807. (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
  808. (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
  809. (((u16 *) (prd))[i + 3]) = 0;
  810. i += 0x04;
  811. }
  812. (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
  813. #ifdef ED_DBGP
  814. printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
  815. printk("2. bttl %x, l %x\n",bttl, l);
  816. #endif
  817. }
  818. #ifdef ED_DBGP
  819. printk("send_s870: prdaddr_2 0x%8x target_id %d\n", dev->id[c][target_id].prdaddr,target_id);
  820. #endif
  821. dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
  822. atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
  823. atp_writeb_pci(dev, c, 2, 0x06);
  824. atp_writeb_pci(dev, c, 2, 0x00);
  825. if (is885(dev)) {
  826. j = atp_readb_pci(dev, c, 1) & 0xf3;
  827. if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
  828. (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
  829. j |= 0x0c;
  830. }
  831. atp_writeb_pci(dev, c, 1, j);
  832. } else if (is880(dev)) {
  833. if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
  834. atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
  835. else
  836. atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f);
  837. } else {
  838. if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
  839. atp_writeb_base(dev, 0x3a, (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08);
  840. else
  841. atp_writeb_base(dev, 0x3a, atp_readb_base(dev, 0x3a) & 0xf3);
  842. }
  843. if(workreq->sc_data_direction == DMA_TO_DEVICE) {
  844. dev->id[c][target_id].dirct = 0x20;
  845. if (atp_readb_io(dev, c, 0x1c) == 0) {
  846. atp_writeb_io(dev, c, 0x18, 0x08);
  847. atp_writeb_pci(dev, c, 0, 0x01);
  848. #ifdef ED_DBGP
  849. printk( "start DMA(to target)\n");
  850. #endif
  851. } else {
  852. dev->last_cmd[c] |= 0x40;
  853. }
  854. dev->in_snd[c] = 0;
  855. return;
  856. }
  857. if (atp_readb_io(dev, c, 0x1c) == 0) {
  858. atp_writeb_io(dev, c, 0x18, 0x08);
  859. atp_writeb_pci(dev, c, 0, 0x09);
  860. #ifdef ED_DBGP
  861. printk( "start DMA(to host)\n");
  862. #endif
  863. } else {
  864. dev->last_cmd[c] |= 0x40;
  865. }
  866. dev->in_snd[c] = 0;
  867. return;
  868. }
  869. static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
  870. {
  871. unsigned short int i, k;
  872. unsigned char j;
  873. atp_writew_io(dev, 0, 0x1c, *val);
  874. for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
  875. k = atp_readw_io(dev, 0, 0x1c);
  876. j = (unsigned char) (k >> 8);
  877. if ((k & 0x8000) != 0) /* DB7 all release? */
  878. i = 0;
  879. }
  880. *val |= 0x4000; /* assert DB6 */
  881. atp_writew_io(dev, 0, 0x1c, *val);
  882. *val &= 0xdfff; /* assert DB5 */
  883. atp_writew_io(dev, 0, 0x1c, *val);
  884. for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
  885. if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */
  886. i = 0;
  887. }
  888. *val |= 0x8000; /* no DB4-0, assert DB7 */
  889. *val &= 0xe0ff;
  890. atp_writew_io(dev, 0, 0x1c, *val);
  891. *val &= 0xbfff; /* release DB6 */
  892. atp_writew_io(dev, 0, 0x1c, *val);
  893. for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
  894. if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */
  895. i = 0;
  896. }
  897. return j;
  898. }
  899. static void tscam(struct Scsi_Host *host, bool wide_chip, u8 scam_on)
  900. {
  901. unsigned char i, j, k;
  902. unsigned long n;
  903. unsigned short int m, assignid_map, val;
  904. unsigned char mbuf[33], quintet[2];
  905. struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
  906. static unsigned char g2q_tab[8] = {
  907. 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
  908. };
  909. /* I can't believe we need this before we've even done anything. Remove it
  910. * and see if anyone bitches.
  911. for (i = 0; i < 0x10; i++) {
  912. udelay(0xffff);
  913. }
  914. */
  915. atp_writeb_io(dev, 0, 1, 0x08);
  916. atp_writeb_io(dev, 0, 2, 0x7f);
  917. atp_writeb_io(dev, 0, 0x11, 0x20);
  918. if ((scam_on & 0x40) == 0) {
  919. return;
  920. }
  921. m = 1;
  922. m <<= dev->host_id[0];
  923. j = 16;
  924. if (!wide_chip) {
  925. m |= 0xff00;
  926. j = 8;
  927. }
  928. assignid_map = m;
  929. atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */
  930. atp_writeb_io(dev, 0, 0x03, 0);
  931. atp_writeb_io(dev, 0, 0x04, 0);
  932. atp_writeb_io(dev, 0, 0x05, 0);
  933. atp_writeb_io(dev, 0, 0x06, 0);
  934. atp_writeb_io(dev, 0, 0x07, 0);
  935. atp_writeb_io(dev, 0, 0x08, 0);
  936. for (i = 0; i < j; i++) {
  937. m = 1;
  938. m = m << i;
  939. if ((m & assignid_map) != 0) {
  940. continue;
  941. }
  942. atp_writeb_io(dev, 0, 0x0f, 0);
  943. atp_writeb_io(dev, 0, 0x12, 0);
  944. atp_writeb_io(dev, 0, 0x13, 0);
  945. atp_writeb_io(dev, 0, 0x14, 0);
  946. if (i > 7) {
  947. k = (i & 0x07) | 0x40;
  948. } else {
  949. k = i;
  950. }
  951. atp_writeb_io(dev, 0, 0x15, k);
  952. if (wide_chip)
  953. atp_writeb_io(dev, 0, 0x1b, 0x01);
  954. else
  955. atp_writeb_io(dev, 0, 0x1b, 0x00);
  956. do {
  957. atp_writeb_io(dev, 0, 0x18, 0x09);
  958. while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
  959. cpu_relax();
  960. k = atp_readb_io(dev, 0, 0x17);
  961. if ((k == 0x85) || (k == 0x42))
  962. break;
  963. if (k != 0x16)
  964. atp_writeb_io(dev, 0, 0x10, 0x41);
  965. } while (k != 0x16);
  966. if ((k == 0x85) || (k == 0x42))
  967. continue;
  968. assignid_map |= m;
  969. }
  970. atp_writeb_io(dev, 0, 0x02, 0x7f);
  971. atp_writeb_io(dev, 0, 0x1b, 0x02);
  972. udelay(2);
  973. val = 0x0080; /* bsy */
  974. atp_writew_io(dev, 0, 0x1c, val);
  975. val |= 0x0040; /* sel */
  976. atp_writew_io(dev, 0, 0x1c, val);
  977. val |= 0x0004; /* msg */
  978. atp_writew_io(dev, 0, 0x1c, val);
  979. udelay(2); /* 2 deskew delay(45ns*2=90ns) */
  980. val &= 0x007f; /* no bsy */
  981. atp_writew_io(dev, 0, 0x1c, val);
  982. msleep(128);
  983. val &= 0x00fb; /* after 1ms no msg */
  984. atp_writew_io(dev, 0, 0x1c, val);
  985. while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0)
  986. ;
  987. udelay(2);
  988. udelay(100);
  989. for (n = 0; n < 0x30000; n++)
  990. if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */
  991. break;
  992. if (n < 0x30000)
  993. for (n = 0; n < 0x30000; n++)
  994. if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) {
  995. udelay(2);
  996. val |= 0x8003; /* io,cd,db7 */
  997. atp_writew_io(dev, 0, 0x1c, val);
  998. udelay(2);
  999. val &= 0x00bf; /* no sel */
  1000. atp_writew_io(dev, 0, 0x1c, val);
  1001. udelay(2);
  1002. break;
  1003. }
  1004. while (1) {
  1005. /*
  1006. * The funny division into multiple delays is to accomodate
  1007. * arches like ARM where udelay() multiplies its argument by
  1008. * a large number to initialize a loop counter. To avoid
  1009. * overflow, the maximum supported udelay is 2000 microseconds.
  1010. *
  1011. * XXX it would be more polite to find a way to use msleep()
  1012. */
  1013. mdelay(2);
  1014. udelay(48);
  1015. if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */
  1016. atp_writew_io(dev, 0, 0x1c, 0);
  1017. atp_writeb_io(dev, 0, 0x1b, 0);
  1018. atp_writeb_io(dev, 0, 0x15, 0);
  1019. atp_writeb_io(dev, 0, 0x18, 0x09);
  1020. while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0)
  1021. cpu_relax();
  1022. atp_readb_io(dev, 0, 0x17);
  1023. return;
  1024. }
  1025. val &= 0x00ff; /* synchronization */
  1026. val |= 0x3f00;
  1027. fun_scam(dev, &val);
  1028. udelay(2);
  1029. val &= 0x00ff; /* isolation */
  1030. val |= 0x2000;
  1031. fun_scam(dev, &val);
  1032. udelay(2);
  1033. i = 8;
  1034. j = 0;
  1035. while (1) {
  1036. if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0)
  1037. continue;
  1038. udelay(2);
  1039. val &= 0x00ff; /* get ID_STRING */
  1040. val |= 0x2000;
  1041. k = fun_scam(dev, &val);
  1042. if ((k & 0x03) == 0)
  1043. break;
  1044. mbuf[j] <<= 0x01;
  1045. mbuf[j] &= 0xfe;
  1046. if ((k & 0x02) != 0)
  1047. mbuf[j] |= 0x01;
  1048. i--;
  1049. if (i > 0)
  1050. continue;
  1051. j++;
  1052. i = 8;
  1053. }
  1054. /* isolation complete.. */
  1055. /* mbuf[32]=0;
  1056. printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
  1057. i = 15;
  1058. j = mbuf[0];
  1059. if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */
  1060. i = 7;
  1061. }
  1062. if ((j & 0x06) != 0) { /* IDvalid? */
  1063. k = mbuf[1];
  1064. while (1) {
  1065. m = 1;
  1066. m <<= k;
  1067. if ((m & assignid_map) == 0)
  1068. break;
  1069. if (k > 0)
  1070. k--;
  1071. else
  1072. break;
  1073. }
  1074. }
  1075. if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */
  1076. k = i; /* max acceptable ID# */
  1077. while (1) {
  1078. m = 1;
  1079. m <<= k;
  1080. if ((m & assignid_map) == 0)
  1081. break;
  1082. if (k > 0)
  1083. k--;
  1084. else
  1085. break;
  1086. }
  1087. }
  1088. /* k=binID#, */
  1089. assignid_map |= m;
  1090. if (k < 8) {
  1091. quintet[0] = 0x38; /* 1st dft ID<8 */
  1092. } else {
  1093. quintet[0] = 0x31; /* 1st ID>=8 */
  1094. }
  1095. k &= 0x07;
  1096. quintet[1] = g2q_tab[k];
  1097. val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */
  1098. m = quintet[0] << 8;
  1099. val |= m;
  1100. fun_scam(dev, &val);
  1101. val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */
  1102. m = quintet[1] << 8;
  1103. val |= m;
  1104. fun_scam(dev, &val);
  1105. }
  1106. }
  1107. static void atp870u_free_tables(struct Scsi_Host *host)
  1108. {
  1109. struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
  1110. int j, k;
  1111. for (j=0; j < 2; j++) {
  1112. for (k = 0; k < 16; k++) {
  1113. if (!atp_dev->id[j][k].prd_table)
  1114. continue;
  1115. dma_free_coherent(&atp_dev->pdev->dev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
  1116. atp_dev->id[j][k].prd_table = NULL;
  1117. }
  1118. }
  1119. }
  1120. static int atp870u_init_tables(struct Scsi_Host *host)
  1121. {
  1122. struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
  1123. int c,k;
  1124. for(c=0;c < 2;c++) {
  1125. for(k=0;k<16;k++) {
  1126. atp_dev->id[c][k].prd_table = dma_alloc_coherent(&atp_dev->pdev->dev, 1024, &(atp_dev->id[c][k].prd_bus), GFP_KERNEL);
  1127. if (!atp_dev->id[c][k].prd_table) {
  1128. printk("atp870u_init_tables fail\n");
  1129. atp870u_free_tables(host);
  1130. return -ENOMEM;
  1131. }
  1132. atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
  1133. atp_dev->id[c][k].devsp=0x20;
  1134. atp_dev->id[c][k].devtype = 0x7f;
  1135. atp_dev->id[c][k].curr_req = NULL;
  1136. }
  1137. atp_dev->active_id[c] = 0;
  1138. atp_dev->wide_id[c] = 0;
  1139. atp_dev->host_id[c] = 0x07;
  1140. atp_dev->quhd[c] = 0;
  1141. atp_dev->quend[c] = 0;
  1142. atp_dev->last_cmd[c] = 0xff;
  1143. atp_dev->in_snd[c] = 0;
  1144. atp_dev->in_int[c] = 0;
  1145. for (k = 0; k < qcnt; k++) {
  1146. atp_dev->quereq[c][k] = NULL;
  1147. }
  1148. for (k = 0; k < 16; k++) {
  1149. atp_dev->id[c][k].curr_req = NULL;
  1150. atp_dev->sp[c][k] = 0x04;
  1151. }
  1152. }
  1153. return 0;
  1154. }
  1155. static void atp_set_host_id(struct atp_unit *atp, u8 c, u8 host_id)
  1156. {
  1157. atp_writeb_io(atp, c, 0, host_id | 0x08);
  1158. atp_writeb_io(atp, c, 0x18, 0);
  1159. while ((atp_readb_io(atp, c, 0x1f) & 0x80) == 0)
  1160. mdelay(1);
  1161. atp_readb_io(atp, c, 0x17);
  1162. atp_writeb_io(atp, c, 1, 8);
  1163. atp_writeb_io(atp, c, 2, 0x7f);
  1164. atp_writeb_io(atp, c, 0x11, 0x20);
  1165. }
  1166. static void atp870_init(struct Scsi_Host *shpnt)
  1167. {
  1168. struct atp_unit *atpdev = shost_priv(shpnt);
  1169. struct pci_dev *pdev = atpdev->pdev;
  1170. unsigned char k, host_id;
  1171. u8 scam_on;
  1172. bool wide_chip =
  1173. (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7610 &&
  1174. pdev->revision == 4) ||
  1175. (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612UW) ||
  1176. (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612SUW);
  1177. pci_read_config_byte(pdev, 0x49, &host_id);
  1178. dev_info(&pdev->dev, "ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: IO:%lx, IRQ:%d.\n",
  1179. shpnt->io_port, shpnt->irq);
  1180. atpdev->ioport[0] = shpnt->io_port;
  1181. atpdev->pciport[0] = shpnt->io_port + 0x20;
  1182. host_id &= 0x07;
  1183. atpdev->host_id[0] = host_id;
  1184. scam_on = atp_readb_pci(atpdev, 0, 2);
  1185. atpdev->global_map[0] = atp_readb_base(atpdev, 0x2d);
  1186. atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x2e);
  1187. if (atpdev->ultra_map[0] == 0) {
  1188. scam_on = 0x00;
  1189. atpdev->global_map[0] = 0x20;
  1190. atpdev->ultra_map[0] = 0xffff;
  1191. }
  1192. if (pdev->revision > 0x07) /* check if atp876 chip */
  1193. atp_writeb_base(atpdev, 0x3e, 0x00); /* enable terminator */
  1194. k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10;
  1195. atp_writeb_base(atpdev, 0x3a, k);
  1196. atp_writeb_base(atpdev, 0x3a, k & 0xdf);
  1197. msleep(32);
  1198. atp_writeb_base(atpdev, 0x3a, k);
  1199. msleep(32);
  1200. atp_set_host_id(atpdev, 0, host_id);
  1201. tscam(shpnt, wide_chip, scam_on);
  1202. atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) | 0x10);
  1203. atp_is(atpdev, 0, wide_chip, 0);
  1204. atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) & 0xef);
  1205. atp_writeb_base(atpdev, 0x3b, atp_readb_base(atpdev, 0x3b) | 0x20);
  1206. shpnt->max_id = wide_chip ? 16 : 8;
  1207. shpnt->this_id = host_id;
  1208. }
  1209. static void atp880_init(struct Scsi_Host *shpnt)
  1210. {
  1211. struct atp_unit *atpdev = shost_priv(shpnt);
  1212. struct pci_dev *pdev = atpdev->pdev;
  1213. unsigned char k, m, host_id;
  1214. unsigned int n;
  1215. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
  1216. atpdev->ioport[0] = shpnt->io_port + 0x40;
  1217. atpdev->pciport[0] = shpnt->io_port + 0x28;
  1218. host_id = atp_readb_base(atpdev, 0x39) >> 4;
  1219. dev_info(&pdev->dev, "ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: IO:%lx, IRQ:%d.\n",
  1220. shpnt->io_port, shpnt->irq);
  1221. atpdev->host_id[0] = host_id;
  1222. atpdev->global_map[0] = atp_readb_base(atpdev, 0x35);
  1223. atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x3c);
  1224. n = 0x3f09;
  1225. while (n < 0x4000) {
  1226. m = 0;
  1227. atp_writew_base(atpdev, 0x34, n);
  1228. n += 0x0002;
  1229. if (atp_readb_base(atpdev, 0x30) == 0xff)
  1230. break;
  1231. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1232. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1233. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1234. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1235. atp_writew_base(atpdev, 0x34, n);
  1236. n += 0x0002;
  1237. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1238. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1239. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1240. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1241. atp_writew_base(atpdev, 0x34, n);
  1242. n += 0x0002;
  1243. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1244. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1245. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1246. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1247. atp_writew_base(atpdev, 0x34, n);
  1248. n += 0x0002;
  1249. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30);
  1250. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31);
  1251. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32);
  1252. atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33);
  1253. n += 0x0018;
  1254. }
  1255. atp_writew_base(atpdev, 0x34, 0);
  1256. atpdev->ultra_map[0] = 0;
  1257. atpdev->async[0] = 0;
  1258. for (k = 0; k < 16; k++) {
  1259. n = 1 << k;
  1260. if (atpdev->sp[0][k] > 1)
  1261. atpdev->ultra_map[0] |= n;
  1262. else
  1263. if (atpdev->sp[0][k] == 0)
  1264. atpdev->async[0] |= n;
  1265. }
  1266. atpdev->async[0] = ~(atpdev->async[0]);
  1267. atp_writeb_base(atpdev, 0x35, atpdev->global_map[0]);
  1268. k = atp_readb_base(atpdev, 0x38) & 0x80;
  1269. atp_writeb_base(atpdev, 0x38, k);
  1270. atp_writeb_base(atpdev, 0x3b, 0x20);
  1271. msleep(32);
  1272. atp_writeb_base(atpdev, 0x3b, 0);
  1273. msleep(32);
  1274. atp_readb_io(atpdev, 0, 0x1b);
  1275. atp_readb_io(atpdev, 0, 0x17);
  1276. atp_set_host_id(atpdev, 0, host_id);
  1277. tscam(shpnt, true, atp_readb_base(atpdev, 0x22));
  1278. atp_is(atpdev, 0, true, atp_readb_base(atpdev, 0x3f) & 0x40);
  1279. atp_writeb_base(atpdev, 0x38, 0xb0);
  1280. shpnt->max_id = 16;
  1281. shpnt->this_id = host_id;
  1282. }
  1283. static void atp885_init(struct Scsi_Host *shpnt)
  1284. {
  1285. struct atp_unit *atpdev = shost_priv(shpnt);
  1286. struct pci_dev *pdev = atpdev->pdev;
  1287. unsigned char k, m, c;
  1288. unsigned int n;
  1289. unsigned char setupdata[2][16];
  1290. dev_info(&pdev->dev, "ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%lx, IRQ:%d.\n",
  1291. shpnt->io_port, shpnt->irq);
  1292. atpdev->ioport[0] = shpnt->io_port + 0x80;
  1293. atpdev->ioport[1] = shpnt->io_port + 0xc0;
  1294. atpdev->pciport[0] = shpnt->io_port + 0x40;
  1295. atpdev->pciport[1] = shpnt->io_port + 0x50;
  1296. c = atp_readb_base(atpdev, 0x29);
  1297. atp_writeb_base(atpdev, 0x29, c | 0x04);
  1298. n = 0x1f80;
  1299. while (n < 0x2000) {
  1300. atp_writew_base(atpdev, 0x3c, n);
  1301. if (atp_readl_base(atpdev, 0x38) == 0xffffffff)
  1302. break;
  1303. for (m = 0; m < 2; m++) {
  1304. atpdev->global_map[m] = 0;
  1305. for (k = 0; k < 4; k++) {
  1306. atp_writew_base(atpdev, 0x3c, n++);
  1307. ((u32 *)&setupdata[m][0])[k] = atp_readl_base(atpdev, 0x38);
  1308. }
  1309. for (k = 0; k < 4; k++) {
  1310. atp_writew_base(atpdev, 0x3c, n++);
  1311. ((u32 *)&atpdev->sp[m][0])[k] = atp_readl_base(atpdev, 0x38);
  1312. }
  1313. n += 8;
  1314. }
  1315. }
  1316. c = atp_readb_base(atpdev, 0x29);
  1317. atp_writeb_base(atpdev, 0x29, c & 0xfb);
  1318. for (c = 0; c < 2; c++) {
  1319. atpdev->ultra_map[c] = 0;
  1320. atpdev->async[c] = 0;
  1321. for (k = 0; k < 16; k++) {
  1322. n = 1 << k;
  1323. if (atpdev->sp[c][k] > 1)
  1324. atpdev->ultra_map[c] |= n;
  1325. else
  1326. if (atpdev->sp[c][k] == 0)
  1327. atpdev->async[c] |= n;
  1328. }
  1329. atpdev->async[c] = ~(atpdev->async[c]);
  1330. if (atpdev->global_map[c] == 0) {
  1331. k = setupdata[c][1];
  1332. if ((k & 0x40) != 0)
  1333. atpdev->global_map[c] |= 0x20;
  1334. k &= 0x07;
  1335. atpdev->global_map[c] |= k;
  1336. if ((setupdata[c][2] & 0x04) != 0)
  1337. atpdev->global_map[c] |= 0x08;
  1338. atpdev->host_id[c] = setupdata[c][0] & 0x07;
  1339. }
  1340. }
  1341. k = atp_readb_base(atpdev, 0x28) & 0x8f;
  1342. k |= 0x10;
  1343. atp_writeb_base(atpdev, 0x28, k);
  1344. atp_writeb_pci(atpdev, 0, 1, 0x80);
  1345. atp_writeb_pci(atpdev, 1, 1, 0x80);
  1346. msleep(100);
  1347. atp_writeb_pci(atpdev, 0, 1, 0);
  1348. atp_writeb_pci(atpdev, 1, 1, 0);
  1349. msleep(1000);
  1350. atp_readb_io(atpdev, 0, 0x1b);
  1351. atp_readb_io(atpdev, 0, 0x17);
  1352. atp_readb_io(atpdev, 1, 0x1b);
  1353. atp_readb_io(atpdev, 1, 0x17);
  1354. k = atpdev->host_id[0];
  1355. if (k > 7)
  1356. k = (k & 0x07) | 0x40;
  1357. atp_set_host_id(atpdev, 0, k);
  1358. k = atpdev->host_id[1];
  1359. if (k > 7)
  1360. k = (k & 0x07) | 0x40;
  1361. atp_set_host_id(atpdev, 1, k);
  1362. msleep(600); /* this delay used to be called tscam_885() */
  1363. dev_info(&pdev->dev, "Scanning Channel A SCSI Device ...\n");
  1364. atp_is(atpdev, 0, true, atp_readb_io(atpdev, 0, 0x1b) >> 7);
  1365. atp_writeb_io(atpdev, 0, 0x16, 0x80);
  1366. dev_info(&pdev->dev, "Scanning Channel B SCSI Device ...\n");
  1367. atp_is(atpdev, 1, true, atp_readb_io(atpdev, 1, 0x1b) >> 7);
  1368. atp_writeb_io(atpdev, 1, 0x16, 0x80);
  1369. k = atp_readb_base(atpdev, 0x28) & 0xcf;
  1370. k |= 0xc0;
  1371. atp_writeb_base(atpdev, 0x28, k);
  1372. k = atp_readb_base(atpdev, 0x1f) | 0x80;
  1373. atp_writeb_base(atpdev, 0x1f, k);
  1374. k = atp_readb_base(atpdev, 0x29) | 0x01;
  1375. atp_writeb_base(atpdev, 0x29, k);
  1376. shpnt->max_id = 16;
  1377. shpnt->max_lun = (atpdev->global_map[0] & 0x07) + 1;
  1378. shpnt->max_channel = 1;
  1379. shpnt->this_id = atpdev->host_id[0];
  1380. }
  1381. /* return non-zero on detection */
  1382. static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1383. {
  1384. struct Scsi_Host *shpnt = NULL;
  1385. struct atp_unit *atpdev;
  1386. int err;
  1387. if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610 && pdev->revision < 2) {
  1388. dev_err(&pdev->dev, "ATP850S chips (AEC6710L/F cards) are not supported.\n");
  1389. return -ENODEV;
  1390. }
  1391. err = pci_enable_device(pdev);
  1392. if (err)
  1393. goto fail;
  1394. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
  1395. printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
  1396. err = -EIO;
  1397. goto disable_device;
  1398. }
  1399. err = pci_request_regions(pdev, "atp870u");
  1400. if (err)
  1401. goto disable_device;
  1402. pci_set_master(pdev);
  1403. err = -ENOMEM;
  1404. shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
  1405. if (!shpnt)
  1406. goto release_region;
  1407. atpdev = shost_priv(shpnt);
  1408. atpdev->host = shpnt;
  1409. atpdev->pdev = pdev;
  1410. pci_set_drvdata(pdev, atpdev);
  1411. shpnt->io_port = pci_resource_start(pdev, 0);
  1412. shpnt->io_port &= 0xfffffff8;
  1413. shpnt->n_io_port = pci_resource_len(pdev, 0);
  1414. atpdev->baseport = shpnt->io_port;
  1415. shpnt->unique_id = shpnt->io_port;
  1416. shpnt->irq = pdev->irq;
  1417. err = atp870u_init_tables(shpnt);
  1418. if (err) {
  1419. dev_err(&pdev->dev, "Unable to allocate tables for Acard controller\n");
  1420. goto unregister;
  1421. }
  1422. if (is880(atpdev))
  1423. atp880_init(shpnt);
  1424. else if (is885(atpdev))
  1425. atp885_init(shpnt);
  1426. else
  1427. atp870_init(shpnt);
  1428. err = request_irq(shpnt->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt);
  1429. if (err) {
  1430. dev_err(&pdev->dev, "Unable to allocate IRQ %d.\n", shpnt->irq);
  1431. goto free_tables;
  1432. }
  1433. err = scsi_add_host(shpnt, &pdev->dev);
  1434. if (err)
  1435. goto scsi_add_fail;
  1436. scsi_scan_host(shpnt);
  1437. return 0;
  1438. scsi_add_fail:
  1439. free_irq(shpnt->irq, shpnt);
  1440. free_tables:
  1441. atp870u_free_tables(shpnt);
  1442. unregister:
  1443. scsi_host_put(shpnt);
  1444. release_region:
  1445. pci_release_regions(pdev);
  1446. disable_device:
  1447. pci_disable_device(pdev);
  1448. fail:
  1449. return err;
  1450. }
  1451. /* The abort command does not leave the device in a clean state where
  1452. it is available to be used again. Until this gets worked out, we will
  1453. leave it commented out. */
  1454. static int atp870u_abort(struct scsi_cmnd * SCpnt)
  1455. {
  1456. unsigned char j, k, c;
  1457. struct scsi_cmnd *workrequ;
  1458. struct atp_unit *dev;
  1459. struct Scsi_Host *host;
  1460. host = SCpnt->device->host;
  1461. dev = (struct atp_unit *)&host->hostdata;
  1462. c = scmd_channel(SCpnt);
  1463. printk(" atp870u: abort Channel = %x \n", c);
  1464. printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
  1465. printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
  1466. for (j = 0; j < 0x18; j++) {
  1467. printk(" r%2x=%2x", j, atp_readb_io(dev, c, j));
  1468. }
  1469. printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c));
  1470. printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]);
  1471. printk(" d00=%2x", atp_readb_pci(dev, c, 0x00));
  1472. printk(" d02=%2x", atp_readb_pci(dev, c, 0x02));
  1473. for(j=0;j<16;j++) {
  1474. if (dev->id[c][j].curr_req != NULL) {
  1475. workrequ = dev->id[c][j].curr_req;
  1476. printk("\n que cdb= ");
  1477. for (k=0; k < workrequ->cmd_len; k++) {
  1478. printk(" %2x ",workrequ->cmnd[k]);
  1479. }
  1480. printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
  1481. }
  1482. }
  1483. return SUCCESS;
  1484. }
  1485. static const char *atp870u_info(struct Scsi_Host *notused)
  1486. {
  1487. static char buffer[128];
  1488. strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
  1489. return buffer;
  1490. }
  1491. static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr)
  1492. {
  1493. seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n"
  1494. "Adapter Configuration:\n");
  1495. seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port);
  1496. seq_printf(m, " IRQ: %d\n", HBAptr->irq);
  1497. return 0;
  1498. }
  1499. static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
  1500. sector_t capacity, int *ip)
  1501. {
  1502. int heads, sectors, cylinders;
  1503. heads = 64;
  1504. sectors = 32;
  1505. cylinders = (unsigned long)capacity / (heads * sectors);
  1506. if (cylinders > 1024) {
  1507. heads = 255;
  1508. sectors = 63;
  1509. cylinders = (unsigned long)capacity / (heads * sectors);
  1510. }
  1511. ip[0] = heads;
  1512. ip[1] = sectors;
  1513. ip[2] = cylinders;
  1514. return 0;
  1515. }
  1516. static void atp870u_remove (struct pci_dev *pdev)
  1517. {
  1518. struct atp_unit *devext = pci_get_drvdata(pdev);
  1519. struct Scsi_Host *pshost = devext->host;
  1520. scsi_remove_host(pshost);
  1521. free_irq(pshost->irq, pshost);
  1522. pci_release_regions(pdev);
  1523. pci_disable_device(pdev);
  1524. atp870u_free_tables(pshost);
  1525. scsi_host_put(pshost);
  1526. }
  1527. MODULE_LICENSE("GPL");
  1528. static struct scsi_host_template atp870u_template = {
  1529. .module = THIS_MODULE,
  1530. .name = "atp870u" /* name */,
  1531. .proc_name = "atp870u",
  1532. .show_info = atp870u_show_info,
  1533. .info = atp870u_info /* info */,
  1534. .queuecommand = atp870u_queuecommand /* queuecommand */,
  1535. .eh_abort_handler = atp870u_abort /* abort */,
  1536. .bios_param = atp870u_biosparam /* biosparm */,
  1537. .can_queue = qcnt /* can_queue */,
  1538. .this_id = 7 /* SCSI ID */,
  1539. .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/,
  1540. .max_sectors = ATP870U_MAX_SECTORS,
  1541. };
  1542. static struct pci_device_id atp870u_id_table[] = {
  1543. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) },
  1544. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) },
  1545. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) },
  1546. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) },
  1547. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) },
  1548. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) },
  1549. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) },
  1550. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) },
  1551. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
  1552. { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) },
  1553. { 0, },
  1554. };
  1555. MODULE_DEVICE_TABLE(pci, atp870u_id_table);
  1556. static struct pci_driver atp870u_driver = {
  1557. .id_table = atp870u_id_table,
  1558. .name = "atp870u",
  1559. .probe = atp870u_probe,
  1560. .remove = atp870u_remove,
  1561. };
  1562. module_pci_driver(atp870u_driver);
  1563. static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, unsigned char lvdmode)
  1564. {
  1565. unsigned char i, j, k, rmb, n;
  1566. unsigned short int m;
  1567. static unsigned char mbuf[512];
  1568. static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
  1569. static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
  1570. static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
  1571. unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
  1572. static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
  1573. static unsigned char synw_870[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
  1574. unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
  1575. static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
  1576. static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
  1577. for (i = 0; i < 16; i++) {
  1578. if (!wide_chip && (i > 7))
  1579. break;
  1580. m = 1;
  1581. m = m << i;
  1582. if ((m & dev->active_id[c]) != 0) {
  1583. continue;
  1584. }
  1585. if (i == dev->host_id[c]) {
  1586. printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
  1587. continue;
  1588. }
  1589. atp_writeb_io(dev, c, 0x1b, wide_chip ? 0x01 : 0x00);
  1590. atp_writeb_io(dev, c, 1, 0x08);
  1591. atp_writeb_io(dev, c, 2, 0x7f);
  1592. atp_writeb_io(dev, c, 3, satn[0]);
  1593. atp_writeb_io(dev, c, 4, satn[1]);
  1594. atp_writeb_io(dev, c, 5, satn[2]);
  1595. atp_writeb_io(dev, c, 6, satn[3]);
  1596. atp_writeb_io(dev, c, 7, satn[4]);
  1597. atp_writeb_io(dev, c, 8, satn[5]);
  1598. atp_writeb_io(dev, c, 0x0f, 0);
  1599. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1600. atp_writeb_io(dev, c, 0x12, 0);
  1601. atp_writeb_io(dev, c, 0x13, satn[6]);
  1602. atp_writeb_io(dev, c, 0x14, satn[7]);
  1603. j = i;
  1604. if ((j & 0x08) != 0) {
  1605. j = (j & 0x07) | 0x40;
  1606. }
  1607. atp_writeb_io(dev, c, 0x15, j);
  1608. atp_writeb_io(dev, c, 0x18, satn[8]);
  1609. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1610. cpu_relax();
  1611. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1612. continue;
  1613. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1614. cpu_relax();
  1615. dev->active_id[c] |= m;
  1616. atp_writeb_io(dev, c, 0x10, 0x30);
  1617. if (is885(dev) || is880(dev))
  1618. atp_writeb_io(dev, c, 0x14, 0x00);
  1619. else /* result of is870() merge - is this a bug? */
  1620. atp_writeb_io(dev, c, 0x04, 0x00);
  1621. phase_cmd:
  1622. atp_writeb_io(dev, c, 0x18, 0x08);
  1623. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1624. cpu_relax();
  1625. j = atp_readb_io(dev, c, 0x17);
  1626. if (j != 0x16) {
  1627. atp_writeb_io(dev, c, 0x10, 0x41);
  1628. goto phase_cmd;
  1629. }
  1630. sel_ok:
  1631. atp_writeb_io(dev, c, 3, inqd[0]);
  1632. atp_writeb_io(dev, c, 4, inqd[1]);
  1633. atp_writeb_io(dev, c, 5, inqd[2]);
  1634. atp_writeb_io(dev, c, 6, inqd[3]);
  1635. atp_writeb_io(dev, c, 7, inqd[4]);
  1636. atp_writeb_io(dev, c, 8, inqd[5]);
  1637. atp_writeb_io(dev, c, 0x0f, 0);
  1638. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1639. atp_writeb_io(dev, c, 0x12, 0);
  1640. atp_writeb_io(dev, c, 0x13, inqd[6]);
  1641. atp_writeb_io(dev, c, 0x14, inqd[7]);
  1642. atp_writeb_io(dev, c, 0x18, inqd[8]);
  1643. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1644. cpu_relax();
  1645. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1646. continue;
  1647. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1648. cpu_relax();
  1649. if (wide_chip)
  1650. atp_writeb_io(dev, c, 0x1b, 0x00);
  1651. atp_writeb_io(dev, c, 0x18, 0x08);
  1652. j = 0;
  1653. rd_inq_data:
  1654. k = atp_readb_io(dev, c, 0x1f);
  1655. if ((k & 0x01) != 0) {
  1656. mbuf[j++] = atp_readb_io(dev, c, 0x19);
  1657. goto rd_inq_data;
  1658. }
  1659. if ((k & 0x80) == 0) {
  1660. goto rd_inq_data;
  1661. }
  1662. j = atp_readb_io(dev, c, 0x17);
  1663. if (j == 0x16) {
  1664. goto inq_ok;
  1665. }
  1666. atp_writeb_io(dev, c, 0x10, 0x46);
  1667. atp_writeb_io(dev, c, 0x12, 0);
  1668. atp_writeb_io(dev, c, 0x13, 0);
  1669. atp_writeb_io(dev, c, 0x14, 0);
  1670. atp_writeb_io(dev, c, 0x18, 0x08);
  1671. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1672. cpu_relax();
  1673. if (atp_readb_io(dev, c, 0x17) != 0x16)
  1674. goto sel_ok;
  1675. inq_ok:
  1676. mbuf[36] = 0;
  1677. printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
  1678. dev->id[c][i].devtype = mbuf[0];
  1679. rmb = mbuf[1];
  1680. n = mbuf[7];
  1681. if (!wide_chip)
  1682. goto not_wide;
  1683. if ((mbuf[7] & 0x60) == 0) {
  1684. goto not_wide;
  1685. }
  1686. if (is885(dev) || is880(dev)) {
  1687. if ((i < 8) && ((dev->global_map[c] & 0x20) == 0))
  1688. goto not_wide;
  1689. } else { /* result of is870() merge - is this a bug? */
  1690. if ((dev->global_map[c] & 0x20) == 0)
  1691. goto not_wide;
  1692. }
  1693. if (lvdmode == 0) {
  1694. goto chg_wide;
  1695. }
  1696. if (dev->sp[c][i] != 0x04) // force u2
  1697. {
  1698. goto chg_wide;
  1699. }
  1700. atp_writeb_io(dev, c, 0x1b, 0x01);
  1701. atp_writeb_io(dev, c, 3, satn[0]);
  1702. atp_writeb_io(dev, c, 4, satn[1]);
  1703. atp_writeb_io(dev, c, 5, satn[2]);
  1704. atp_writeb_io(dev, c, 6, satn[3]);
  1705. atp_writeb_io(dev, c, 7, satn[4]);
  1706. atp_writeb_io(dev, c, 8, satn[5]);
  1707. atp_writeb_io(dev, c, 0x0f, 0);
  1708. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1709. atp_writeb_io(dev, c, 0x12, 0);
  1710. atp_writeb_io(dev, c, 0x13, satn[6]);
  1711. atp_writeb_io(dev, c, 0x14, satn[7]);
  1712. atp_writeb_io(dev, c, 0x18, satn[8]);
  1713. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1714. cpu_relax();
  1715. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1716. continue;
  1717. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1718. cpu_relax();
  1719. try_u3:
  1720. j = 0;
  1721. atp_writeb_io(dev, c, 0x14, 0x09);
  1722. atp_writeb_io(dev, c, 0x18, 0x20);
  1723. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1724. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1725. atp_writeb_io(dev, c, 0x19, u3[j++]);
  1726. cpu_relax();
  1727. }
  1728. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
  1729. cpu_relax();
  1730. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1731. if (j == 0x0f) {
  1732. goto u3p_in;
  1733. }
  1734. if (j == 0x0a) {
  1735. goto u3p_cmd;
  1736. }
  1737. if (j == 0x0e) {
  1738. goto try_u3;
  1739. }
  1740. continue;
  1741. u3p_out:
  1742. atp_writeb_io(dev, c, 0x18, 0x20);
  1743. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1744. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1745. atp_writeb_io(dev, c, 0x19, 0);
  1746. cpu_relax();
  1747. }
  1748. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1749. if (j == 0x0f) {
  1750. goto u3p_in;
  1751. }
  1752. if (j == 0x0a) {
  1753. goto u3p_cmd;
  1754. }
  1755. if (j == 0x0e) {
  1756. goto u3p_out;
  1757. }
  1758. continue;
  1759. u3p_in:
  1760. atp_writeb_io(dev, c, 0x14, 0x09);
  1761. atp_writeb_io(dev, c, 0x18, 0x20);
  1762. k = 0;
  1763. u3p_in1:
  1764. j = atp_readb_io(dev, c, 0x1f);
  1765. if ((j & 0x01) != 0) {
  1766. mbuf[k++] = atp_readb_io(dev, c, 0x19);
  1767. goto u3p_in1;
  1768. }
  1769. if ((j & 0x80) == 0x00) {
  1770. goto u3p_in1;
  1771. }
  1772. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1773. if (j == 0x0f) {
  1774. goto u3p_in;
  1775. }
  1776. if (j == 0x0a) {
  1777. goto u3p_cmd;
  1778. }
  1779. if (j == 0x0e) {
  1780. goto u3p_out;
  1781. }
  1782. continue;
  1783. u3p_cmd:
  1784. atp_writeb_io(dev, c, 0x10, 0x30);
  1785. atp_writeb_io(dev, c, 0x14, 0x00);
  1786. atp_writeb_io(dev, c, 0x18, 0x08);
  1787. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00);
  1788. j = atp_readb_io(dev, c, 0x17);
  1789. if (j != 0x16) {
  1790. if (j == 0x4e) {
  1791. goto u3p_out;
  1792. }
  1793. continue;
  1794. }
  1795. if (mbuf[0] != 0x01) {
  1796. goto chg_wide;
  1797. }
  1798. if (mbuf[1] != 0x06) {
  1799. goto chg_wide;
  1800. }
  1801. if (mbuf[2] != 0x04) {
  1802. goto chg_wide;
  1803. }
  1804. if (mbuf[3] == 0x09) {
  1805. m = 1;
  1806. m = m << i;
  1807. dev->wide_id[c] |= m;
  1808. dev->id[c][i].devsp = 0xce;
  1809. #ifdef ED_DBGP
  1810. printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
  1811. #endif
  1812. continue;
  1813. }
  1814. chg_wide:
  1815. atp_writeb_io(dev, c, 0x1b, 0x01);
  1816. atp_writeb_io(dev, c, 3, satn[0]);
  1817. atp_writeb_io(dev, c, 4, satn[1]);
  1818. atp_writeb_io(dev, c, 5, satn[2]);
  1819. atp_writeb_io(dev, c, 6, satn[3]);
  1820. atp_writeb_io(dev, c, 7, satn[4]);
  1821. atp_writeb_io(dev, c, 8, satn[5]);
  1822. atp_writeb_io(dev, c, 0x0f, 0);
  1823. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1824. atp_writeb_io(dev, c, 0x12, 0);
  1825. atp_writeb_io(dev, c, 0x13, satn[6]);
  1826. atp_writeb_io(dev, c, 0x14, satn[7]);
  1827. atp_writeb_io(dev, c, 0x18, satn[8]);
  1828. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1829. cpu_relax();
  1830. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1831. continue;
  1832. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1833. cpu_relax();
  1834. try_wide:
  1835. j = 0;
  1836. atp_writeb_io(dev, c, 0x14, 0x05);
  1837. atp_writeb_io(dev, c, 0x18, 0x20);
  1838. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1839. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1840. atp_writeb_io(dev, c, 0x19, wide[j++]);
  1841. cpu_relax();
  1842. }
  1843. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
  1844. cpu_relax();
  1845. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1846. if (j == 0x0f) {
  1847. goto widep_in;
  1848. }
  1849. if (j == 0x0a) {
  1850. goto widep_cmd;
  1851. }
  1852. if (j == 0x0e) {
  1853. goto try_wide;
  1854. }
  1855. continue;
  1856. widep_out:
  1857. atp_writeb_io(dev, c, 0x18, 0x20);
  1858. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1859. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0)
  1860. atp_writeb_io(dev, c, 0x19, 0);
  1861. cpu_relax();
  1862. }
  1863. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1864. if (j == 0x0f) {
  1865. goto widep_in;
  1866. }
  1867. if (j == 0x0a) {
  1868. goto widep_cmd;
  1869. }
  1870. if (j == 0x0e) {
  1871. goto widep_out;
  1872. }
  1873. continue;
  1874. widep_in:
  1875. atp_writeb_io(dev, c, 0x14, 0xff);
  1876. atp_writeb_io(dev, c, 0x18, 0x20);
  1877. k = 0;
  1878. widep_in1:
  1879. j = atp_readb_io(dev, c, 0x1f);
  1880. if ((j & 0x01) != 0) {
  1881. mbuf[k++] = atp_readb_io(dev, c, 0x19);
  1882. goto widep_in1;
  1883. }
  1884. if ((j & 0x80) == 0x00) {
  1885. goto widep_in1;
  1886. }
  1887. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1888. if (j == 0x0f) {
  1889. goto widep_in;
  1890. }
  1891. if (j == 0x0a) {
  1892. goto widep_cmd;
  1893. }
  1894. if (j == 0x0e) {
  1895. goto widep_out;
  1896. }
  1897. continue;
  1898. widep_cmd:
  1899. atp_writeb_io(dev, c, 0x10, 0x30);
  1900. atp_writeb_io(dev, c, 0x14, 0x00);
  1901. atp_writeb_io(dev, c, 0x18, 0x08);
  1902. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1903. cpu_relax();
  1904. j = atp_readb_io(dev, c, 0x17);
  1905. if (j != 0x16) {
  1906. if (j == 0x4e) {
  1907. goto widep_out;
  1908. }
  1909. continue;
  1910. }
  1911. if (mbuf[0] != 0x01) {
  1912. goto not_wide;
  1913. }
  1914. if (mbuf[1] != 0x02) {
  1915. goto not_wide;
  1916. }
  1917. if (mbuf[2] != 0x03) {
  1918. goto not_wide;
  1919. }
  1920. if (mbuf[3] != 0x01) {
  1921. goto not_wide;
  1922. }
  1923. m = 1;
  1924. m = m << i;
  1925. dev->wide_id[c] |= m;
  1926. not_wide:
  1927. if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) || ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
  1928. m = 1;
  1929. m = m << i;
  1930. if ((dev->async[c] & m) != 0) {
  1931. goto set_sync;
  1932. }
  1933. }
  1934. continue;
  1935. set_sync:
  1936. if ((!is885(dev) && !is880(dev)) || (dev->sp[c][i] == 0x02)) {
  1937. synu[4] = 0x0c;
  1938. synuw[4] = 0x0c;
  1939. } else {
  1940. if (dev->sp[c][i] >= 0x03) {
  1941. synu[4] = 0x0a;
  1942. synuw[4] = 0x0a;
  1943. }
  1944. }
  1945. j = 0;
  1946. if ((m & dev->wide_id[c]) != 0) {
  1947. j |= 0x01;
  1948. }
  1949. atp_writeb_io(dev, c, 0x1b, j);
  1950. atp_writeb_io(dev, c, 3, satn[0]);
  1951. atp_writeb_io(dev, c, 4, satn[1]);
  1952. atp_writeb_io(dev, c, 5, satn[2]);
  1953. atp_writeb_io(dev, c, 6, satn[3]);
  1954. atp_writeb_io(dev, c, 7, satn[4]);
  1955. atp_writeb_io(dev, c, 8, satn[5]);
  1956. atp_writeb_io(dev, c, 0x0f, 0);
  1957. atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp);
  1958. atp_writeb_io(dev, c, 0x12, 0);
  1959. atp_writeb_io(dev, c, 0x13, satn[6]);
  1960. atp_writeb_io(dev, c, 0x14, satn[7]);
  1961. atp_writeb_io(dev, c, 0x18, satn[8]);
  1962. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  1963. cpu_relax();
  1964. if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e)
  1965. continue;
  1966. while (atp_readb_io(dev, c, 0x17) != 0x8e)
  1967. cpu_relax();
  1968. try_sync:
  1969. j = 0;
  1970. atp_writeb_io(dev, c, 0x14, 0x06);
  1971. atp_writeb_io(dev, c, 0x18, 0x20);
  1972. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) {
  1973. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) {
  1974. if ((m & dev->wide_id[c]) != 0) {
  1975. if (is885(dev) || is880(dev)) {
  1976. if ((m & dev->ultra_map[c]) != 0) {
  1977. atp_writeb_io(dev, c, 0x19, synuw[j++]);
  1978. } else {
  1979. atp_writeb_io(dev, c, 0x19, synw[j++]);
  1980. }
  1981. } else
  1982. atp_writeb_io(dev, c, 0x19, synw_870[j++]);
  1983. } else {
  1984. if ((m & dev->ultra_map[c]) != 0) {
  1985. atp_writeb_io(dev, c, 0x19, synu[j++]);
  1986. } else {
  1987. atp_writeb_io(dev, c, 0x19, synn[j++]);
  1988. }
  1989. }
  1990. }
  1991. }
  1992. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00)
  1993. cpu_relax();
  1994. j = atp_readb_io(dev, c, 0x17) & 0x0f;
  1995. if (j == 0x0f) {
  1996. goto phase_ins;
  1997. }
  1998. if (j == 0x0a) {
  1999. goto phase_cmds;
  2000. }
  2001. if (j == 0x0e) {
  2002. goto try_sync;
  2003. }
  2004. continue;
  2005. phase_outs:
  2006. atp_writeb_io(dev, c, 0x18, 0x20);
  2007. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) {
  2008. if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00)
  2009. atp_writeb_io(dev, c, 0x19, 0x00);
  2010. cpu_relax();
  2011. }
  2012. j = atp_readb_io(dev, c, 0x17);
  2013. if (j == 0x85) {
  2014. goto tar_dcons;
  2015. }
  2016. j &= 0x0f;
  2017. if (j == 0x0f) {
  2018. goto phase_ins;
  2019. }
  2020. if (j == 0x0a) {
  2021. goto phase_cmds;
  2022. }
  2023. if (j == 0x0e) {
  2024. goto phase_outs;
  2025. }
  2026. continue;
  2027. phase_ins:
  2028. if (is885(dev) || is880(dev))
  2029. atp_writeb_io(dev, c, 0x14, 0x06);
  2030. else
  2031. atp_writeb_io(dev, c, 0x14, 0xff);
  2032. atp_writeb_io(dev, c, 0x18, 0x20);
  2033. k = 0;
  2034. phase_ins1:
  2035. j = atp_readb_io(dev, c, 0x1f);
  2036. if ((j & 0x01) != 0x00) {
  2037. mbuf[k++] = atp_readb_io(dev, c, 0x19);
  2038. goto phase_ins1;
  2039. }
  2040. if ((j & 0x80) == 0x00) {
  2041. goto phase_ins1;
  2042. }
  2043. while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00);
  2044. j = atp_readb_io(dev, c, 0x17);
  2045. if (j == 0x85) {
  2046. goto tar_dcons;
  2047. }
  2048. j &= 0x0f;
  2049. if (j == 0x0f) {
  2050. goto phase_ins;
  2051. }
  2052. if (j == 0x0a) {
  2053. goto phase_cmds;
  2054. }
  2055. if (j == 0x0e) {
  2056. goto phase_outs;
  2057. }
  2058. continue;
  2059. phase_cmds:
  2060. atp_writeb_io(dev, c, 0x10, 0x30);
  2061. tar_dcons:
  2062. atp_writeb_io(dev, c, 0x14, 0x00);
  2063. atp_writeb_io(dev, c, 0x18, 0x08);
  2064. while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00)
  2065. cpu_relax();
  2066. j = atp_readb_io(dev, c, 0x17);
  2067. if (j != 0x16) {
  2068. continue;
  2069. }
  2070. if (mbuf[0] != 0x01) {
  2071. continue;
  2072. }
  2073. if (mbuf[1] != 0x03) {
  2074. continue;
  2075. }
  2076. if (mbuf[4] == 0x00) {
  2077. continue;
  2078. }
  2079. if (mbuf[3] > 0x64) {
  2080. continue;
  2081. }
  2082. if (is885(dev) || is880(dev)) {
  2083. if (mbuf[4] > 0x0e) {
  2084. mbuf[4] = 0x0e;
  2085. }
  2086. } else {
  2087. if (mbuf[4] > 0x0c) {
  2088. mbuf[4] = 0x0c;
  2089. }
  2090. }
  2091. dev->id[c][i].devsp = mbuf[4];
  2092. if (is885(dev) || is880(dev))
  2093. if (mbuf[3] < 0x0c) {
  2094. j = 0xb0;
  2095. goto set_syn_ok;
  2096. }
  2097. if ((mbuf[3] < 0x0d) && (rmb == 0)) {
  2098. j = 0xa0;
  2099. goto set_syn_ok;
  2100. }
  2101. if (mbuf[3] < 0x1a) {
  2102. j = 0x20;
  2103. goto set_syn_ok;
  2104. }
  2105. if (mbuf[3] < 0x33) {
  2106. j = 0x40;
  2107. goto set_syn_ok;
  2108. }
  2109. if (mbuf[3] < 0x4c) {
  2110. j = 0x50;
  2111. goto set_syn_ok;
  2112. }
  2113. j = 0x60;
  2114. set_syn_ok:
  2115. dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
  2116. #ifdef ED_DBGP
  2117. printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
  2118. #endif
  2119. }
  2120. }