NCR5380.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * NCR 5380 defines
  4. *
  5. * Copyright 1993, Drew Eckhardt
  6. * Visionary Computing
  7. * (Unix consulting and custom programming)
  8. * drew@colorado.edu
  9. * +1 (303) 666-5836
  10. *
  11. * For more information, please consult
  12. *
  13. * NCR 5380 Family
  14. * SCSI Protocol Controller
  15. * Databook
  16. * NCR Microelectronics
  17. * 1635 Aeroplaza Drive
  18. * Colorado Springs, CO 80916
  19. * 1+ (719) 578-3400
  20. * 1+ (800) 334-5454
  21. */
  22. #ifndef NCR5380_H
  23. #define NCR5380_H
  24. #include <linux/delay.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/workqueue.h>
  28. #include <scsi/scsi_dbg.h>
  29. #include <scsi/scsi_eh.h>
  30. #include <scsi/scsi_transport_spi.h>
  31. #define NDEBUG_ARBITRATION 0x1
  32. #define NDEBUG_AUTOSENSE 0x2
  33. #define NDEBUG_DMA 0x4
  34. #define NDEBUG_HANDSHAKE 0x8
  35. #define NDEBUG_INFORMATION 0x10
  36. #define NDEBUG_INIT 0x20
  37. #define NDEBUG_INTR 0x40
  38. #define NDEBUG_LINKED 0x80
  39. #define NDEBUG_MAIN 0x100
  40. #define NDEBUG_NO_DATAOUT 0x200
  41. #define NDEBUG_NO_WRITE 0x400
  42. #define NDEBUG_PIO 0x800
  43. #define NDEBUG_PSEUDO_DMA 0x1000
  44. #define NDEBUG_QUEUES 0x2000
  45. #define NDEBUG_RESELECTION 0x4000
  46. #define NDEBUG_SELECTION 0x8000
  47. #define NDEBUG_USLEEP 0x10000
  48. #define NDEBUG_LAST_BYTE_SENT 0x20000
  49. #define NDEBUG_RESTART_SELECT 0x40000
  50. #define NDEBUG_EXTENDED 0x80000
  51. #define NDEBUG_C400_PREAD 0x100000
  52. #define NDEBUG_C400_PWRITE 0x200000
  53. #define NDEBUG_LISTS 0x400000
  54. #define NDEBUG_ABORT 0x800000
  55. #define NDEBUG_TAGS 0x1000000
  56. #define NDEBUG_MERGING 0x2000000
  57. #define NDEBUG_ANY 0xFFFFFFFFUL
  58. /*
  59. * The contents of the OUTPUT DATA register are asserted on the bus when
  60. * either arbitration is occurring or the phase-indicating signals (
  61. * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  62. * bit in the INITIATOR COMMAND register is set.
  63. */
  64. #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
  65. #define CURRENT_SCSI_DATA_REG 0 /* ro same */
  66. #define INITIATOR_COMMAND_REG 1 /* rw */
  67. #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
  68. #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
  69. #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
  70. #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
  71. #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
  72. #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
  73. #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
  74. #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
  75. #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
  76. #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
  77. #define ICR_BASE 0
  78. #define MODE_REG 2
  79. /*
  80. * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
  81. * transfer, causing the chip to hog the bus. You probably don't want
  82. * this.
  83. */
  84. #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
  85. #define MR_TARGET 0x40 /* rw target mode */
  86. #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
  87. #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
  88. #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
  89. #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
  90. #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
  91. #define MR_ARBITRATE 0x01 /* rw start arbitration */
  92. #define MR_BASE 0
  93. #define TARGET_COMMAND_REG 3
  94. #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
  95. #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
  96. #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
  97. #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
  98. #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
  99. #define STATUS_REG 4 /* ro */
  100. /*
  101. * Note : a set bit indicates an active signal, driven by us or another
  102. * device.
  103. */
  104. #define SR_RST 0x80
  105. #define SR_BSY 0x40
  106. #define SR_REQ 0x20
  107. #define SR_MSG 0x10
  108. #define SR_CD 0x08
  109. #define SR_IO 0x04
  110. #define SR_SEL 0x02
  111. #define SR_DBP 0x01
  112. /*
  113. * Setting a bit in this register will cause an interrupt to be generated when
  114. * BSY is false and SEL true and this bit is asserted on the bus.
  115. */
  116. #define SELECT_ENABLE_REG 4 /* wo */
  117. #define BUS_AND_STATUS_REG 5 /* ro */
  118. #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
  119. #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
  120. #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
  121. #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
  122. #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
  123. #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
  124. #define BASR_ATN 0x02 /* ro BUS status */
  125. #define BASR_ACK 0x01 /* ro BUS status */
  126. /* Write any value to this register to start a DMA send */
  127. #define START_DMA_SEND_REG 5 /* wo */
  128. /*
  129. * Used in DMA transfer mode, data is latched from the SCSI bus on
  130. * the falling edge of REQ (ini) or ACK (tgt)
  131. */
  132. #define INPUT_DATA_REG 6 /* ro */
  133. /* Write any value to this register to start a DMA receive */
  134. #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
  135. /* Read this register to clear interrupt conditions */
  136. #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
  137. /* Write any value to this register to start an ini mode DMA receive */
  138. #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
  139. /* NCR 53C400(A) Control Status Register bits: */
  140. #define CSR_RESET 0x80 /* wo Resets 53c400 */
  141. #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
  142. #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
  143. #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
  144. #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
  145. #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
  146. #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
  147. #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
  148. #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
  149. #define CSR_BASE CSR_53C80_INTR
  150. /* Note : PHASE_* macros are based on the values of the STATUS register */
  151. #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
  152. #define PHASE_DATAOUT 0
  153. #define PHASE_DATAIN SR_IO
  154. #define PHASE_CMDOUT SR_CD
  155. #define PHASE_STATIN (SR_CD | SR_IO)
  156. #define PHASE_MSGOUT (SR_MSG | SR_CD)
  157. #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
  158. #define PHASE_UNKNOWN 0xff
  159. /*
  160. * Convert status register phase to something we can use to set phase in
  161. * the target register so we can get phase mismatch interrupts on DMA
  162. * transfers.
  163. */
  164. #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
  165. #ifndef NO_IRQ
  166. #define NO_IRQ 0
  167. #endif
  168. #define FLAG_DMA_FIXUP 1 /* Use DMA errata workarounds */
  169. #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
  170. #define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
  171. #define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */
  172. struct NCR5380_hostdata {
  173. NCR5380_implementation_fields; /* Board-specific data */
  174. u8 __iomem *io; /* Remapped 5380 address */
  175. u8 __iomem *pdma_io; /* Remapped PDMA address */
  176. unsigned long poll_loops; /* Register polling limit */
  177. spinlock_t lock; /* Protects this struct */
  178. struct scsi_cmnd *connected; /* Currently connected cmnd */
  179. struct list_head disconnected; /* Waiting for reconnect */
  180. struct Scsi_Host *host; /* SCSI host backpointer */
  181. struct workqueue_struct *work_q; /* SCSI host work queue */
  182. struct work_struct main_task; /* Work item for main loop */
  183. int flags; /* Board-specific quirks */
  184. int dma_len; /* Requested length of DMA */
  185. int read_overruns; /* Transfer size reduction for DMA erratum */
  186. unsigned long io_port; /* Device IO port */
  187. unsigned long base; /* Device base address */
  188. struct list_head unissued; /* Waiting to be issued */
  189. struct scsi_cmnd *selecting; /* Cmnd to be connected */
  190. struct list_head autosense; /* Priority cmnd queue */
  191. struct scsi_cmnd *sensing; /* Cmnd needing autosense */
  192. struct scsi_eh_save ses; /* Cmnd state saved for EH */
  193. unsigned char busy[8]; /* Index = target, bit = lun */
  194. unsigned char id_mask; /* 1 << Host ID */
  195. unsigned char id_higher_mask; /* All bits above id_mask */
  196. unsigned char last_message; /* Last Message Out */
  197. unsigned long region_size; /* Size of address/port range */
  198. char info[168]; /* Host banner message */
  199. };
  200. struct NCR5380_cmd {
  201. struct list_head list;
  202. };
  203. #define NCR5380_CMD_SIZE (sizeof(struct NCR5380_cmd))
  204. #define NCR5380_PIO_CHUNK_SIZE 256
  205. /* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */
  206. #define NCR5380_REG_POLL_TIME 10
  207. static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
  208. {
  209. return ((struct scsi_cmnd *)ncmd_ptr) - 1;
  210. }
  211. #ifndef NDEBUG
  212. #define NDEBUG (0)
  213. #endif
  214. #define dprintk(flg, fmt, ...) \
  215. do { if ((NDEBUG) & (flg)) \
  216. printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
  217. #define dsprintk(flg, host, fmt, ...) \
  218. do { if ((NDEBUG) & (flg)) \
  219. shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
  220. } while (0)
  221. #if NDEBUG
  222. #define NCR5380_dprint(flg, arg) \
  223. do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
  224. #define NCR5380_dprint_phase(flg, arg) \
  225. do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
  226. static void NCR5380_print_phase(struct Scsi_Host *instance);
  227. static void NCR5380_print(struct Scsi_Host *instance);
  228. #else
  229. #define NCR5380_dprint(flg, arg) do {} while (0)
  230. #define NCR5380_dprint_phase(flg, arg) do {} while (0)
  231. #endif
  232. static int NCR5380_init(struct Scsi_Host *instance, int flags);
  233. static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
  234. static void NCR5380_exit(struct Scsi_Host *instance);
  235. static void NCR5380_information_transfer(struct Scsi_Host *instance);
  236. static irqreturn_t NCR5380_intr(int irq, void *dev_id);
  237. static void NCR5380_main(struct work_struct *work);
  238. static const char *NCR5380_info(struct Scsi_Host *instance);
  239. static void NCR5380_reselect(struct Scsi_Host *instance);
  240. static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
  241. static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
  242. static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
  243. static int NCR5380_poll_politely2(struct NCR5380_hostdata *,
  244. unsigned int, u8, u8,
  245. unsigned int, u8, u8, unsigned long);
  246. static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata,
  247. unsigned int reg, u8 bit, u8 val,
  248. unsigned long wait)
  249. {
  250. if ((NCR5380_read(reg) & bit) == val)
  251. return 0;
  252. return NCR5380_poll_politely2(hostdata, reg, bit, val,
  253. reg, bit, val, wait);
  254. }
  255. static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *,
  256. struct scsi_cmnd *);
  257. static int NCR5380_dma_send_setup(struct NCR5380_hostdata *,
  258. unsigned char *, int);
  259. static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *,
  260. unsigned char *, int);
  261. static int NCR5380_dma_residual(struct NCR5380_hostdata *);
  262. static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata,
  263. struct scsi_cmnd *cmd)
  264. {
  265. return 0;
  266. }
  267. static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata,
  268. unsigned char *data, int count)
  269. {
  270. return 0;
  271. }
  272. static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata)
  273. {
  274. return 0;
  275. }
  276. #endif /* NCR5380_H */