3w-xxxx.h 16 KB

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  1. /*
  2. 3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
  3. Written By: Adam Radford <aradford@gmail.com>
  4. Modifications By: Joel Jacobson <linux@3ware.com>
  5. Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  6. Brad Strand <linux@3ware.com>
  7. Copyright (C) 1999-2010 3ware Inc.
  8. Kernel compatibility By: Andre Hedrick <andre@suse.com>
  9. Non-Copyright (C) 2000 Andre Hedrick <andre@suse.com>
  10. This program is free software; you can redistribute it and/or modify
  11. it under the terms of the GNU General Public License as published by
  12. the Free Software Foundation; version 2 of the License.
  13. This program is distributed in the hope that it will be useful,
  14. but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. GNU General Public License for more details.
  17. NO WARRANTY
  18. THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  19. CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  20. LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  21. MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  22. solely responsible for determining the appropriateness of using and
  23. distributing the Program and assumes all risks associated with its
  24. exercise of rights under this Agreement, including but not limited to
  25. the risks and costs of program errors, damage to or loss of data,
  26. programs or equipment, and unavailability or interruption of operations.
  27. DISCLAIMER OF LIABILITY
  28. NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  29. DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30. DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  31. ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  32. TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  33. USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  34. HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  35. You should have received a copy of the GNU General Public License
  36. along with this program; if not, write to the Free Software
  37. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  38. Bugs/Comments/Suggestions should be mailed to:
  39. aradford@gmail.com
  40. For more information, goto:
  41. http://www.lsi.com
  42. */
  43. #ifndef _3W_XXXX_H
  44. #define _3W_XXXX_H
  45. #include <linux/types.h>
  46. /* AEN strings */
  47. static char *tw_aen_string[] = {
  48. [0x000] = "INFO: AEN queue empty",
  49. [0x001] = "INFO: Soft reset occurred",
  50. [0x002] = "ERROR: Unit degraded: Unit #",
  51. [0x003] = "ERROR: Controller error",
  52. [0x004] = "ERROR: Rebuild failed: Unit #",
  53. [0x005] = "INFO: Rebuild complete: Unit #",
  54. [0x006] = "ERROR: Incomplete unit detected: Unit #",
  55. [0x007] = "INFO: Initialization complete: Unit #",
  56. [0x008] = "WARNING: Unclean shutdown detected: Unit #",
  57. [0x009] = "WARNING: ATA port timeout: Port #",
  58. [0x00A] = "ERROR: Drive error: Port #",
  59. [0x00B] = "INFO: Rebuild started: Unit #",
  60. [0x00C] = "INFO: Initialization started: Unit #",
  61. [0x00D] = "ERROR: Logical unit deleted: Unit #",
  62. [0x00F] = "WARNING: SMART threshold exceeded: Port #",
  63. [0x021] = "WARNING: ATA UDMA downgrade: Port #",
  64. [0x022] = "WARNING: ATA UDMA upgrade: Port #",
  65. [0x023] = "WARNING: Sector repair occurred: Port #",
  66. [0x024] = "ERROR: SBUF integrity check failure",
  67. [0x025] = "ERROR: Lost cached write: Port #",
  68. [0x026] = "ERROR: Drive ECC error detected: Port #",
  69. [0x027] = "ERROR: DCB checksum error: Port #",
  70. [0x028] = "ERROR: DCB unsupported version: Port #",
  71. [0x029] = "INFO: Verify started: Unit #",
  72. [0x02A] = "ERROR: Verify failed: Port #",
  73. [0x02B] = "INFO: Verify complete: Unit #",
  74. [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
  75. [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
  76. [0x02E] = "ERROR: Replacement drive is too small: Port #",
  77. [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
  78. [0x030] = "ERROR: Drive not supported: Port #"
  79. };
  80. /*
  81. Sense key lookup table
  82. Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
  83. */
  84. static unsigned char tw_sense_table[][4] =
  85. {
  86. /* Codes for newer firmware */
  87. // ATA Error SCSI Error
  88. {0x01, 0x03, 0x13, 0x00}, // Address mark not found Address mark not found for data field
  89. {0x04, 0x0b, 0x00, 0x00}, // Aborted command Aborted command
  90. {0x10, 0x0b, 0x14, 0x00}, // ID not found Recorded entity not found
  91. {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error Unrecovered read error
  92. {0x61, 0x04, 0x00, 0x00}, // Device fault Hardware error
  93. {0x84, 0x0b, 0x47, 0x00}, // Data CRC error SCSI parity error
  94. {0xd0, 0x0b, 0x00, 0x00}, // Device busy Aborted command
  95. {0xd1, 0x0b, 0x00, 0x00}, // Device busy Aborted command
  96. {0x37, 0x02, 0x04, 0x00}, // Unit offline Not ready
  97. {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error Not ready
  98. /* Codes for older firmware */
  99. // 3ware Error SCSI Error
  100. {0x51, 0x0b, 0x00, 0x00} // Unspecified Aborted command
  101. };
  102. /* Control register bit definitions */
  103. #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
  104. #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
  105. #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
  106. #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
  107. #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
  108. #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
  109. #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
  110. #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
  111. #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
  112. #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
  113. #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
  114. #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
  115. #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
  116. #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
  117. #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
  118. /* Status register bit definitions */
  119. #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
  120. #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
  121. #define TW_STATUS_PCI_PARITY_ERROR 0x00800000
  122. #define TW_STATUS_QUEUE_ERROR 0x00400000
  123. #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
  124. #define TW_STATUS_PCI_ABORT 0x00100000
  125. #define TW_STATUS_HOST_INTERRUPT 0x00080000
  126. #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
  127. #define TW_STATUS_COMMAND_INTERRUPT 0x00020000
  128. #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
  129. #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
  130. #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
  131. #define TW_STATUS_MICROCONTROLLER_READY 0x00002000
  132. #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
  133. #define TW_STATUS_ALL_INTERRUPTS 0x000F0000
  134. #define TW_STATUS_CLEARABLE_BITS 0x00D00000
  135. #define TW_STATUS_EXPECTED_BITS 0x00002000
  136. #define TW_STATUS_UNEXPECTED_BITS 0x00F00008
  137. #define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
  138. #define TW_STATUS_VALID_INTERRUPT 0x00DF0008
  139. /* RESPONSE QUEUE BIT DEFINITIONS */
  140. #define TW_RESPONSE_ID_MASK 0x00000FF0
  141. /* PCI related defines */
  142. #define TW_IO_ADDRESS_RANGE 0x10
  143. #define TW_DEVICE_NAME "3ware Storage Controller"
  144. #define TW_VENDOR_ID (0x13C1) /* 3ware */
  145. #define TW_DEVICE_ID (0x1000) /* Storage Controller */
  146. #define TW_DEVICE_ID2 (0x1001) /* 7000 series controller */
  147. #define TW_NUMDEVICES 2
  148. #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
  149. #define TW_PCI_CLEAR_PCI_ABORT 0x2000
  150. /* Command packet opcodes */
  151. #define TW_OP_NOP 0x0
  152. #define TW_OP_INIT_CONNECTION 0x1
  153. #define TW_OP_READ 0x2
  154. #define TW_OP_WRITE 0x3
  155. #define TW_OP_VERIFY 0x4
  156. #define TW_OP_GET_PARAM 0x12
  157. #define TW_OP_SET_PARAM 0x13
  158. #define TW_OP_SECTOR_INFO 0x1a
  159. #define TW_OP_AEN_LISTEN 0x1c
  160. #define TW_OP_FLUSH_CACHE 0x0e
  161. #define TW_CMD_PACKET 0x1d
  162. #define TW_CMD_PACKET_WITH_DATA 0x1f
  163. /* Asynchronous Event Notification (AEN) Codes */
  164. #define TW_AEN_QUEUE_EMPTY 0x0000
  165. #define TW_AEN_SOFT_RESET 0x0001
  166. #define TW_AEN_DEGRADED_MIRROR 0x0002
  167. #define TW_AEN_CONTROLLER_ERROR 0x0003
  168. #define TW_AEN_REBUILD_FAIL 0x0004
  169. #define TW_AEN_REBUILD_DONE 0x0005
  170. #define TW_AEN_QUEUE_FULL 0x00ff
  171. #define TW_AEN_TABLE_UNDEFINED 0x15
  172. #define TW_AEN_APORT_TIMEOUT 0x0009
  173. #define TW_AEN_DRIVE_ERROR 0x000A
  174. #define TW_AEN_SMART_FAIL 0x000F
  175. #define TW_AEN_SBUF_FAIL 0x0024
  176. /* Misc defines */
  177. #define TW_ALIGNMENT_6000 64 /* 64 bytes */
  178. #define TW_ALIGNMENT_7000 4 /* 4 bytes */
  179. #define TW_MAX_UNITS 16
  180. #define TW_COMMAND_ALIGNMENT_MASK 0x1ff
  181. #define TW_INIT_MESSAGE_CREDITS 0x100
  182. #define TW_INIT_COMMAND_PACKET_SIZE 0x3
  183. #define TW_POLL_MAX_RETRIES 20000
  184. #define TW_MAX_SGL_LENGTH 62
  185. #define TW_ATA_PASS_SGL_MAX 60
  186. #define TW_Q_LENGTH 256
  187. #define TW_Q_START 0
  188. #define TW_MAX_SLOT 32
  189. #define TW_MAX_PCI_BUSES 255
  190. #define TW_MAX_RESET_TRIES 3
  191. #define TW_UNIT_INFORMATION_TABLE_BASE 0x300
  192. #define TW_MAX_CMDS_PER_LUN 254 /* 254 for io, 1 for
  193. chrdev ioctl, one for
  194. internal aen post */
  195. #define TW_BLOCK_SIZE 0x200 /* 512-byte blocks */
  196. #define TW_IOCTL 0x80
  197. #define TW_UNIT_ONLINE 1
  198. #define TW_IN_INTR 1
  199. #define TW_IN_RESET 2
  200. #define TW_IN_CHRDEV_IOCTL 3
  201. #define TW_MAX_SECTORS 256
  202. #define TW_MAX_IOCTL_SECTORS 512
  203. #define TW_AEN_WAIT_TIME 1000
  204. #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */
  205. #define TW_ISR_DONT_COMPLETE 2
  206. #define TW_ISR_DONT_RESULT 3
  207. #define TW_IOCTL_TIMEOUT 25 /* 25 seconds */
  208. #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
  209. #define TW_IOCTL_CHRDEV_FREE -1
  210. #define TW_MAX_CDB_LEN 16
  211. /* Bitmask macros to eliminate bitfields */
  212. /* opcode: 5, sgloffset: 3 */
  213. #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
  214. #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
  215. /* reserved_1: 4, response_id: 8, reserved_2: 20 */
  216. #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
  217. /* unit: 4, host_id: 4 */
  218. #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
  219. #define TW_UNIT_OUT(x) (x & 0xf)
  220. /* Macros */
  221. #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
  222. #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
  223. #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
  224. #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
  225. #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
  226. #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
  227. #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
  228. #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
  229. #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
  230. #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
  231. #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
  232. #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
  233. TW_CONTROL_CLEAR_HOST_INTERRUPT | \
  234. TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
  235. TW_CONTROL_MASK_COMMAND_INTERRUPT | \
  236. TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
  237. TW_CONTROL_CLEAR_ERROR_STATUS | \
  238. TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
  239. #define TW_STATUS_ERRORS(x) \
  240. (((x & TW_STATUS_PCI_ABORT) || \
  241. (x & TW_STATUS_PCI_PARITY_ERROR) || \
  242. (x & TW_STATUS_QUEUE_ERROR) || \
  243. (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
  244. (x & TW_STATUS_MICROCONTROLLER_READY))
  245. #ifdef TW_DEBUG
  246. #define dprintk(msg...) printk(msg)
  247. #else
  248. #define dprintk(msg...) do { } while(0)
  249. #endif
  250. #pragma pack(1)
  251. /* Scatter Gather List Entry */
  252. typedef struct TAG_TW_SG_Entry {
  253. u32 address;
  254. u32 length;
  255. } TW_SG_Entry;
  256. typedef unsigned char TW_Sector[512];
  257. /* Command Packet */
  258. typedef struct TW_Command {
  259. unsigned char opcode__sgloffset;
  260. unsigned char size;
  261. unsigned char request_id;
  262. unsigned char unit__hostid;
  263. /* Second DWORD */
  264. unsigned char status;
  265. unsigned char flags;
  266. union {
  267. unsigned short block_count;
  268. unsigned short parameter_count;
  269. unsigned short message_credits;
  270. } byte6;
  271. union {
  272. struct {
  273. u32 lba;
  274. TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
  275. u32 padding; /* pad to 512 bytes */
  276. } io;
  277. struct {
  278. TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
  279. u32 padding[2];
  280. } param;
  281. struct {
  282. u32 response_queue_pointer;
  283. u32 padding[125];
  284. } init_connection;
  285. struct {
  286. char version[504];
  287. } ioctl_miniport_version;
  288. } byte8;
  289. } TW_Command;
  290. #pragma pack()
  291. typedef struct TAG_TW_Ioctl {
  292. unsigned char opcode;
  293. unsigned short table_id;
  294. unsigned char parameter_id;
  295. unsigned char parameter_size_bytes;
  296. unsigned char unit_index;
  297. unsigned char data[1];
  298. } TW_Ioctl;
  299. #pragma pack(1)
  300. /* Structure for new chardev ioctls */
  301. typedef struct TAG_TW_New_Ioctl {
  302. unsigned int data_buffer_length;
  303. unsigned char padding [508];
  304. TW_Command firmware_command;
  305. char data_buffer[1];
  306. } TW_New_Ioctl;
  307. /* GetParam descriptor */
  308. typedef struct {
  309. unsigned short table_id;
  310. unsigned char parameter_id;
  311. unsigned char parameter_size_bytes;
  312. unsigned char data[1];
  313. } TW_Param, *PTW_Param;
  314. /* Response queue */
  315. typedef union TAG_TW_Response_Queue {
  316. u32 response_id;
  317. u32 value;
  318. } TW_Response_Queue;
  319. typedef int TW_Cmd_State;
  320. #define TW_S_INITIAL 0x1 /* Initial state */
  321. #define TW_S_STARTED 0x2 /* Id in use */
  322. #define TW_S_POSTED 0x4 /* Posted to the controller */
  323. #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
  324. #define TW_S_COMPLETED 0x10 /* Completed by isr */
  325. #define TW_S_FINISHED 0x20 /* I/O completely done */
  326. #define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
  327. /* Command header for ATA pass-thru */
  328. typedef struct TAG_TW_Passthru
  329. {
  330. unsigned char opcode__sgloffset;
  331. unsigned char size;
  332. unsigned char request_id;
  333. unsigned char aport__hostid;
  334. unsigned char status;
  335. unsigned char flags;
  336. unsigned short param;
  337. unsigned short features;
  338. unsigned short sector_count;
  339. unsigned short sector_num;
  340. unsigned short cylinder_lo;
  341. unsigned short cylinder_hi;
  342. unsigned char drive_head;
  343. unsigned char command;
  344. TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
  345. unsigned char padding[12];
  346. } TW_Passthru;
  347. #pragma pack()
  348. typedef struct TAG_TW_Device_Extension {
  349. u32 base_addr;
  350. unsigned long *alignment_virtual_address[TW_Q_LENGTH];
  351. unsigned long alignment_physical_address[TW_Q_LENGTH];
  352. int is_unit_present[TW_MAX_UNITS];
  353. unsigned long *command_packet_virtual_address[TW_Q_LENGTH];
  354. unsigned long command_packet_physical_address[TW_Q_LENGTH];
  355. struct pci_dev *tw_pci_dev;
  356. struct scsi_cmnd *srb[TW_Q_LENGTH];
  357. unsigned char free_queue[TW_Q_LENGTH];
  358. unsigned char free_head;
  359. unsigned char free_tail;
  360. unsigned char pending_queue[TW_Q_LENGTH];
  361. unsigned char pending_head;
  362. unsigned char pending_tail;
  363. TW_Cmd_State state[TW_Q_LENGTH];
  364. u32 posted_request_count;
  365. u32 max_posted_request_count;
  366. u32 request_count_marked_pending;
  367. u32 pending_request_count;
  368. u32 max_pending_request_count;
  369. u32 max_sgl_entries;
  370. u32 sgl_entries;
  371. u32 num_resets;
  372. u32 sector_count;
  373. u32 max_sector_count;
  374. u32 aen_count;
  375. struct Scsi_Host *host;
  376. struct mutex ioctl_lock;
  377. unsigned short aen_queue[TW_Q_LENGTH];
  378. unsigned char aen_head;
  379. unsigned char aen_tail;
  380. volatile long flags; /* long req'd for set_bit --RR */
  381. int reset_print;
  382. volatile int chrdev_request_id;
  383. wait_queue_head_t ioctl_wqueue;
  384. } TW_Device_Extension;
  385. #endif /* _3W_XXXX_H */