rtc-xgene.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * APM X-Gene SoC Real Time Clock Driver
  4. *
  5. * Copyright (c) 2014, Applied Micro Circuits Corporation
  6. * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
  7. * Loc Ho <lho@apm.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/rtc.h>
  17. #include <linux/slab.h>
  18. /* RTC CSR Registers */
  19. #define RTC_CCVR 0x00
  20. #define RTC_CMR 0x04
  21. #define RTC_CLR 0x08
  22. #define RTC_CCR 0x0C
  23. #define RTC_CCR_IE BIT(0)
  24. #define RTC_CCR_MASK BIT(1)
  25. #define RTC_CCR_EN BIT(2)
  26. #define RTC_CCR_WEN BIT(3)
  27. #define RTC_STAT 0x10
  28. #define RTC_STAT_BIT BIT(0)
  29. #define RTC_RSTAT 0x14
  30. #define RTC_EOI 0x18
  31. #define RTC_VER 0x1C
  32. #define RTC_CPSR 0x20
  33. #define COUNTER_PRESCALER_VALUE 0x8000
  34. #define RTC_PSCLR_EN BIT(4)
  35. struct xgene_rtc_dev {
  36. struct rtc_device *rtc;
  37. void __iomem *csr_base;
  38. struct clk *clk;
  39. unsigned int irq_wake;
  40. unsigned int irq_enabled;
  41. };
  42. static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)
  43. {
  44. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  45. rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
  46. return 0;
  47. }
  48. static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm)
  49. {
  50. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  51. /*
  52. * NOTE: After the following write, the RTC_CCVR is only reflected
  53. * after the update cycle of 1 seconds.
  54. */
  55. writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
  56. readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
  57. return 0;
  58. }
  59. static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  60. {
  61. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  62. /* If possible, CMR should be read here */
  63. rtc_time64_to_tm(0, &alrm->time);
  64. alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
  65. return 0;
  66. }
  67. static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
  68. {
  69. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  70. u32 ccr;
  71. ccr = readl(pdata->csr_base + RTC_CCR);
  72. if (enabled) {
  73. ccr &= ~RTC_CCR_MASK;
  74. ccr |= RTC_CCR_IE;
  75. } else {
  76. ccr &= ~RTC_CCR_IE;
  77. ccr |= RTC_CCR_MASK;
  78. }
  79. writel(ccr, pdata->csr_base + RTC_CCR);
  80. return 0;
  81. }
  82. static int xgene_rtc_alarm_irq_enabled(struct device *dev)
  83. {
  84. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  85. return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
  86. }
  87. static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  88. {
  89. struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
  90. writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
  91. xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
  92. return 0;
  93. }
  94. static const struct rtc_class_ops xgene_rtc_ops = {
  95. .read_time = xgene_rtc_read_time,
  96. .set_time = xgene_rtc_set_time,
  97. .read_alarm = xgene_rtc_read_alarm,
  98. .set_alarm = xgene_rtc_set_alarm,
  99. .alarm_irq_enable = xgene_rtc_alarm_irq_enable,
  100. };
  101. static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
  102. {
  103. struct xgene_rtc_dev *pdata = id;
  104. /* Check if interrupt asserted */
  105. if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
  106. return IRQ_NONE;
  107. /* Clear interrupt */
  108. readl(pdata->csr_base + RTC_EOI);
  109. rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
  110. return IRQ_HANDLED;
  111. }
  112. static int xgene_rtc_probe(struct platform_device *pdev)
  113. {
  114. struct xgene_rtc_dev *pdata;
  115. int ret;
  116. int irq;
  117. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  118. if (!pdata)
  119. return -ENOMEM;
  120. platform_set_drvdata(pdev, pdata);
  121. pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
  122. if (IS_ERR(pdata->csr_base))
  123. return PTR_ERR(pdata->csr_base);
  124. pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
  125. if (IS_ERR(pdata->rtc))
  126. return PTR_ERR(pdata->rtc);
  127. irq = platform_get_irq(pdev, 0);
  128. if (irq < 0)
  129. return irq;
  130. ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
  131. dev_name(&pdev->dev), pdata);
  132. if (ret) {
  133. dev_err(&pdev->dev, "Could not request IRQ\n");
  134. return ret;
  135. }
  136. pdata->clk = devm_clk_get(&pdev->dev, NULL);
  137. if (IS_ERR(pdata->clk)) {
  138. dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
  139. return -ENODEV;
  140. }
  141. ret = clk_prepare_enable(pdata->clk);
  142. if (ret)
  143. return ret;
  144. /* Turn on the clock and the crystal */
  145. writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
  146. /* the input clock in light platform is 32K but not 1HZ, so we need to prescale the clock, 32K / COUNTER_PRESCALER_VALUE = 1HZ */
  147. writel(COUNTER_PRESCALER_VALUE, pdata->csr_base + RTC_CPSR);
  148. /* Allows user to control the usage of RTC Prescaler feature */
  149. writel(readl(pdata->csr_base + RTC_CCR) | RTC_PSCLR_EN, pdata->csr_base + RTC_CCR);
  150. ret = device_init_wakeup(&pdev->dev, 1);
  151. if (ret) {
  152. clk_disable_unprepare(pdata->clk);
  153. return ret;
  154. }
  155. /* HW does not support update faster than 1 seconds */
  156. pdata->rtc->uie_unsupported = 1;
  157. pdata->rtc->ops = &xgene_rtc_ops;
  158. pdata->rtc->range_max = U32_MAX;
  159. ret = rtc_register_device(pdata->rtc);
  160. if (ret) {
  161. clk_disable_unprepare(pdata->clk);
  162. return ret;
  163. }
  164. return 0;
  165. }
  166. static int xgene_rtc_remove(struct platform_device *pdev)
  167. {
  168. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  169. xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
  170. device_init_wakeup(&pdev->dev, 0);
  171. clk_disable_unprepare(pdata->clk);
  172. return 0;
  173. }
  174. static int __maybe_unused xgene_rtc_suspend(struct device *dev)
  175. {
  176. struct platform_device *pdev = to_platform_device(dev);
  177. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  178. int irq;
  179. irq = platform_get_irq(pdev, 0);
  180. /*
  181. * If this RTC alarm will be used for waking the system up,
  182. * don't disable it of course. Else we just disable the alarm
  183. * and await suspension.
  184. */
  185. if (device_may_wakeup(&pdev->dev)) {
  186. if (!enable_irq_wake(irq))
  187. pdata->irq_wake = 1;
  188. } else {
  189. pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
  190. xgene_rtc_alarm_irq_enable(dev, 0);
  191. clk_disable_unprepare(pdata->clk);
  192. }
  193. return 0;
  194. }
  195. static int __maybe_unused xgene_rtc_resume(struct device *dev)
  196. {
  197. struct platform_device *pdev = to_platform_device(dev);
  198. struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
  199. int irq;
  200. int rc;
  201. irq = platform_get_irq(pdev, 0);
  202. if (device_may_wakeup(&pdev->dev)) {
  203. if (pdata->irq_wake) {
  204. disable_irq_wake(irq);
  205. pdata->irq_wake = 0;
  206. }
  207. } else {
  208. rc = clk_prepare_enable(pdata->clk);
  209. if (rc) {
  210. dev_err(dev, "Unable to enable clock error %d\n", rc);
  211. return rc;
  212. }
  213. xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
  214. }
  215. return 0;
  216. }
  217. static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);
  218. #ifdef CONFIG_OF
  219. static const struct of_device_id xgene_rtc_of_match[] = {
  220. {.compatible = "apm,xgene-rtc" },
  221. { }
  222. };
  223. MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
  224. #endif
  225. static struct platform_driver xgene_rtc_driver = {
  226. .probe = xgene_rtc_probe,
  227. .remove = xgene_rtc_remove,
  228. .driver = {
  229. .name = "xgene-rtc",
  230. .pm = &xgene_rtc_pm_ops,
  231. .of_match_table = of_match_ptr(xgene_rtc_of_match),
  232. },
  233. };
  234. module_platform_driver(xgene_rtc_driver);
  235. MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
  236. MODULE_AUTHOR("Rameshwar Sahu <rsahu@apm.com>");
  237. MODULE_LICENSE("GPL");