rtc-x1205.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * An i2c driver for the Xicor/Intersil X1205 RTC
  4. * Copyright 2004 Karen Spearel
  5. * Copyright 2005 Alessandro Zummo
  6. *
  7. * please send all reports to:
  8. * Karen Spearel <kas111 at gmail dot com>
  9. * Alessandro Zummo <a.zummo@towertech.it>
  10. *
  11. * based on a lot of other RTC drivers.
  12. *
  13. * Information and datasheet:
  14. * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
  15. */
  16. #include <linux/i2c.h>
  17. #include <linux/bcd.h>
  18. #include <linux/rtc.h>
  19. #include <linux/delay.h>
  20. #include <linux/module.h>
  21. #include <linux/bitops.h>
  22. /* offsets into CCR area */
  23. #define CCR_SEC 0
  24. #define CCR_MIN 1
  25. #define CCR_HOUR 2
  26. #define CCR_MDAY 3
  27. #define CCR_MONTH 4
  28. #define CCR_YEAR 5
  29. #define CCR_WDAY 6
  30. #define CCR_Y2K 7
  31. #define X1205_REG_SR 0x3F /* status register */
  32. #define X1205_REG_Y2K 0x37
  33. #define X1205_REG_DW 0x36
  34. #define X1205_REG_YR 0x35
  35. #define X1205_REG_MO 0x34
  36. #define X1205_REG_DT 0x33
  37. #define X1205_REG_HR 0x32
  38. #define X1205_REG_MN 0x31
  39. #define X1205_REG_SC 0x30
  40. #define X1205_REG_DTR 0x13
  41. #define X1205_REG_ATR 0x12
  42. #define X1205_REG_INT 0x11
  43. #define X1205_REG_0 0x10
  44. #define X1205_REG_Y2K1 0x0F
  45. #define X1205_REG_DWA1 0x0E
  46. #define X1205_REG_YRA1 0x0D
  47. #define X1205_REG_MOA1 0x0C
  48. #define X1205_REG_DTA1 0x0B
  49. #define X1205_REG_HRA1 0x0A
  50. #define X1205_REG_MNA1 0x09
  51. #define X1205_REG_SCA1 0x08
  52. #define X1205_REG_Y2K0 0x07
  53. #define X1205_REG_DWA0 0x06
  54. #define X1205_REG_YRA0 0x05
  55. #define X1205_REG_MOA0 0x04
  56. #define X1205_REG_DTA0 0x03
  57. #define X1205_REG_HRA0 0x02
  58. #define X1205_REG_MNA0 0x01
  59. #define X1205_REG_SCA0 0x00
  60. #define X1205_CCR_BASE 0x30 /* Base address of CCR */
  61. #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
  62. #define X1205_SR_RTCF 0x01 /* Clock failure */
  63. #define X1205_SR_WEL 0x02 /* Write Enable Latch */
  64. #define X1205_SR_RWEL 0x04 /* Register Write Enable */
  65. #define X1205_SR_AL0 0x20 /* Alarm 0 match */
  66. #define X1205_DTR_DTR0 0x01
  67. #define X1205_DTR_DTR1 0x02
  68. #define X1205_DTR_DTR2 0x04
  69. #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
  70. #define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
  71. static struct i2c_driver x1205_driver;
  72. /*
  73. * In the routines that deal directly with the x1205 hardware, we use
  74. * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
  75. * Epoch is initialized as 2000. Time is set to UTC.
  76. */
  77. static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
  78. unsigned char reg_base)
  79. {
  80. unsigned char dt_addr[2] = { 0, reg_base };
  81. unsigned char buf[8];
  82. int i;
  83. struct i2c_msg msgs[] = {
  84. {/* setup read ptr */
  85. .addr = client->addr,
  86. .len = 2,
  87. .buf = dt_addr
  88. },
  89. {/* read date */
  90. .addr = client->addr,
  91. .flags = I2C_M_RD,
  92. .len = 8,
  93. .buf = buf
  94. },
  95. };
  96. /* read date registers */
  97. if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
  98. dev_err(&client->dev, "%s: read error\n", __func__);
  99. return -EIO;
  100. }
  101. dev_dbg(&client->dev,
  102. "%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
  103. "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
  104. __func__,
  105. buf[0], buf[1], buf[2], buf[3],
  106. buf[4], buf[5], buf[6], buf[7]);
  107. /* Mask out the enable bits if these are alarm registers */
  108. if (reg_base < X1205_CCR_BASE)
  109. for (i = 0; i <= 4; i++)
  110. buf[i] &= 0x7F;
  111. tm->tm_sec = bcd2bin(buf[CCR_SEC]);
  112. tm->tm_min = bcd2bin(buf[CCR_MIN]);
  113. tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
  114. tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
  115. tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
  116. tm->tm_year = bcd2bin(buf[CCR_YEAR])
  117. + (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
  118. tm->tm_wday = buf[CCR_WDAY];
  119. dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  120. "mday=%d, mon=%d, year=%d, wday=%d\n",
  121. __func__,
  122. tm->tm_sec, tm->tm_min, tm->tm_hour,
  123. tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
  124. return 0;
  125. }
  126. static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
  127. {
  128. static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
  129. struct i2c_msg msgs[] = {
  130. { /* setup read ptr */
  131. .addr = client->addr,
  132. .len = 2,
  133. .buf = sr_addr
  134. },
  135. { /* read status */
  136. .addr = client->addr,
  137. .flags = I2C_M_RD,
  138. .len = 1,
  139. .buf = sr
  140. },
  141. };
  142. /* read status register */
  143. if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
  144. dev_err(&client->dev, "%s: read error\n", __func__);
  145. return -EIO;
  146. }
  147. return 0;
  148. }
  149. static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
  150. u8 reg_base, unsigned char alm_enable)
  151. {
  152. int i, xfer;
  153. unsigned char rdata[10] = { 0, reg_base };
  154. unsigned char *buf = rdata + 2;
  155. static const unsigned char wel[3] = { 0, X1205_REG_SR,
  156. X1205_SR_WEL };
  157. static const unsigned char rwel[3] = { 0, X1205_REG_SR,
  158. X1205_SR_WEL | X1205_SR_RWEL };
  159. static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
  160. dev_dbg(&client->dev,
  161. "%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
  162. __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
  163. tm->tm_mon, tm->tm_year, tm->tm_wday);
  164. buf[CCR_SEC] = bin2bcd(tm->tm_sec);
  165. buf[CCR_MIN] = bin2bcd(tm->tm_min);
  166. /* set hour and 24hr bit */
  167. buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
  168. buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
  169. /* month, 1 - 12 */
  170. buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
  171. /* year, since the rtc epoch*/
  172. buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
  173. buf[CCR_WDAY] = tm->tm_wday & 0x07;
  174. buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
  175. /* If writing alarm registers, set compare bits on registers 0-4 */
  176. if (reg_base < X1205_CCR_BASE)
  177. for (i = 0; i <= 4; i++)
  178. buf[i] |= 0x80;
  179. /* this sequence is required to unlock the chip */
  180. xfer = i2c_master_send(client, wel, 3);
  181. if (xfer != 3) {
  182. dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
  183. return -EIO;
  184. }
  185. xfer = i2c_master_send(client, rwel, 3);
  186. if (xfer != 3) {
  187. dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
  188. return -EIO;
  189. }
  190. xfer = i2c_master_send(client, rdata, sizeof(rdata));
  191. if (xfer != sizeof(rdata)) {
  192. dev_err(&client->dev,
  193. "%s: result=%d addr=%02x, data=%02x\n",
  194. __func__,
  195. xfer, rdata[1], rdata[2]);
  196. return -EIO;
  197. }
  198. /* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
  199. if (reg_base < X1205_CCR_BASE) {
  200. unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
  201. msleep(10);
  202. /* ...and set or clear the AL0E bit in the INT register */
  203. /* Need to set RWEL again as the write has cleared it */
  204. xfer = i2c_master_send(client, rwel, 3);
  205. if (xfer != 3) {
  206. dev_err(&client->dev,
  207. "%s: aloe rwel - %d\n",
  208. __func__,
  209. xfer);
  210. return -EIO;
  211. }
  212. if (alm_enable)
  213. al0e[2] = X1205_INT_AL0E;
  214. xfer = i2c_master_send(client, al0e, 3);
  215. if (xfer != 3) {
  216. dev_err(&client->dev,
  217. "%s: al0e - %d\n",
  218. __func__,
  219. xfer);
  220. return -EIO;
  221. }
  222. /* and wait 10msec again for this write to complete */
  223. msleep(10);
  224. }
  225. /* disable further writes */
  226. xfer = i2c_master_send(client, diswe, 3);
  227. if (xfer != 3) {
  228. dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
  229. return -EIO;
  230. }
  231. return 0;
  232. }
  233. static int x1205_fix_osc(struct i2c_client *client)
  234. {
  235. int err;
  236. struct rtc_time tm;
  237. memset(&tm, 0, sizeof(tm));
  238. err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
  239. if (err < 0)
  240. dev_err(&client->dev, "unable to restart the oscillator\n");
  241. return err;
  242. }
  243. static int x1205_get_dtrim(struct i2c_client *client, int *trim)
  244. {
  245. unsigned char dtr;
  246. static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
  247. struct i2c_msg msgs[] = {
  248. { /* setup read ptr */
  249. .addr = client->addr,
  250. .len = 2,
  251. .buf = dtr_addr
  252. },
  253. { /* read dtr */
  254. .addr = client->addr,
  255. .flags = I2C_M_RD,
  256. .len = 1,
  257. .buf = &dtr
  258. },
  259. };
  260. /* read dtr register */
  261. if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
  262. dev_err(&client->dev, "%s: read error\n", __func__);
  263. return -EIO;
  264. }
  265. dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
  266. *trim = 0;
  267. if (dtr & X1205_DTR_DTR0)
  268. *trim += 20;
  269. if (dtr & X1205_DTR_DTR1)
  270. *trim += 10;
  271. if (dtr & X1205_DTR_DTR2)
  272. *trim = -*trim;
  273. return 0;
  274. }
  275. static int x1205_get_atrim(struct i2c_client *client, int *trim)
  276. {
  277. s8 atr;
  278. static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
  279. struct i2c_msg msgs[] = {
  280. {/* setup read ptr */
  281. .addr = client->addr,
  282. .len = 2,
  283. .buf = atr_addr
  284. },
  285. {/* read atr */
  286. .addr = client->addr,
  287. .flags = I2C_M_RD,
  288. .len = 1,
  289. .buf = &atr
  290. },
  291. };
  292. /* read atr register */
  293. if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
  294. dev_err(&client->dev, "%s: read error\n", __func__);
  295. return -EIO;
  296. }
  297. dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
  298. /* atr is a two's complement value on 6 bits,
  299. * perform sign extension. The formula is
  300. * Catr = (atr * 0.25pF) + 11.00pF.
  301. */
  302. atr = sign_extend32(atr, 5);
  303. dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
  304. *trim = (atr * 250) + 11000;
  305. dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
  306. return 0;
  307. }
  308. struct x1205_limit {
  309. unsigned char reg, mask, min, max;
  310. };
  311. static int x1205_validate_client(struct i2c_client *client)
  312. {
  313. int i, xfer;
  314. /* Probe array. We will read the register at the specified
  315. * address and check if the given bits are zero.
  316. */
  317. static const unsigned char probe_zero_pattern[] = {
  318. /* register, mask */
  319. X1205_REG_SR, 0x18,
  320. X1205_REG_DTR, 0xF8,
  321. X1205_REG_ATR, 0xC0,
  322. X1205_REG_INT, 0x18,
  323. X1205_REG_0, 0xFF,
  324. };
  325. static const struct x1205_limit probe_limits_pattern[] = {
  326. /* register, mask, min, max */
  327. { X1205_REG_Y2K, 0xFF, 19, 20 },
  328. { X1205_REG_DW, 0xFF, 0, 6 },
  329. { X1205_REG_YR, 0xFF, 0, 99 },
  330. { X1205_REG_MO, 0xFF, 0, 12 },
  331. { X1205_REG_DT, 0xFF, 0, 31 },
  332. { X1205_REG_HR, 0x7F, 0, 23 },
  333. { X1205_REG_MN, 0xFF, 0, 59 },
  334. { X1205_REG_SC, 0xFF, 0, 59 },
  335. { X1205_REG_Y2K1, 0xFF, 19, 20 },
  336. { X1205_REG_Y2K0, 0xFF, 19, 20 },
  337. };
  338. /* check that registers have bits a 0 where expected */
  339. for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
  340. unsigned char buf;
  341. unsigned char addr[2] = { 0, probe_zero_pattern[i] };
  342. struct i2c_msg msgs[2] = {
  343. {
  344. .addr = client->addr,
  345. .len = 2,
  346. .buf = addr
  347. },
  348. {
  349. .addr = client->addr,
  350. .flags = I2C_M_RD,
  351. .len = 1,
  352. .buf = &buf
  353. },
  354. };
  355. xfer = i2c_transfer(client->adapter, msgs, 2);
  356. if (xfer != 2) {
  357. dev_err(&client->dev,
  358. "%s: could not read register %x\n",
  359. __func__, probe_zero_pattern[i]);
  360. return -EIO;
  361. }
  362. if ((buf & probe_zero_pattern[i+1]) != 0) {
  363. dev_err(&client->dev,
  364. "%s: register=%02x, zero pattern=%d, value=%x\n",
  365. __func__, probe_zero_pattern[i], i, buf);
  366. return -ENODEV;
  367. }
  368. }
  369. /* check limits (only registers with bcd values) */
  370. for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
  371. unsigned char reg, value;
  372. unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
  373. struct i2c_msg msgs[2] = {
  374. {
  375. .addr = client->addr,
  376. .len = 2,
  377. .buf = addr
  378. },
  379. {
  380. .addr = client->addr,
  381. .flags = I2C_M_RD,
  382. .len = 1,
  383. .buf = &reg
  384. },
  385. };
  386. xfer = i2c_transfer(client->adapter, msgs, 2);
  387. if (xfer != 2) {
  388. dev_err(&client->dev,
  389. "%s: could not read register %x\n",
  390. __func__, probe_limits_pattern[i].reg);
  391. return -EIO;
  392. }
  393. value = bcd2bin(reg & probe_limits_pattern[i].mask);
  394. if (value > probe_limits_pattern[i].max ||
  395. value < probe_limits_pattern[i].min) {
  396. dev_dbg(&client->dev,
  397. "%s: register=%x, lim pattern=%d, value=%d\n",
  398. __func__, probe_limits_pattern[i].reg,
  399. i, value);
  400. return -ENODEV;
  401. }
  402. }
  403. return 0;
  404. }
  405. static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  406. {
  407. int err;
  408. unsigned char intreg, status;
  409. static unsigned char int_addr[2] = { 0, X1205_REG_INT };
  410. struct i2c_client *client = to_i2c_client(dev);
  411. struct i2c_msg msgs[] = {
  412. { /* setup read ptr */
  413. .addr = client->addr,
  414. .len = 2,
  415. .buf = int_addr
  416. },
  417. {/* read INT register */
  418. .addr = client->addr,
  419. .flags = I2C_M_RD,
  420. .len = 1,
  421. .buf = &intreg
  422. },
  423. };
  424. /* read interrupt register and status register */
  425. if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
  426. dev_err(&client->dev, "%s: read error\n", __func__);
  427. return -EIO;
  428. }
  429. err = x1205_get_status(client, &status);
  430. if (err == 0) {
  431. alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
  432. alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
  433. err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
  434. }
  435. return err;
  436. }
  437. static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  438. {
  439. return x1205_set_datetime(to_i2c_client(dev),
  440. &alrm->time, X1205_ALM0_BASE, alrm->enabled);
  441. }
  442. static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
  443. {
  444. return x1205_get_datetime(to_i2c_client(dev),
  445. tm, X1205_CCR_BASE);
  446. }
  447. static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
  448. {
  449. return x1205_set_datetime(to_i2c_client(dev),
  450. tm, X1205_CCR_BASE, 0);
  451. }
  452. static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
  453. {
  454. int err, dtrim, atrim;
  455. err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
  456. if (!err)
  457. seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
  458. err = x1205_get_atrim(to_i2c_client(dev), &atrim);
  459. if (!err)
  460. seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
  461. atrim / 1000, atrim % 1000);
  462. return 0;
  463. }
  464. static const struct rtc_class_ops x1205_rtc_ops = {
  465. .proc = x1205_rtc_proc,
  466. .read_time = x1205_rtc_read_time,
  467. .set_time = x1205_rtc_set_time,
  468. .read_alarm = x1205_rtc_read_alarm,
  469. .set_alarm = x1205_rtc_set_alarm,
  470. };
  471. static ssize_t x1205_sysfs_show_atrim(struct device *dev,
  472. struct device_attribute *attr, char *buf)
  473. {
  474. int err, atrim;
  475. err = x1205_get_atrim(to_i2c_client(dev), &atrim);
  476. if (err)
  477. return err;
  478. return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
  479. }
  480. static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
  481. static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
  482. struct device_attribute *attr, char *buf)
  483. {
  484. int err, dtrim;
  485. err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
  486. if (err)
  487. return err;
  488. return sprintf(buf, "%d ppm\n", dtrim);
  489. }
  490. static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
  491. static int x1205_sysfs_register(struct device *dev)
  492. {
  493. int err;
  494. err = device_create_file(dev, &dev_attr_atrim);
  495. if (err)
  496. return err;
  497. err = device_create_file(dev, &dev_attr_dtrim);
  498. if (err)
  499. device_remove_file(dev, &dev_attr_atrim);
  500. return err;
  501. }
  502. static void x1205_sysfs_unregister(struct device *dev)
  503. {
  504. device_remove_file(dev, &dev_attr_atrim);
  505. device_remove_file(dev, &dev_attr_dtrim);
  506. }
  507. static int x1205_probe(struct i2c_client *client,
  508. const struct i2c_device_id *id)
  509. {
  510. int err = 0;
  511. unsigned char sr;
  512. struct rtc_device *rtc;
  513. dev_dbg(&client->dev, "%s\n", __func__);
  514. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
  515. return -ENODEV;
  516. if (x1205_validate_client(client) < 0)
  517. return -ENODEV;
  518. rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
  519. &x1205_rtc_ops, THIS_MODULE);
  520. if (IS_ERR(rtc))
  521. return PTR_ERR(rtc);
  522. i2c_set_clientdata(client, rtc);
  523. /* Check for power failures and eventually enable the osc */
  524. err = x1205_get_status(client, &sr);
  525. if (!err) {
  526. if (sr & X1205_SR_RTCF) {
  527. dev_err(&client->dev,
  528. "power failure detected, "
  529. "please set the clock\n");
  530. udelay(50);
  531. x1205_fix_osc(client);
  532. }
  533. } else {
  534. dev_err(&client->dev, "couldn't read status\n");
  535. }
  536. err = x1205_sysfs_register(&client->dev);
  537. if (err)
  538. dev_err(&client->dev, "Unable to create sysfs entries\n");
  539. return 0;
  540. }
  541. static int x1205_remove(struct i2c_client *client)
  542. {
  543. x1205_sysfs_unregister(&client->dev);
  544. return 0;
  545. }
  546. static const struct i2c_device_id x1205_id[] = {
  547. { "x1205", 0 },
  548. { }
  549. };
  550. MODULE_DEVICE_TABLE(i2c, x1205_id);
  551. static const struct of_device_id x1205_dt_ids[] = {
  552. { .compatible = "xircom,x1205", },
  553. {},
  554. };
  555. MODULE_DEVICE_TABLE(of, x1205_dt_ids);
  556. static struct i2c_driver x1205_driver = {
  557. .driver = {
  558. .name = "rtc-x1205",
  559. .of_match_table = x1205_dt_ids,
  560. },
  561. .probe = x1205_probe,
  562. .remove = x1205_remove,
  563. .id_table = x1205_id,
  564. };
  565. module_i2c_driver(x1205_driver);
  566. MODULE_AUTHOR(
  567. "Karen Spearel <kas111 at gmail dot com>, "
  568. "Alessandro Zummo <a.zummo@towertech.it>");
  569. MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
  570. MODULE_LICENSE("GPL");