rtc-vr41xx.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for NEC VR4100 series Real Time Clock unit.
  4. *
  5. * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
  6. */
  7. #include <linux/compat.h>
  8. #include <linux/err.h>
  9. #include <linux/fs.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/ioport.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/rtc.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/types.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/log2.h>
  21. #include <asm/div64.h>
  22. MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
  23. MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
  24. MODULE_LICENSE("GPL v2");
  25. /* RTC 1 registers */
  26. #define ETIMELREG 0x00
  27. #define ETIMEMREG 0x02
  28. #define ETIMEHREG 0x04
  29. /* RFU */
  30. #define ECMPLREG 0x08
  31. #define ECMPMREG 0x0a
  32. #define ECMPHREG 0x0c
  33. /* RFU */
  34. #define RTCL1LREG 0x10
  35. #define RTCL1HREG 0x12
  36. #define RTCL1CNTLREG 0x14
  37. #define RTCL1CNTHREG 0x16
  38. #define RTCL2LREG 0x18
  39. #define RTCL2HREG 0x1a
  40. #define RTCL2CNTLREG 0x1c
  41. #define RTCL2CNTHREG 0x1e
  42. /* RTC 2 registers */
  43. #define TCLKLREG 0x00
  44. #define TCLKHREG 0x02
  45. #define TCLKCNTLREG 0x04
  46. #define TCLKCNTHREG 0x06
  47. /* RFU */
  48. #define RTCINTREG 0x1e
  49. #define TCLOCK_INT 0x08
  50. #define RTCLONG2_INT 0x04
  51. #define RTCLONG1_INT 0x02
  52. #define ELAPSEDTIME_INT 0x01
  53. #define RTC_FREQUENCY 32768
  54. #define MAX_PERIODIC_RATE 6553
  55. static void __iomem *rtc1_base;
  56. static void __iomem *rtc2_base;
  57. #define rtc1_read(offset) readw(rtc1_base + (offset))
  58. #define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
  59. #define rtc2_read(offset) readw(rtc2_base + (offset))
  60. #define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
  61. /* 32-bit compat for ioctls that nobody else uses */
  62. #define RTC_EPOCH_READ32 _IOR('p', 0x0d, __u32)
  63. static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
  64. static DEFINE_SPINLOCK(rtc_lock);
  65. static char rtc_name[] = "RTC";
  66. static unsigned long periodic_count;
  67. static unsigned int alarm_enabled;
  68. static int aie_irq;
  69. static int pie_irq;
  70. static inline time64_t read_elapsed_second(void)
  71. {
  72. unsigned long first_low, first_mid, first_high;
  73. unsigned long second_low, second_mid, second_high;
  74. do {
  75. first_low = rtc1_read(ETIMELREG);
  76. first_mid = rtc1_read(ETIMEMREG);
  77. first_high = rtc1_read(ETIMEHREG);
  78. second_low = rtc1_read(ETIMELREG);
  79. second_mid = rtc1_read(ETIMEMREG);
  80. second_high = rtc1_read(ETIMEHREG);
  81. } while (first_low != second_low || first_mid != second_mid ||
  82. first_high != second_high);
  83. return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
  84. }
  85. static inline void write_elapsed_second(time64_t sec)
  86. {
  87. spin_lock_irq(&rtc_lock);
  88. rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
  89. rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
  90. rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
  91. spin_unlock_irq(&rtc_lock);
  92. }
  93. static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
  94. {
  95. time64_t epoch_sec, elapsed_sec;
  96. epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
  97. elapsed_sec = read_elapsed_second();
  98. rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
  99. return 0;
  100. }
  101. static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
  102. {
  103. time64_t epoch_sec, current_sec;
  104. epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
  105. current_sec = rtc_tm_to_time64(time);
  106. write_elapsed_second(current_sec - epoch_sec);
  107. return 0;
  108. }
  109. static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  110. {
  111. unsigned long low, mid, high;
  112. struct rtc_time *time = &wkalrm->time;
  113. spin_lock_irq(&rtc_lock);
  114. low = rtc1_read(ECMPLREG);
  115. mid = rtc1_read(ECMPMREG);
  116. high = rtc1_read(ECMPHREG);
  117. wkalrm->enabled = alarm_enabled;
  118. spin_unlock_irq(&rtc_lock);
  119. rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
  120. return 0;
  121. }
  122. static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  123. {
  124. time64_t alarm_sec;
  125. alarm_sec = rtc_tm_to_time64(&wkalrm->time);
  126. spin_lock_irq(&rtc_lock);
  127. if (alarm_enabled)
  128. disable_irq(aie_irq);
  129. rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
  130. rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
  131. rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
  132. if (wkalrm->enabled)
  133. enable_irq(aie_irq);
  134. alarm_enabled = wkalrm->enabled;
  135. spin_unlock_irq(&rtc_lock);
  136. return 0;
  137. }
  138. static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  139. {
  140. switch (cmd) {
  141. case RTC_EPOCH_READ:
  142. return put_user(epoch, (unsigned long __user *)arg);
  143. #ifdef CONFIG_64BIT
  144. case RTC_EPOCH_READ32:
  145. return put_user(epoch, (unsigned int __user *)arg);
  146. #endif
  147. case RTC_EPOCH_SET:
  148. /* Doesn't support before 1900 */
  149. if (arg < 1900)
  150. return -EINVAL;
  151. epoch = arg;
  152. break;
  153. default:
  154. return -ENOIOCTLCMD;
  155. }
  156. return 0;
  157. }
  158. static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  159. {
  160. spin_lock_irq(&rtc_lock);
  161. if (enabled) {
  162. if (!alarm_enabled) {
  163. enable_irq(aie_irq);
  164. alarm_enabled = 1;
  165. }
  166. } else {
  167. if (alarm_enabled) {
  168. disable_irq(aie_irq);
  169. alarm_enabled = 0;
  170. }
  171. }
  172. spin_unlock_irq(&rtc_lock);
  173. return 0;
  174. }
  175. static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
  176. {
  177. struct platform_device *pdev = (struct platform_device *)dev_id;
  178. struct rtc_device *rtc = platform_get_drvdata(pdev);
  179. rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
  180. rtc_update_irq(rtc, 1, RTC_AF);
  181. return IRQ_HANDLED;
  182. }
  183. static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
  184. {
  185. struct platform_device *pdev = (struct platform_device *)dev_id;
  186. struct rtc_device *rtc = platform_get_drvdata(pdev);
  187. unsigned long count = periodic_count;
  188. rtc2_write(RTCINTREG, RTCLONG1_INT);
  189. rtc1_write(RTCL1LREG, count);
  190. rtc1_write(RTCL1HREG, count >> 16);
  191. rtc_update_irq(rtc, 1, RTC_PF);
  192. return IRQ_HANDLED;
  193. }
  194. static const struct rtc_class_ops vr41xx_rtc_ops = {
  195. .ioctl = vr41xx_rtc_ioctl,
  196. .read_time = vr41xx_rtc_read_time,
  197. .set_time = vr41xx_rtc_set_time,
  198. .read_alarm = vr41xx_rtc_read_alarm,
  199. .set_alarm = vr41xx_rtc_set_alarm,
  200. .alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
  201. };
  202. static int rtc_probe(struct platform_device *pdev)
  203. {
  204. struct resource *res;
  205. struct rtc_device *rtc;
  206. int retval;
  207. if (pdev->num_resources != 4)
  208. return -EBUSY;
  209. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  210. if (!res)
  211. return -EBUSY;
  212. rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  213. if (!rtc1_base)
  214. return -EBUSY;
  215. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  216. if (!res) {
  217. retval = -EBUSY;
  218. goto err_rtc1_iounmap;
  219. }
  220. rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  221. if (!rtc2_base) {
  222. retval = -EBUSY;
  223. goto err_rtc1_iounmap;
  224. }
  225. rtc = devm_rtc_allocate_device(&pdev->dev);
  226. if (IS_ERR(rtc)) {
  227. retval = PTR_ERR(rtc);
  228. goto err_iounmap_all;
  229. }
  230. rtc->ops = &vr41xx_rtc_ops;
  231. /* 48-bit counter at 32.768 kHz */
  232. rtc->range_max = (1ULL << 33) - 1;
  233. rtc->max_user_freq = MAX_PERIODIC_RATE;
  234. spin_lock_irq(&rtc_lock);
  235. rtc1_write(ECMPLREG, 0);
  236. rtc1_write(ECMPMREG, 0);
  237. rtc1_write(ECMPHREG, 0);
  238. rtc1_write(RTCL1LREG, 0);
  239. rtc1_write(RTCL1HREG, 0);
  240. spin_unlock_irq(&rtc_lock);
  241. aie_irq = platform_get_irq(pdev, 0);
  242. if (aie_irq <= 0) {
  243. retval = -EBUSY;
  244. goto err_iounmap_all;
  245. }
  246. retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
  247. "elapsed_time", pdev);
  248. if (retval < 0)
  249. goto err_iounmap_all;
  250. pie_irq = platform_get_irq(pdev, 1);
  251. if (pie_irq <= 0) {
  252. retval = -EBUSY;
  253. goto err_iounmap_all;
  254. }
  255. retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
  256. "rtclong1", pdev);
  257. if (retval < 0)
  258. goto err_iounmap_all;
  259. platform_set_drvdata(pdev, rtc);
  260. disable_irq(aie_irq);
  261. disable_irq(pie_irq);
  262. dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
  263. retval = rtc_register_device(rtc);
  264. if (retval)
  265. goto err_iounmap_all;
  266. return 0;
  267. err_iounmap_all:
  268. rtc2_base = NULL;
  269. err_rtc1_iounmap:
  270. rtc1_base = NULL;
  271. return retval;
  272. }
  273. /* work with hotplug and coldplug */
  274. MODULE_ALIAS("platform:RTC");
  275. static struct platform_driver rtc_platform_driver = {
  276. .probe = rtc_probe,
  277. .driver = {
  278. .name = rtc_name,
  279. },
  280. };
  281. module_platform_driver(rtc_platform_driver);