rtc-tps6586x.c 8.3 KB

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  1. /*
  2. * rtc-tps6586x.c: RTC driver for TI PMIC TPS6586X
  3. *
  4. * Copyright (c) 2012, NVIDIA Corporation.
  5. *
  6. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  13. * whether express or implied; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20. * 02111-1307, USA
  21. */
  22. #include <linux/device.h>
  23. #include <linux/err.h>
  24. #include <linux/init.h>
  25. #include <linux/irq.h>
  26. #include <linux/kernel.h>
  27. #include <linux/mfd/tps6586x.h>
  28. #include <linux/module.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pm_runtime.h>
  31. #include <linux/rtc.h>
  32. #include <linux/slab.h>
  33. #define RTC_CTRL 0xc0
  34. #define POR_RESET_N BIT(7)
  35. #define OSC_SRC_SEL BIT(6)
  36. #define RTC_ENABLE BIT(5) /* enables alarm */
  37. #define RTC_BUF_ENABLE BIT(4) /* 32 KHz buffer enable */
  38. #define PRE_BYPASS BIT(3) /* 0=1KHz or 1=32KHz updates */
  39. #define CL_SEL_MASK (BIT(2)|BIT(1))
  40. #define CL_SEL_POS 1
  41. #define RTC_ALARM1_HI 0xc1
  42. #define RTC_COUNT4 0xc6
  43. /* start a PMU RTC access by reading the register prior to the RTC_COUNT4 */
  44. #define RTC_COUNT4_DUMMYREAD 0xc5
  45. /*only 14-bits width in second*/
  46. #define ALM1_VALID_RANGE_IN_SEC 0x3FFF
  47. #define TPS6586X_RTC_CL_SEL_1_5PF 0x0
  48. #define TPS6586X_RTC_CL_SEL_6_5PF 0x1
  49. #define TPS6586X_RTC_CL_SEL_7_5PF 0x2
  50. #define TPS6586X_RTC_CL_SEL_12_5PF 0x3
  51. struct tps6586x_rtc {
  52. struct device *dev;
  53. struct rtc_device *rtc;
  54. int irq;
  55. bool irq_en;
  56. };
  57. static inline struct device *to_tps6586x_dev(struct device *dev)
  58. {
  59. return dev->parent;
  60. }
  61. static int tps6586x_rtc_read_time(struct device *dev, struct rtc_time *tm)
  62. {
  63. struct device *tps_dev = to_tps6586x_dev(dev);
  64. unsigned long long ticks = 0;
  65. time64_t seconds;
  66. u8 buff[6];
  67. int ret;
  68. int i;
  69. ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD, sizeof(buff), buff);
  70. if (ret < 0) {
  71. dev_err(dev, "read counter failed with err %d\n", ret);
  72. return ret;
  73. }
  74. for (i = 1; i < sizeof(buff); i++) {
  75. ticks <<= 8;
  76. ticks |= buff[i];
  77. }
  78. seconds = ticks >> 10;
  79. rtc_time64_to_tm(seconds, tm);
  80. return 0;
  81. }
  82. static int tps6586x_rtc_set_time(struct device *dev, struct rtc_time *tm)
  83. {
  84. struct device *tps_dev = to_tps6586x_dev(dev);
  85. unsigned long long ticks;
  86. time64_t seconds;
  87. u8 buff[5];
  88. int ret;
  89. seconds = rtc_tm_to_time64(tm);
  90. ticks = (unsigned long long)seconds << 10;
  91. buff[0] = (ticks >> 32) & 0xff;
  92. buff[1] = (ticks >> 24) & 0xff;
  93. buff[2] = (ticks >> 16) & 0xff;
  94. buff[3] = (ticks >> 8) & 0xff;
  95. buff[4] = ticks & 0xff;
  96. /* Disable RTC before changing time */
  97. ret = tps6586x_clr_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
  98. if (ret < 0) {
  99. dev_err(dev, "failed to clear RTC_ENABLE\n");
  100. return ret;
  101. }
  102. ret = tps6586x_writes(tps_dev, RTC_COUNT4, sizeof(buff), buff);
  103. if (ret < 0) {
  104. dev_err(dev, "failed to program new time\n");
  105. return ret;
  106. }
  107. /* Enable RTC */
  108. ret = tps6586x_set_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
  109. if (ret < 0) {
  110. dev_err(dev, "failed to set RTC_ENABLE\n");
  111. return ret;
  112. }
  113. return 0;
  114. }
  115. static int tps6586x_rtc_alarm_irq_enable(struct device *dev,
  116. unsigned int enabled)
  117. {
  118. struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
  119. if (enabled && !rtc->irq_en) {
  120. enable_irq(rtc->irq);
  121. rtc->irq_en = true;
  122. } else if (!enabled && rtc->irq_en) {
  123. disable_irq(rtc->irq);
  124. rtc->irq_en = false;
  125. }
  126. return 0;
  127. }
  128. static int tps6586x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  129. {
  130. struct device *tps_dev = to_tps6586x_dev(dev);
  131. time64_t seconds;
  132. unsigned long ticks;
  133. unsigned long rtc_current_time;
  134. unsigned long long rticks = 0;
  135. u8 buff[3];
  136. u8 rbuff[6];
  137. int ret;
  138. int i;
  139. seconds = rtc_tm_to_time64(&alrm->time);
  140. ret = tps6586x_rtc_alarm_irq_enable(dev, alrm->enabled);
  141. if (ret < 0) {
  142. dev_err(dev, "can't set alarm irq, err %d\n", ret);
  143. return ret;
  144. }
  145. ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD,
  146. sizeof(rbuff), rbuff);
  147. if (ret < 0) {
  148. dev_err(dev, "read counter failed with err %d\n", ret);
  149. return ret;
  150. }
  151. for (i = 1; i < sizeof(rbuff); i++) {
  152. rticks <<= 8;
  153. rticks |= rbuff[i];
  154. }
  155. rtc_current_time = rticks >> 10;
  156. if ((seconds - rtc_current_time) > ALM1_VALID_RANGE_IN_SEC)
  157. seconds = rtc_current_time - 1;
  158. ticks = (unsigned long long)seconds << 10;
  159. buff[0] = (ticks >> 16) & 0xff;
  160. buff[1] = (ticks >> 8) & 0xff;
  161. buff[2] = ticks & 0xff;
  162. ret = tps6586x_writes(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
  163. if (ret)
  164. dev_err(dev, "programming alarm failed with err %d\n", ret);
  165. return ret;
  166. }
  167. static int tps6586x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  168. {
  169. struct device *tps_dev = to_tps6586x_dev(dev);
  170. unsigned long ticks;
  171. time64_t seconds;
  172. u8 buff[3];
  173. int ret;
  174. ret = tps6586x_reads(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
  175. if (ret) {
  176. dev_err(dev, "read RTC_ALARM1_HI failed with err %d\n", ret);
  177. return ret;
  178. }
  179. ticks = (buff[0] << 16) | (buff[1] << 8) | buff[2];
  180. seconds = ticks >> 10;
  181. rtc_time64_to_tm(seconds, &alrm->time);
  182. return 0;
  183. }
  184. static const struct rtc_class_ops tps6586x_rtc_ops = {
  185. .read_time = tps6586x_rtc_read_time,
  186. .set_time = tps6586x_rtc_set_time,
  187. .set_alarm = tps6586x_rtc_set_alarm,
  188. .read_alarm = tps6586x_rtc_read_alarm,
  189. .alarm_irq_enable = tps6586x_rtc_alarm_irq_enable,
  190. };
  191. static irqreturn_t tps6586x_rtc_irq(int irq, void *data)
  192. {
  193. struct tps6586x_rtc *rtc = data;
  194. rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
  195. return IRQ_HANDLED;
  196. }
  197. static int tps6586x_rtc_probe(struct platform_device *pdev)
  198. {
  199. struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
  200. struct tps6586x_rtc *rtc;
  201. int ret;
  202. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  203. if (!rtc)
  204. return -ENOMEM;
  205. rtc->dev = &pdev->dev;
  206. rtc->irq = platform_get_irq(pdev, 0);
  207. /* 1 kHz tick mode, enable tick counting */
  208. ret = tps6586x_update(tps_dev, RTC_CTRL,
  209. RTC_ENABLE | OSC_SRC_SEL |
  210. ((TPS6586X_RTC_CL_SEL_1_5PF << CL_SEL_POS) & CL_SEL_MASK),
  211. RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
  212. if (ret < 0) {
  213. dev_err(&pdev->dev, "unable to start counter\n");
  214. return ret;
  215. }
  216. device_init_wakeup(&pdev->dev, 1);
  217. platform_set_drvdata(pdev, rtc);
  218. rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
  219. if (IS_ERR(rtc->rtc)) {
  220. ret = PTR_ERR(rtc->rtc);
  221. goto fail_rtc_register;
  222. }
  223. rtc->rtc->ops = &tps6586x_rtc_ops;
  224. rtc->rtc->range_max = (1ULL << 30) - 1; /* 30-bit seconds */
  225. rtc->rtc->start_secs = mktime64(2009, 1, 1, 0, 0, 0);
  226. rtc->rtc->set_start_time = true;
  227. irq_set_status_flags(rtc->irq, IRQ_NOAUTOEN);
  228. ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
  229. tps6586x_rtc_irq,
  230. IRQF_ONESHOT,
  231. dev_name(&pdev->dev), rtc);
  232. if (ret < 0) {
  233. dev_err(&pdev->dev, "request IRQ(%d) failed with ret %d\n",
  234. rtc->irq, ret);
  235. goto fail_rtc_register;
  236. }
  237. ret = rtc_register_device(rtc->rtc);
  238. if (ret)
  239. goto fail_rtc_register;
  240. return 0;
  241. fail_rtc_register:
  242. tps6586x_update(tps_dev, RTC_CTRL, 0,
  243. RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
  244. return ret;
  245. };
  246. static int tps6586x_rtc_remove(struct platform_device *pdev)
  247. {
  248. struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
  249. tps6586x_update(tps_dev, RTC_CTRL, 0,
  250. RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
  251. return 0;
  252. }
  253. #ifdef CONFIG_PM_SLEEP
  254. static int tps6586x_rtc_suspend(struct device *dev)
  255. {
  256. struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
  257. if (device_may_wakeup(dev))
  258. enable_irq_wake(rtc->irq);
  259. return 0;
  260. }
  261. static int tps6586x_rtc_resume(struct device *dev)
  262. {
  263. struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
  264. if (device_may_wakeup(dev))
  265. disable_irq_wake(rtc->irq);
  266. return 0;
  267. }
  268. #endif
  269. static SIMPLE_DEV_PM_OPS(tps6586x_pm_ops, tps6586x_rtc_suspend,
  270. tps6586x_rtc_resume);
  271. static struct platform_driver tps6586x_rtc_driver = {
  272. .driver = {
  273. .name = "tps6586x-rtc",
  274. .pm = &tps6586x_pm_ops,
  275. },
  276. .probe = tps6586x_rtc_probe,
  277. .remove = tps6586x_rtc_remove,
  278. };
  279. module_platform_driver(tps6586x_rtc_driver);
  280. MODULE_ALIAS("platform:tps6586x-rtc");
  281. MODULE_DESCRIPTION("TI TPS6586x RTC driver");
  282. MODULE_AUTHOR("Laxman dewangan <ldewangan@nvidia.com>");
  283. MODULE_LICENSE("GPL v2");