rtc-tegra.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
  4. *
  5. * Copyright (c) 2010-2019, NVIDIA Corporation.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/irq.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/mod_devicetable.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm.h>
  17. #include <linux/rtc.h>
  18. #include <linux/slab.h>
  19. /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
  20. #define TEGRA_RTC_REG_BUSY 0x004
  21. #define TEGRA_RTC_REG_SECONDS 0x008
  22. /* When msec is read, the seconds are buffered into shadow seconds. */
  23. #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
  24. #define TEGRA_RTC_REG_MILLI_SECONDS 0x010
  25. #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
  26. #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
  27. #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
  28. #define TEGRA_RTC_REG_INTR_MASK 0x028
  29. /* write 1 bits to clear status bits */
  30. #define TEGRA_RTC_REG_INTR_STATUS 0x02c
  31. /* bits in INTR_MASK */
  32. #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
  33. #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
  34. #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
  35. #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
  36. #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
  37. /* bits in INTR_STATUS */
  38. #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
  39. #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
  40. #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
  41. #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
  42. #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
  43. struct tegra_rtc_info {
  44. struct platform_device *pdev;
  45. struct rtc_device *rtc;
  46. void __iomem *base; /* NULL if not initialized */
  47. struct clk *clk;
  48. int irq; /* alarm and periodic IRQ */
  49. spinlock_t lock;
  50. };
  51. /*
  52. * RTC hardware is busy when it is updating its values over AHB once every
  53. * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
  54. * write. CPU is always free to read.
  55. */
  56. static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
  57. {
  58. return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
  59. }
  60. /*
  61. * Wait for hardware to be ready for writing. This function tries to maximize
  62. * the amount of time before the next update. It does this by waiting for the
  63. * RTC to become busy with its periodic update, then returning once the RTC
  64. * first becomes not busy.
  65. *
  66. * This periodic update (where the seconds and milliseconds are copied to the
  67. * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
  68. * function allows us to make some assumptions without introducing a race,
  69. * because 250 us is plenty of time to read/write a value.
  70. */
  71. static int tegra_rtc_wait_while_busy(struct device *dev)
  72. {
  73. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  74. int retries = 500; /* ~490 us is the worst case, ~250 us is best */
  75. /*
  76. * First wait for the RTC to become busy. This is when it posts its
  77. * updated seconds+msec registers to AHB side.
  78. */
  79. while (tegra_rtc_check_busy(info)) {
  80. if (!retries--)
  81. goto retry_failed;
  82. udelay(1);
  83. }
  84. /* now we have about 250 us to manipulate registers */
  85. return 0;
  86. retry_failed:
  87. dev_err(dev, "write failed: retry count exceeded\n");
  88. return -ETIMEDOUT;
  89. }
  90. static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
  91. {
  92. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  93. unsigned long flags;
  94. u32 sec;
  95. /*
  96. * RTC hardware copies seconds to shadow seconds when a read of
  97. * milliseconds occurs. use a lock to keep other threads out.
  98. */
  99. spin_lock_irqsave(&info->lock, flags);
  100. readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
  101. sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
  102. spin_unlock_irqrestore(&info->lock, flags);
  103. rtc_time64_to_tm(sec, tm);
  104. dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
  105. return 0;
  106. }
  107. static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
  108. {
  109. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  110. u32 sec;
  111. int ret;
  112. /* convert tm to seconds */
  113. sec = rtc_tm_to_time64(tm);
  114. dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
  115. /* seconds only written if wait succeeded */
  116. ret = tegra_rtc_wait_while_busy(dev);
  117. if (!ret)
  118. writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
  119. dev_vdbg(dev, "time read back as %d\n",
  120. readl(info->base + TEGRA_RTC_REG_SECONDS));
  121. return ret;
  122. }
  123. static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  124. {
  125. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  126. u32 sec, value;
  127. sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
  128. if (sec == 0) {
  129. /* alarm is disabled */
  130. alarm->enabled = 0;
  131. } else {
  132. /* alarm is enabled */
  133. alarm->enabled = 1;
  134. rtc_time64_to_tm(sec, &alarm->time);
  135. }
  136. value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
  137. alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
  138. return 0;
  139. }
  140. static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  141. {
  142. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  143. unsigned long flags;
  144. u32 status;
  145. tegra_rtc_wait_while_busy(dev);
  146. spin_lock_irqsave(&info->lock, flags);
  147. /* read the original value, and OR in the flag */
  148. status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
  149. if (enabled)
  150. status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
  151. else
  152. status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
  153. writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
  154. spin_unlock_irqrestore(&info->lock, flags);
  155. return 0;
  156. }
  157. static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  158. {
  159. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  160. u32 sec;
  161. if (alarm->enabled)
  162. sec = rtc_tm_to_time64(&alarm->time);
  163. else
  164. sec = 0;
  165. tegra_rtc_wait_while_busy(dev);
  166. writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
  167. dev_vdbg(dev, "alarm read back as %d\n",
  168. readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
  169. /* if successfully written and alarm is enabled ... */
  170. if (sec) {
  171. tegra_rtc_alarm_irq_enable(dev, 1);
  172. dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
  173. } else {
  174. /* disable alarm if 0 or write error */
  175. dev_vdbg(dev, "alarm disabled\n");
  176. tegra_rtc_alarm_irq_enable(dev, 0);
  177. }
  178. return 0;
  179. }
  180. static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
  181. {
  182. if (!dev || !dev->driver)
  183. return 0;
  184. seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
  185. return 0;
  186. }
  187. static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
  188. {
  189. struct device *dev = data;
  190. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  191. unsigned long events = 0, flags;
  192. u32 status;
  193. status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
  194. if (status) {
  195. /* clear the interrupt masks and status on any IRQ */
  196. tegra_rtc_wait_while_busy(dev);
  197. spin_lock_irqsave(&info->lock, flags);
  198. writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
  199. writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
  200. spin_unlock_irqrestore(&info->lock, flags);
  201. }
  202. /* check if alarm */
  203. if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
  204. events |= RTC_IRQF | RTC_AF;
  205. /* check if periodic */
  206. if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
  207. events |= RTC_IRQF | RTC_PF;
  208. rtc_update_irq(info->rtc, 1, events);
  209. return IRQ_HANDLED;
  210. }
  211. static const struct rtc_class_ops tegra_rtc_ops = {
  212. .read_time = tegra_rtc_read_time,
  213. .set_time = tegra_rtc_set_time,
  214. .read_alarm = tegra_rtc_read_alarm,
  215. .set_alarm = tegra_rtc_set_alarm,
  216. .proc = tegra_rtc_proc,
  217. .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
  218. };
  219. static const struct of_device_id tegra_rtc_dt_match[] = {
  220. { .compatible = "nvidia,tegra20-rtc", },
  221. {}
  222. };
  223. MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
  224. static int tegra_rtc_probe(struct platform_device *pdev)
  225. {
  226. struct tegra_rtc_info *info;
  227. int ret;
  228. info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
  229. if (!info)
  230. return -ENOMEM;
  231. info->base = devm_platform_ioremap_resource(pdev, 0);
  232. if (IS_ERR(info->base))
  233. return PTR_ERR(info->base);
  234. ret = platform_get_irq(pdev, 0);
  235. if (ret <= 0)
  236. return ret;
  237. info->irq = ret;
  238. info->rtc = devm_rtc_allocate_device(&pdev->dev);
  239. if (IS_ERR(info->rtc))
  240. return PTR_ERR(info->rtc);
  241. info->rtc->ops = &tegra_rtc_ops;
  242. info->rtc->range_max = U32_MAX;
  243. info->clk = devm_clk_get(&pdev->dev, NULL);
  244. if (IS_ERR(info->clk))
  245. return PTR_ERR(info->clk);
  246. ret = clk_prepare_enable(info->clk);
  247. if (ret < 0)
  248. return ret;
  249. /* set context info */
  250. info->pdev = pdev;
  251. spin_lock_init(&info->lock);
  252. platform_set_drvdata(pdev, info);
  253. /* clear out the hardware */
  254. writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
  255. writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
  256. writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
  257. device_init_wakeup(&pdev->dev, 1);
  258. ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
  259. IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
  260. &pdev->dev);
  261. if (ret) {
  262. dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
  263. goto disable_clk;
  264. }
  265. ret = rtc_register_device(info->rtc);
  266. if (ret)
  267. goto disable_clk;
  268. dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
  269. return 0;
  270. disable_clk:
  271. clk_disable_unprepare(info->clk);
  272. return ret;
  273. }
  274. static int tegra_rtc_remove(struct platform_device *pdev)
  275. {
  276. struct tegra_rtc_info *info = platform_get_drvdata(pdev);
  277. clk_disable_unprepare(info->clk);
  278. return 0;
  279. }
  280. #ifdef CONFIG_PM_SLEEP
  281. static int tegra_rtc_suspend(struct device *dev)
  282. {
  283. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  284. tegra_rtc_wait_while_busy(dev);
  285. /* only use ALARM0 as a wake source */
  286. writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
  287. writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
  288. info->base + TEGRA_RTC_REG_INTR_MASK);
  289. dev_vdbg(dev, "alarm sec = %d\n",
  290. readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
  291. dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
  292. device_may_wakeup(dev), info->irq);
  293. /* leave the alarms on as a wake source */
  294. if (device_may_wakeup(dev))
  295. enable_irq_wake(info->irq);
  296. return 0;
  297. }
  298. static int tegra_rtc_resume(struct device *dev)
  299. {
  300. struct tegra_rtc_info *info = dev_get_drvdata(dev);
  301. dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
  302. device_may_wakeup(dev));
  303. /* alarms were left on as a wake source, turn them off */
  304. if (device_may_wakeup(dev))
  305. disable_irq_wake(info->irq);
  306. return 0;
  307. }
  308. #endif
  309. static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
  310. static void tegra_rtc_shutdown(struct platform_device *pdev)
  311. {
  312. dev_vdbg(&pdev->dev, "disabling interrupts\n");
  313. tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
  314. }
  315. static struct platform_driver tegra_rtc_driver = {
  316. .probe = tegra_rtc_probe,
  317. .remove = tegra_rtc_remove,
  318. .shutdown = tegra_rtc_shutdown,
  319. .driver = {
  320. .name = "tegra_rtc",
  321. .of_match_table = tegra_rtc_dt_match,
  322. .pm = &tegra_rtc_pm_ops,
  323. },
  324. };
  325. module_platform_driver(tegra_rtc_driver);
  326. MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
  327. MODULE_DESCRIPTION("driver for Tegra internal RTC");
  328. MODULE_LICENSE("GPL");